octeontx2-af: Extend debugfs support for cn20k NPA

Extend debugfs to display CN20K NPA aura and pool contexts.

Signed-off-by: Linu Cherian <lcherian@marvell.com>
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Link: https://patch.msgid.link/1761388367-16579-6-git-send-email-sbhatta@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c
index 50b1bd1d2c865ae4bd8ab2ba71277e88bc157df9..498968bf4cf59dbed308b10260e0492107048015 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c
@@ -132,3 +132,87 @@ void print_nix_cn20k_cq_ctx(struct seq_file *m,
        seq_printf(m, "W4: lbpid_ext \t\t\t\t%d\n\n", cq_ctx->lbpid_ext);
        seq_printf(m, "W4: bpid_ext \t\t\t\t%d\n\n", cq_ctx->bpid_ext);
 }
+
+void print_npa_cn20k_aura_ctx(struct seq_file *m,
+                             struct npa_cn20k_aq_enq_rsp *rsp)
+{
+       struct npa_cn20k_aura_s *aura = &rsp->aura;
+
+       seq_printf(m, "W0: Pool addr\t\t%llx\n", aura->pool_addr);
+
+       seq_printf(m, "W1: ena\t\t\t%d\nW1: pool caching\t%d\n",
+                  aura->ena, aura->pool_caching);
+       seq_printf(m, "W1: avg con\t\t%d\n", aura->avg_con);
+       seq_printf(m, "W1: pool drop ena\t%d\nW1: aura drop ena\t%d\n",
+                  aura->pool_drop_ena, aura->aura_drop_ena);
+       seq_printf(m, "W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\n",
+                  aura->bp_ena, aura->aura_drop);
+       seq_printf(m, "W1: aura shift\t\t%d\nW1: avg_level\t\t%d\n",
+                  aura->shift, aura->avg_level);
+
+       seq_printf(m, "W2: count\t\t%llu\nW2: nix_bpid\t\t%d\n",
+                  (u64)aura->count, aura->bpid);
+
+       seq_printf(m, "W3: limit\t\t%llu\nW3: bp\t\t\t%d\nW3: fc_ena\t\t%d\n",
+                  (u64)aura->limit, aura->bp, aura->fc_ena);
+
+       seq_printf(m, "W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d\n",
+                  aura->fc_up_crossing, aura->fc_stype);
+       seq_printf(m, "W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits);
+
+       seq_printf(m, "W4: fc_addr\t\t%llx\n", aura->fc_addr);
+
+       seq_printf(m, "W5: pool_drop\t\t%d\nW5: update_time\t\t%d\n",
+                  aura->pool_drop, aura->update_time);
+       seq_printf(m, "W5: err_int \t\t%d\nW5: err_int_ena\t\t%d\n",
+                  aura->err_int, aura->err_int_ena);
+       seq_printf(m, "W5: thresh_int\t\t%d\nW5: thresh_int_ena \t%d\n",
+                  aura->thresh_int, aura->thresh_int_ena);
+       seq_printf(m, "W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d\n",
+                  aura->thresh_up, aura->thresh_qint_idx);
+       seq_printf(m, "W5: err_qint_idx \t%d\n", aura->err_qint_idx);
+
+       seq_printf(m, "W6: thresh\t\t%llu\n", (u64)aura->thresh);
+       seq_printf(m, "W6: fc_msh_dst\t\t%d\n", aura->fc_msh_dst);
+}
+
+void print_npa_cn20k_pool_ctx(struct seq_file *m,
+                             struct npa_cn20k_aq_enq_rsp *rsp)
+{
+       struct npa_cn20k_pool_s *pool = &rsp->pool;
+
+       seq_printf(m, "W0: Stack base\t\t%llx\n", pool->stack_base);
+
+       seq_printf(m, "W1: ena \t\t%d\nW1: nat_align \t\t%d\n",
+                  pool->ena, pool->nat_align);
+       seq_printf(m, "W1: stack_caching\t%d\n",
+                  pool->stack_caching);
+       seq_printf(m, "W1: buf_offset\t\t%d\nW1: buf_size\t\t%d\n",
+                  pool->buf_offset, pool->buf_size);
+
+       seq_printf(m, "W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n",
+                  pool->stack_max_pages, pool->stack_pages);
+
+       seq_printf(m, "W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d\n",
+                  pool->stack_offset, pool->shift, pool->avg_level);
+       seq_printf(m, "W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d\n",
+                  pool->avg_con, pool->fc_ena, pool->fc_stype);
+       seq_printf(m, "W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d\n",
+                  pool->fc_hyst_bits, pool->fc_up_crossing);
+       seq_printf(m, "W4: update_time\t\t%d\n", pool->update_time);
+
+       seq_printf(m, "W5: fc_addr\t\t%llx\n", pool->fc_addr);
+
+       seq_printf(m, "W6: ptr_start\t\t%llx\n", pool->ptr_start);
+
+       seq_printf(m, "W7: ptr_end\t\t%llx\n", pool->ptr_end);
+
+       seq_printf(m, "W8: err_int\t\t%d\nW8: err_int_ena\t\t%d\n",
+                  pool->err_int, pool->err_int_ena);
+       seq_printf(m, "W8: thresh_int\t\t%d\n", pool->thresh_int);
+       seq_printf(m, "W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d\n",
+                  pool->thresh_int_ena, pool->thresh_up);
+       seq_printf(m, "W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n",
+                  pool->thresh_qint_idx, pool->err_qint_idx);
+       seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst);
+}

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h
index 9d3a98dc300050b265f4d2b3f38ea57711d75047..a2e3a2cd6edb308669e0b5c8bf7ba9731038c4a9 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h
@@ -20,5 +20,9 @@ void print_nix_cn20k_sq_ctx(struct seq_file *m,
                            struct nix_cn20k_sq_ctx_s *sq_ctx);
 void print_nix_cn20k_cq_ctx(struct seq_file *m,
                            struct nix_cn20k_aq_enq_rsp *rsp);
+void print_npa_cn20k_aura_ctx(struct seq_file *m,
+                             struct npa_cn20k_aq_enq_rsp *rsp);
+void print_npa_cn20k_pool_ctx(struct seq_file *m,
+                             struct npa_cn20k_aq_enq_rsp *rsp);
 
 #endif

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
index eeca8cef79648b8ac8093856d8d782bcaa84e1c9..c55a0f15380d00583db1854bc740c00973ea22f1 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
@@ -1103,6 +1103,11 @@ static void print_npa_aura_ctx(struct seq_file *m, struct npa_aq_enq_rsp *rsp)
        struct npa_aura_s *aura = &rsp->aura;
        struct rvu *rvu = m->private;
 
+       if (is_cn20k(rvu->pdev)) {
+               print_npa_cn20k_aura_ctx(m, (struct npa_cn20k_aq_enq_rsp *)rsp);
+               return;
+       }
+
        seq_printf(m, "W0: Pool addr\t\t%llx\n", aura->pool_addr);
 
        seq_printf(m, "W1: ena\t\t\t%d\nW1: pool caching\t%d\n",
@@ -1151,6 +1156,11 @@ static void print_npa_pool_ctx(struct seq_file *m, struct npa_aq_enq_rsp *rsp)
        struct npa_pool_s *pool = &rsp->pool;
        struct rvu *rvu = m->private;
 
+       if (is_cn20k(rvu->pdev)) {
+               print_npa_cn20k_pool_ctx(m, (struct npa_cn20k_aq_enq_rsp *)rsp);
+               return;
+       }
+
        seq_printf(m, "W0: Stack base\t\t%llx\n", pool->stack_base);
 
        seq_printf(m, "W1: ena \t\t%d\nW1: nat_align \t\t%d\n",