]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: ti: am62-lp-sk: Add overlay for NAND expansion card
authorRoger Quadros <rogerq@kernel.org>
Sat, 22 Jun 2024 11:59:57 +0000 (14:59 +0300)
committerVignesh Raghavendra <vigneshr@ti.com>
Mon, 1 Jul 2024 16:06:06 +0000 (21:36 +0530)
The NAND expansion card (PROC143E1) connects over the User/MCU/PRU
Expansion port on the am62-lp-sk EVM.

The following pins are shared between McASP1 and GPMC-NAND so
both cannot work simultaneously.

Pin name McASP1 function GPMC function
======== =============== =============
J17 MCASP1_AXR0 GPMC0_WEN
P21 MCASP1_AFSX GPMC0_WAIT0
K17 MCASP1_ACLKX GPMC0_BE0N_CLE
K20 MCASP1_AXR2 GPMC0_ADVN_ALE

The factory default sets the pins for McASP1 use. (i.e.
Resistor Array RA1 installed, RA4 not installed).

For NAND use, RA1 has to be removed and RA4 must be
installed.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240622-am62lp-sk-nand-v1-2-caee496eaf42@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/Makefile
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso [new file with mode: 0644]
arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts

index cebc7bade968d74935972404379fba09d8b2bc6e..c11b0acd2134bb76ac7c9ed500f97f32852da598 100644 (file)
@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
 
 # Boards with AM62Ax SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso b/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
new file mode 100644 (file)
index 0000000..173ac60
--- /dev/null
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "k3-pinctrl.h"
+
+&mcasp1 {
+       status = "disabled";
+};
+
+&main_pmx0 {
+       gpmc0_pins_default: gpmc0-pins-default {
+               pinctrl-single,pins = <
+                       AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
+                       AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
+                       AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
+                       AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
+                       AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
+                       AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
+                       AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
+                       AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */
+                       AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
+                       AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
+                       AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */
+                       AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */
+                       AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */
+                       AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */
+                       AM62X_IOPAD(0x00a0, PIN_OUTPUT, 0) /* (J20) GPMC0_WPn */
+               >;
+       };
+};
+
+&elm0 {
+       status = "okay";
+};
+
+&gpmc0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&gpmc0_pins_default>;
+       #address-cells = <2>;
+       #size-cells = <1>;
+
+       nand@0,0 {
+               compatible = "ti,am64-nand";
+               reg = <0 0 64>;         /* device IO registers */
+               interrupt-parent = <&gpmc0>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+               ti,nand-xfer-type = "prefetch-polled";
+               ti,nand-ecc-opt = "bch8";       /* BCH8: Bootrom limitation */
+               ti,elm-id = <&elm0>;
+               nand-bus-width = <8>;
+               gpmc,device-width = <1>;
+               gpmc,sync-clk-ps = <0>;
+               gpmc,cs-on-ns = <0>;
+               gpmc,cs-rd-off-ns = <40>;
+               gpmc,cs-wr-off-ns = <40>;
+               gpmc,adv-on-ns = <0>;
+               gpmc,adv-rd-off-ns = <25>;
+               gpmc,adv-wr-off-ns = <25>;
+               gpmc,we-on-ns = <0>;
+               gpmc,we-off-ns = <20>;
+               gpmc,oe-on-ns = <3>;
+               gpmc,oe-off-ns = <30>;
+               gpmc,access-ns = <30>;
+               gpmc,rd-cycle-ns = <40>;
+               gpmc,wr-cycle-ns = <40>;
+               gpmc,bus-turnaround-ns = <0>;
+               gpmc,cycle2cycle-delay-ns = <0>;
+               gpmc,clk-activation-ns = <0>;
+               gpmc,wr-access-ns = <40>;
+               gpmc,wr-data-mux-bus-ns = <0>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "NAND.tiboot3";
+                               reg = <0x00000000 0x00200000>;  /* 2M */
+                       };
+                       partition@200000 {
+                               label = "NAND.tispl";
+                               reg = <0x00200000 0x00200000>;  /* 2M */
+                       };
+                       partition@400000 {
+                               label = "NAND.tiboot3.backup";  /* 2M */
+                               reg = <0x00400000 0x00200000>;  /* BootROM looks at 4M */
+                       };
+                       partition@600000 {
+                               label = "NAND.u-boot";
+                               reg = <0x00600000 0x00400000>;  /* 4M */
+                       };
+                       partition@a00000 {
+                               label = "NAND.u-boot-env";
+                               reg = <0x00a00000 0x00040000>;  /* 256K */
+                       };
+                       partition@a40000 {
+                               label = "NAND.u-boot-env.backup";
+                               reg = <0x00a40000 0x00040000>;  /* 256K */
+                       };
+                       partition@a80000 {
+                               label = "NAND.file-system";
+                               reg = <0x00a80000 0x3f580000>;
+                       };
+               };
+       };
+};
index 9a17bd3e59c90f69c4465225e158dacb33db8abc..8e9fc00a6b3c7459a360f9e1d6bbb60e68c460ab 100644 (file)
 &tlv320aic3106 {
        DVDD-supply = <&buck2_reg>;
 };
+
+&gpmc0 {
+       ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
+};