RISC-V: Error early with V and no M extension.

For calculating the value of a poly_int at runtime we use a
multiplication instruction that requires the M extension.
Instead of just asserting and ICEing this patch emits an early
error at option-parsing time.

gcc/ChangeLog:

	PR target/116036

	* config/riscv/riscv.cc (riscv_override_options_internal): Error
	with TARGET_VECTOR && !TARGET_MUL.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-31.c: Add m to arch string and expect it.
	* gcc.target/riscv/arch-32.c: Ditto.
	* gcc.target/riscv/arch-37.c: Ditto.
	* gcc.target/riscv/arch-38.c: Ditto.
	* gcc.target/riscv/predef-14.c: Ditto.
	* gcc.target/riscv/predef-15.c: Ditto.
	* gcc.target/riscv/predef-16.c: Ditto.
	* gcc.target/riscv/predef-26.c: Ditto.
	* gcc.target/riscv/predef-27.c: Ditto.
	* gcc.target/riscv/predef-32.c: Ditto.
	* gcc.target/riscv/predef-33.c: Ditto.
	* gcc.target/riscv/predef-36.c: Ditto.
	* gcc.target/riscv/predef-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/pr111486.c: Add m to arch string.
	* gcc.target/riscv/compare-debug-1.c: Ditto.
	* gcc.target/riscv/compare-debug-2.c: Ditto.
	* gcc.target/riscv/rvv/base/pr116036.c: New test.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 96c4ab6dddd5c5bb6dca9d8d665e876f77a38fef..2bb7f2aace1b16fe7cab1eb19921bbb7d0774141 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9691,6 +9691,11 @@ riscv_override_options_internal (struct gcc_options *opts)
   else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts))
     error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
 
+  /* We might use a multiplication to calculate the scalable vector length at
+     runtime.  Therefore, require the M extension.  */
+  if (TARGET_VECTOR && !TARGET_MUL)
+    sorry ("GCC's current %<V%> implementation requires the %<M%> extension");
+
   /* Likewise floating-point division and square root.  */
   if ((TARGET_HARD_FLOAT_OPTS_P (opts) || TARGET_ZFINX_OPTS_P (opts))
       && ((target_flags_explicit & MASK_FDIV) == 0))

diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c b/gcc/testsuite/gcc.target/riscv/arch-31.c
index 5180753b9057fcf2664a53240dce3fb794f84245..9b867c5ecd20ce21ff623a3eec547b187ab68662 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/arch-31.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-31.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */
+/* { dg-options "-march=rv32im_zvfbfmin -mabi=ilp32f" } */
 int foo()
 {
 }

diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c b/gcc/testsuite/gcc.target/riscv/arch-32.c
index 49616832512977113db155a132e54421faa88557..49a3db794892dd5f6a331a43b3627bd4a08ce2af 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/arch-32.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */
+/* { dg-options "-march=rv64imv_zvfbfmin -mabi=lp64d" } */
 int foo()
 {
 }

diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c b/gcc/testsuite/gcc.target/riscv/arch-37.c
index 5b19a73c55677e658acbe9ddf0a6d042ab5611b1..b56ba77b973eef512f467d2601236935b1570428 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/arch-37.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-37.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */
+/* { dg-options "-march=rv32im_zvfbfwma -mabi=ilp32f" } */
 int
 foo ()
 {}

diff --git a/gcc/testsuite/gcc.target/riscv/arch-38.c b/gcc/testsuite/gcc.target/riscv/arch-38.c
index cee3efebe75350642f1036285a6a7f533ff36c32..164a91e38a3bb9abe2c88bead63e98c7ca1fbe56 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/arch-38.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-38.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64iv_zvfbfwma -mabi=lp64d" } */
+/* { dg-options "-march=rv64imv_zvfbfwma -mabi=lp64d" } */
 int
 foo ()
 {}

diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-1.c b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c
index d65bb287b9a7e233fe3e75f58b7077e9413ad9a1..c22e967f03d0716319aeb6fb300eede43accb1ab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/compare-debug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64iv -mabi=lp64d -fcompare-debug" } */
+/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64imv -mabi=lp64d -fcompare-debug" } */
 
 
 void

diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-2.c b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c
index d87758475e46033cec5fc1735ab958f8df22ee8f..be9bda17b59a1345b802f24bf288634b28d20856 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/compare-debug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c
@@ -1,3 +1,3 @@
 /* { dg-do compile } */
-/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64iv -mabi=lp64d -fno-dce -fschedule-insns -fcompare-debug" } */
+/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64imv -mabi=lp64d -fno-dce -fschedule-insns -fcompare-debug" } */
 #include "compare-debug-1.c"

diff --git a/gcc/testsuite/gcc.target/riscv/predef-14.c b/gcc/testsuite/gcc.target/riscv/predef-14.c
index 4815150ddfae541efe9e12f8acecd34b15c21955..138209a0169579515024f20ca56cb829d7b92770 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-14.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv32imv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
@@ -27,8 +27,8 @@ int main () {
 #error "__riscv_a"
 #endif
 
-#if defined(__riscv_m)
-#error "__riscv_m"
+#if !defined(__riscv_mul)
+#error "__riscv_mul"
 #endif
 
 #if !defined(__riscv_f)

diff --git a/gcc/testsuite/gcc.target/riscv/predef-15.c b/gcc/testsuite/gcc.target/riscv/predef-15.c
index dad14952ade088a7d3c12db61c47b40dd24a3d96..fd119dc7492e91edfe0f538168a7f4439ab7ee15 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-15.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv64imv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
@@ -27,7 +27,7 @@ int main () {
 #error "__riscv_a"
 #endif
 
-#if defined(__riscv_m)
+#if !defined(__riscv_m)
 #error "__riscv_m"
 #endif
 

diff --git a/gcc/testsuite/gcc.target/riscv/predef-16.c b/gcc/testsuite/gcc.target/riscv/predef-16.c
index faebc1ab4f25a273d3b477a0b193080750206bd4..d64b8dc56ebd41fbbe9d80de6baad1f79408dbf2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-16.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv64im_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
@@ -27,7 +27,7 @@ int main () {
 #error "__riscv_a"
 #endif
 
-#if defined(__riscv_m)
+#if !defined(__riscv_m)
 #error "__riscv_m"
 #endif
 

diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c
index 285f64bd6c0fcef5c372b17ad61ba07c08e9d3a3..df0f05e4550698aa6109b4aba08fac1958e0f0fd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-26.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
+/* { dg-options "-O2 -march=rv64im_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
 
 int main () {
 
@@ -15,6 +15,10 @@ int main () {
 #error "__riscv_i"
 #endif
 
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
 #if !defined(__riscv_f)
 #error "__riscv_f"
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c b/gcc/testsuite/gcc.target/riscv/predef-27.c
index 0f9ab4417a6642932cdb000b4da25f68cb8c10ba..554acf36e5c5ea7f39b1bd8399e840ce9f2f36f7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-27.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
+/* { dg-options "-O2 -march=rv64im_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
 
 int main () {
 
@@ -15,6 +15,10 @@ int main () {
 #error "__riscv_i"
 #endif
 
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
 #if !defined(__riscv_f)
 #error "__riscv_f"
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c b/gcc/testsuite/gcc.target/riscv/predef-32.c
index 7417e0d996f455d4967db051fd51df584cafb78d..6d56f8fe6b8a3f24b15a7ffff1f09223f268b576 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-32.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32i_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */
+/* { dg-options "-O2 -march=rv32im_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */
 
 int main () {
 
@@ -15,6 +15,10 @@ int main () {
 #error "__riscv_i"
 #endif
 
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
 #if !defined(__riscv_f)
 #error "__riscv_f"
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c b/gcc/testsuite/gcc.target/riscv/predef-33.c
index 74d05bc9719dc8eed621892e5ffe17a8d19d0e64..f1da7e582af4a737c38d48b8488c9336ca8edf90 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-33.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-33.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */
+/* { dg-options "-O2 -march=rv64imv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */
 
 int main () {
 
@@ -15,6 +15,10 @@ int main () {
 #error "__riscv_i"
 #endif
 
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
 #if !defined(__riscv_f)
 #error "__riscv_f"
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/predef-36.c b/gcc/testsuite/gcc.target/riscv/predef-36.c
index b0205b085136bffb7a8fcf6d10c7dc4844c6a47c..7c87a42f3d36b3c4948965cfabe7749a7df04862 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-36.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-36.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32i_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */
+/* { dg-options "-O2 -march=rv32im_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */
 
 int
 main ()
@@ -16,6 +16,10 @@ main ()
 #error "__riscv_i"
 #endif
 
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
 #if !defined(__riscv_f)
 #error "__riscv_f"
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/predef-37.c b/gcc/testsuite/gcc.target/riscv/predef-37.c
index b5aa41102f472c7f33f7fd4afdd48b7e03e6a998..150150e32466c8d75dd5b481a18915ed02c49705 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/predef-37.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-37.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64iv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */
+/* { dg-options "-O2 -march=rv64imv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */
 
 int
 main ()
@@ -16,6 +16,10 @@ main ()
 #error "__riscv_i"
 #endif
 
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
 #if !defined(__riscv_f)
 #error "__riscv_f"
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c
index 2ba2a3633995c6b565838f849525b736ca0bb8ed..483e9b931f682bf1daef684c4d2807b2affb4643 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64iv -mabi=lp64d -O2" } */
+/* { dg-options "-march=rv64imv -mabi=lp64d -O2" } */
 
 typedef char __attribute__((__vector_size__ (1))) V;
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c
new file mode 100644 (file)
index 0000000..a722095
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64idv -mabi=lp64d -O3" } */
+
+int a[15][15];
+void init() {
+  for (int i_0 ; i_0 < 15 ; ++i_0)
+    for (int i_1 = 0; i_1 < 15; ++i_1)
+      a[i_0][i_1] = 1;
+}
+
+/* { dg-excess-errors "sorry, unimplemented: GCC's current 'V' implementation requires the 'M' extension" } */