arm64: dts: amlogic: s6: add power domain controller node

Add power domain controller node for Amlogic S6 SoC.

Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://patch.msgid.link/20250822-pm-s6-s7-s7d-v1-3-82e3f3aff327@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
index 5f602f1170c001f6cb5dea7bd941f89f09bb1d4e..0dca64a2ef9e9af113a7a7d4b6272cca0bcc615c 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
+#include <dt-bindings/power/amlogic,s6-pwrc.h>
 / {
        cpus {
                #address-cells = <2>;
@@ -41,6 +42,15 @@
                };
        };
 
+       sm: secure-monitor {
+               compatible = "amlogic,meson-gxbb-sm";
+
+               pwrc: power-controller {
+                       compatible = "amlogic,s6-pwrc";
+                       #power-domain-cells = <1>;
+               };
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,