+++ /dev/null
-From a2d17f6b47fa16a1e35b7b29b9504fed586c2ae4 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 2 Jan 2023 10:46:29 +0100
-Subject: arm64: dts: qcom: ipq6018: Add/remove some newlines
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 6db9ed9a128cbae1423d043f3debd8bfa77783fd ]
-
-Some lines were broken very aggresively, presumably to fit under 80 chars
-and some places could have used a newline, particularly between subsequent
-nodes. Address all that and remove redundant comments near PCIe ranges
-while at it so as not to exceed 100 chars needlessly.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
- 1 file changed, 12 insertions(+), 14 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index 2c9bd06c5c3c6..e566dccfdcf50 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -96,26 +96,31 @@
- opp-microvolt = <725000>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <787500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1320000000 {
- opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <862500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <925000>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <987500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1062500>;
-@@ -131,8 +136,7 @@
-
- pmuv8: pmu {
- compatible = "arm,cortex-a53-pmu";
-- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
-- IRQ_TYPE_LEVEL_HIGH)>;
-+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- psci: psci {
-@@ -429,24 +433,18 @@
- phys = <&pcie_phy0>;
- phy-names = "pciephy";
-
-- ranges = <0x81000000 0 0x20200000 0 0x20200000
-- 0 0x10000>, /* downstream I/O */
-- <0x82000000 0 0x20220000 0 0x20220000
-- 0 0xfde0000>; /* non-prefetchable memory */
-+ ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
-+ <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
-
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
-- interrupt-map = <0 0 0 1 &intc 0 75
-- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-- <0 0 0 2 &intc 0 78
-- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-- <0 0 0 3 &intc 0 79
-- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-- <0 0 0 4 &intc 0 83
-- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
- <&gcc GCC_PCIE0_AXI_M_CLK>,
---
-2.39.2
-
Link: https://lore.kernel.org/r/20230228164752.55682-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index e566dccfdcf50..e49b7cb405956 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -433,8 +433,8 @@
+@@ -433,10 +433,8 @@
phys = <&pcie_phy0>;
phy-names = "pciephy";
-- ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
-- <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
+- ranges = <0x81000000 0 0x20200000 0 0x20200000
+- 0 0x10000>, /* downstream I/O */
+- <0x82000000 0 0x20220000 0 0x20220000
+- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
+ <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
---
-2.39.2
-
+++ /dev/null
-From 0da8bd2056261cbf6a1d80b2e948955e75219e37 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 3 Nov 2022 22:21:25 +0100
-Subject: arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table
-
-From: Christian Marangi <ansuelsmth@gmail.com>
-
-[ Upstream commit 08f399a818b0eff552b1f23c3171950a58aea78f ]
-
-This is not a fix on its own but more a cleanup. Phy qmp pcie driver
-currently have a workaround to handle pcs_misc not declared and add
-0x400 offset to the pcs reg if pcs_misc is not declared.
-
-Correctly declare pcs_misc reg and reduce PCS size to the common value
-of 0x1f0 as done for every other qmp based pcie phy device.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Vinod Koul <vkoul@kernel.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index 15ba7d215dde9..2c9bd06c5c3c6 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -399,7 +399,8 @@
- pcie_phy0: phy@84200 {
- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
-- <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
-+ <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-+ <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
---
-2.39.2
-
+++ /dev/null
-From f0d32902d997adbd150dc8abf558e2f7e948d29f Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Fri, 9 Sep 2022 11:20:31 +0200
-Subject: arm64: dts: qcom: ipq6018: switch TCSR mutex to MMIO
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit f5e303aefc06b7508d7a490f9a2d80e4dc134c70 ]
-
-The TCSR mutex bindings allow device to be described only with address
-space (so it uses MMIO, not syscon regmap). This seems reasonable as
-TCSR mutex is actually a dedicated IO address space and it also fixes DT
-schema checks:
-
- qcom/ipq6018-cp01-c1.dtb: hwlock: 'reg' is a required property
- qcom/ipq6018-cp01-c1.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+'
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220909092035.223915-12-krzysztof.kozlowski@linaro.org
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 ++++---------
- 1 file changed, 4 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index 30ac0b2e8c896..15ba7d215dde9 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -129,12 +129,6 @@
- };
- };
-
-- tcsr_mutex: hwlock {
-- compatible = "qcom,tcsr-mutex";
-- syscon = <&tcsr_mutex_regs 0 0x80>;
-- #hwlock-cells = <1>;
-- };
--
- pmuv8: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
-@@ -253,9 +247,10 @@
- #reset-cells = <1>;
- };
-
-- tcsr_mutex_regs: syscon@1905000 {
-- compatible = "syscon";
-- reg = <0x0 0x01905000 0x0 0x8000>;
-+ tcsr_mutex: hwlock@1905000 {
-+ compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
-+ reg = <0x0 0x01905000 0x0 0x1000>;
-+ #hwlock-cells = <1>;
- };
-
- tcsr: syscon@1937000 {
---
-2.39.2
-
arm64-dts-qcom-sdm845-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-msm8998-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-ipq8074-fix-the-pci-i-o-port-range.patch
-arm64-dts-qcom-ipq6018-switch-tcsr-mutex-to-mmio.patch
-arm64-dts-qcom-ipq6018-improve-pcie-phy-pcs-reg-tabl.patch
-arm64-dts-qcom-ipq6018-add-remove-some-newlines.patch
arm64-dts-qcom-ipq6018-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-msm8996-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-sm8250-fix-the-pci-i-o-port-range.patch
+++ /dev/null
-From e785237272a2a5fb7e59877828cd837cf2165298 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 2 Jan 2023 10:46:29 +0100
-Subject: arm64: dts: qcom: ipq6018: Add/remove some newlines
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 6db9ed9a128cbae1423d043f3debd8bfa77783fd ]
-
-Some lines were broken very aggresively, presumably to fit under 80 chars
-and some places could have used a newline, particularly between subsequent
-nodes. Address all that and remove redundant comments near PCIe ranges
-while at it so as not to exceed 100 chars needlessly.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
- 1 file changed, 12 insertions(+), 14 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index 2972fe760c573..2b90c8b4d1a03 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -102,26 +102,31 @@
- opp-microvolt = <725000>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <787500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1320000000 {
- opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <862500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <925000>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <987500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1062500>;
-@@ -131,8 +136,7 @@
-
- pmuv8: pmu {
- compatible = "arm,cortex-a53-pmu";
-- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
-- IRQ_TYPE_LEVEL_HIGH)>;
-+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- psci: psci {
-@@ -742,24 +746,18 @@
- phys = <&pcie_phy0>;
- phy-names = "pciephy";
-
-- ranges = <0x81000000 0 0x20200000 0 0x20200000
-- 0 0x10000>, /* downstream I/O */
-- <0x82000000 0 0x20220000 0 0x20220000
-- 0 0xfde0000>; /* non-prefetchable memory */
-+ ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
-+ <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
-
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
-- interrupt-map = <0 0 0 1 &intc 0 75
-- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-- <0 0 0 2 &intc 0 78
-- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-- <0 0 0 3 &intc 0 79
-- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-- <0 0 0 4 &intc 0 83
-- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
- <&gcc GCC_PCIE0_AXI_M_CLK>,
---
-2.39.2
-
Link: https://lore.kernel.org/r/20230228164752.55682-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index 2b90c8b4d1a03..042d87c620db1 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -746,8 +746,8 @@
+@@ -436,10 +436,8 @@
phys = <&pcie_phy0>;
phy-names = "pciephy";
-- ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
-- <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
+- ranges = <0x81000000 0 0x20200000 0 0x20200000
+- 0 0x10000>, /* downstream I/O */
+- <0x82000000 0 0x20220000 0 0x20220000
+- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
+ <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
---
-2.39.2
-
+++ /dev/null
-From 163c2bc7e47fcd3a6374e17257536cf54ee7fafd Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 2 Jan 2023 10:46:27 +0100
-Subject: arm64: dts: qcom: ipq6018: Fix up indentation
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit c2596b717e9d96ae57c45481acfbafe9d3d54e56 ]
-
-The dwc3 subnode was indented using spaces for some reason and other
-properties were not exactly properly indented. Fix it.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-3-konrad.dybcio@linaro.org
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 44 +++++++++++++--------------
- 1 file changed, 22 insertions(+), 22 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index 12d1ba1923ffd..2aac6abe441fc 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -201,8 +201,8 @@
- compatible = "qcom,crypto-v5.1";
- reg = <0x0 0x0073a000 0x0 0x6000>;
- clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
-- <&gcc GCC_CRYPTO_AXI_CLK>,
-- <&gcc GCC_CRYPTO_CLK>;
-+ <&gcc GCC_CRYPTO_AXI_CLK>,
-+ <&gcc GCC_CRYPTO_CLK>;
- clock-names = "iface", "bus", "core";
- dmas = <&cryptobam 2>, <&cryptobam 3>;
- dma-names = "rx", "tx";
-@@ -272,7 +272,7 @@
- reg = <0x0 0x078b1000 0x0 0x200>;
- interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
-- <&gcc GCC_BLSP1_AHB_CLK>;
-+ <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
-@@ -285,7 +285,7 @@
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
-- <&gcc GCC_BLSP1_AHB_CLK>;
-+ <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- dmas = <&blsp_dma 12>, <&blsp_dma 13>;
- dma-names = "tx", "rx";
-@@ -300,7 +300,7 @@
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
- clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
-- <&gcc GCC_BLSP1_AHB_CLK>;
-+ <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- dmas = <&blsp_dma 14>, <&blsp_dma 15>;
- dma-names = "tx", "rx";
-@@ -358,8 +358,8 @@
- clock-names = "core", "aon";
-
- dmas = <&qpic_bam 0>,
-- <&qpic_bam 1>,
-- <&qpic_bam 2>;
-+ <&qpic_bam 1>,
-+ <&qpic_bam 2>;
- dma-names = "tx", "rx", "cmd";
- pinctrl-0 = <&qpic_pins>;
- pinctrl-names = "default";
-@@ -372,10 +372,10 @@
- #size-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <0x3>;
-- reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
-- <0x0 0x0b002000 0x0 0x1000>, /*GICC*/
-- <0x0 0x0b001000 0x0 0x1000>, /*GICH*/
-- <0x0 0x0b004000 0x0 0x1000>; /*GICV*/
-+ reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
-+ <0x0 0x0b002000 0x0 0x1000>, /*GICC*/
-+ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/
-+ <0x0 0x0b004000 0x0 0x1000>; /*GICV*/
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- ranges = <0 0 0 0xb00a000 0 0xffd>;
-
-@@ -671,17 +671,17 @@
- status = "disabled";
-
- dwc_1: usb@7000000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x07000000 0x0 0xcd00>;
-- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-- phys = <&qusb_phy_1>;
-- phy-names = "usb2-phy";
-- tx-fifo-resize;
-- snps,is-utmi-l1-suspend;
-- snps,hird-threshold = /bits/ 8 <0x0>;
-- snps,dis_u2_susphy_quirk;
-- snps,dis_u3_susphy_quirk;
-- dr_mode = "host";
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x07000000 0x0 0xcd00>;
-+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&qusb_phy_1>;
-+ phy-names = "usb2-phy";
-+ tx-fifo-resize;
-+ snps,is-utmi-l1-suspend;
-+ snps,hird-threshold = /bits/ 8 <0x0>;
-+ snps,dis_u2_susphy_quirk;
-+ snps,dis_u3_susphy_quirk;
-+ dr_mode = "host";
- };
- };
-
---
-2.39.2
-
+++ /dev/null
-From 9e5cb83a65d2052835632ed90083944ca5c4a488 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 3 Nov 2022 22:21:25 +0100
-Subject: arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table
-
-From: Christian Marangi <ansuelsmth@gmail.com>
-
-[ Upstream commit 08f399a818b0eff552b1f23c3171950a58aea78f ]
-
-This is not a fix on its own but more a cleanup. Phy qmp pcie driver
-currently have a workaround to handle pcs_misc not declared and add
-0x400 offset to the pcs reg if pcs_misc is not declared.
-
-Correctly declare pcs_misc reg and reduce PCS size to the common value
-of 0x1f0 as done for every other qmp based pcie phy device.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Vinod Koul <vkoul@kernel.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index a7c7ca980a71c..f3a4cf6e14c72 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -406,7 +406,8 @@
- pcie_phy0: phy@84200 {
- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
-- <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
-+ <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-+ <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
---
-2.39.2
-
+++ /dev/null
-From cfc319f806f16d22fe70f31d39e2f66c3c3faf78 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 2 Jan 2023 10:46:26 +0100
-Subject: arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 647380e41520c7dbd651ebf0d9fd7dfa4928f42d ]
-
-Some addresses were 7-hex-digits long, or less. Fix that.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 24 ++++++++++++------------
- 1 file changed, 12 insertions(+), 12 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index dd7f33cda867d..12d1ba1923ffd 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -146,7 +146,7 @@
- ranges;
-
- rpm_msg_ram: memory@60000 {
-- reg = <0x0 0x60000 0x0 0x6000>;
-+ reg = <0x0 0x00060000 0x0 0x6000>;
- no-map;
- };
-
-@@ -181,7 +181,7 @@
-
- prng: qrng@e1000 {
- compatible = "qcom,prng-ee";
-- reg = <0x0 0xe3000 0x0 0x1000>;
-+ reg = <0x0 0x000e3000 0x0 0x1000>;
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
- clock-names = "core";
- };
-@@ -388,7 +388,7 @@
-
- pcie_phy: phy@84000 {
- compatible = "qcom,ipq6018-qmp-pcie-phy";
-- reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
-+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
-@@ -404,10 +404,10 @@
- "common";
-
- pcie_phy0: phy@84200 {
-- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
-- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
-- <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-- <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
-+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
-+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
-+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-@@ -631,7 +631,7 @@
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
-- reg = <0x0 0x90000 0x0 0x64>;
-+ reg = <0x0 0x00090000 0x0 0x64>;
- clocks = <&gcc GCC_MDIO_AHB_CLK>;
- clock-names = "gcc_mdio_ahb_clk";
- status = "disabled";
-@@ -639,7 +639,7 @@
-
- qusb_phy_1: qusb@59000 {
- compatible = "qcom,ipq6018-qusb2-phy";
-- reg = <0x0 0x059000 0x0 0x180>;
-+ reg = <0x0 0x00059000 0x0 0x180>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
-@@ -672,7 +672,7 @@
-
- dwc_1: usb@7000000 {
- compatible = "snps,dwc3";
-- reg = <0x0 0x7000000 0x0 0xcd00>;
-+ reg = <0x0 0x07000000 0x0 0xcd00>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_1>;
- phy-names = "usb2-phy";
-@@ -687,7 +687,7 @@
-
- ssphy_0: ssphy@78000 {
- compatible = "qcom,ipq6018-qmp-usb3-phy";
-- reg = <0x0 0x78000 0x0 0x1c4>;
-+ reg = <0x0 0x00078000 0x0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-@@ -716,7 +716,7 @@
-
- qusb_phy_0: qusb@79000 {
- compatible = "qcom,ipq6018-qusb2-phy";
-- reg = <0x0 0x079000 0x0 0x180>;
-+ reg = <0x0 0x00079000 0x0 0x180>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
---
-2.39.2
-
+++ /dev/null
-From f65eaf4006a87dcb9711bbdf2622be38a94bf462 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 2 Jan 2023 10:46:28 +0100
-Subject: arm64: dts: qcom: ipq6018: Sort nodes properly
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d ]
-
-Order nodes by unit address if one exists and alphabetically otherwise.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++-------------
- 1 file changed, 281 insertions(+), 281 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index 2aac6abe441fc..2972fe760c573 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -87,6 +87,12 @@
- };
- };
-
-+ firmware {
-+ scm {
-+ compatible = "qcom,scm-ipq6018", "qcom,scm";
-+ };
-+ };
-+
- cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
- opp-shared;
-@@ -123,12 +129,6 @@
- };
- };
-
-- firmware {
-- scm {
-- compatible = "qcom,scm-ipq6018", "qcom,scm";
-- };
-- };
--
- pmuv8: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
-@@ -166,6 +166,28 @@
- };
- };
-
-+ rpm-glink {
-+ compatible = "qcom,glink-rpm";
-+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
-+ mboxes = <&apcs_glb 0>;
-+
-+ rpm_requests: glink-channel {
-+ compatible = "qcom,rpm-ipq6018";
-+ qcom,glink-channels = "rpm_requests";
-+
-+ regulators {
-+ compatible = "qcom,rpm-mp5496-regulators";
-+
-+ ipq6018_s2: s2 {
-+ regulator-min-microvolt = <725000>;
-+ regulator-max-microvolt = <1062500>;
-+ regulator-always-on;
-+ };
-+ };
-+ };
-+ };
-+
- smem {
- compatible = "qcom,smem";
- memory-region = <&smem_region>;
-@@ -179,6 +201,102 @@
- dma-ranges;
- compatible = "simple-bus";
-
-+ qusb_phy_1: qusb@59000 {
-+ compatible = "qcom,ipq6018-qusb2-phy";
-+ reg = <0x0 0x00059000 0x0 0x180>;
-+ #phy-cells = <0>;
-+
-+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
-+ <&xo>;
-+ clock-names = "cfg_ahb", "ref";
-+
-+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
-+ status = "disabled";
-+ };
-+
-+ ssphy_0: ssphy@78000 {
-+ compatible = "qcom,ipq6018-qmp-usb3-phy";
-+ reg = <0x0 0x00078000 0x0 0x1c4>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_USB0_AUX_CLK>,
-+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
-+ clock-names = "aux", "cfg_ahb", "ref";
-+
-+ resets = <&gcc GCC_USB0_PHY_BCR>,
-+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
-+ reset-names = "phy","common";
-+ status = "disabled";
-+
-+ usb0_ssphy: phy@78200 {
-+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
-+ <0x0 0x00078400 0x0 0x200>, /* Rx */
-+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */
-+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
-+ #phy-cells = <0>;
-+ #clock-cells = <0>;
-+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "gcc_usb0_pipe_clk_src";
-+ };
-+ };
-+
-+ qusb_phy_0: qusb@79000 {
-+ compatible = "qcom,ipq6018-qusb2-phy";
-+ reg = <0x0 0x00079000 0x0 0x180>;
-+ #phy-cells = <0>;
-+
-+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
-+ <&xo>;
-+ clock-names = "cfg_ahb", "ref";
-+
-+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
-+ status = "disabled";
-+ };
-+
-+ pcie_phy: phy@84000 {
-+ compatible = "qcom,ipq6018-qmp-pcie-phy";
-+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
-+ status = "disabled";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-+ <&gcc GCC_PCIE0_AHB_CLK>;
-+ clock-names = "aux", "cfg_ahb";
-+
-+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
-+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
-+ reset-names = "phy",
-+ "common";
-+
-+ pcie_phy0: phy@84200 {
-+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
-+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
-+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
-+ #phy-cells = <0>;
-+
-+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "gcc_pcie0_pipe_clk_src";
-+ #clock-cells = <0>;
-+ };
-+ };
-+
-+ mdio: mdio@90000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
-+ reg = <0x0 0x00090000 0x0 0x64>;
-+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
-+ clock-names = "gcc_mdio_ahb_clk";
-+ status = "disabled";
-+ };
-+
- prng: qrng@e1000 {
- compatible = "qcom,prng-ee";
- reg = <0x0 0x000e3000 0x0 0x1000>;
-@@ -257,6 +375,41 @@
- reg = <0x0 0x01937000 0x0 0x21000>;
- };
-
-+ usb2: usb@70f8800 {
-+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-+ reg = <0x0 0x070F8800 0x0 0x400>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ clocks = <&gcc GCC_USB1_MASTER_CLK>,
-+ <&gcc GCC_USB1_SLEEP_CLK>,
-+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-+ clock-names = "core",
-+ "sleep",
-+ "mock_utmi";
-+
-+ assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
-+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-+ assigned-clock-rates = <133330000>,
-+ <24000000>;
-+ resets = <&gcc GCC_USB1_BCR>;
-+ status = "disabled";
-+
-+ dwc_1: usb@7000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x07000000 0x0 0xcd00>;
-+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&qusb_phy_1>;
-+ phy-names = "usb2-phy";
-+ tx-fifo-resize;
-+ snps,is-utmi-l1-suspend;
-+ snps,hird-threshold = /bits/ 8 <0x0>;
-+ snps,dis_u2_susphy_quirk;
-+ snps,dis_u3_susphy_quirk;
-+ dr_mode = "host";
-+ };
-+ };
-+
- blsp_dma: dma-controller@7884000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x0 0x07884000 0x0 0x2b000>;
-@@ -366,6 +519,49 @@
- status = "disabled";
- };
-
-+ usb3: usb@8af8800 {
-+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-+ reg = <0x0 0x08af8800 0x0 0x400>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-+ <&gcc GCC_USB0_MASTER_CLK>,
-+ <&gcc GCC_USB0_SLEEP_CLK>,
-+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-+ clock-names = "cfg_noc",
-+ "core",
-+ "sleep",
-+ "mock_utmi";
-+
-+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-+ <&gcc GCC_USB0_MASTER_CLK>,
-+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-+ assigned-clock-rates = <133330000>,
-+ <133330000>,
-+ <20000000>;
-+
-+ resets = <&gcc GCC_USB0_BCR>;
-+ status = "disabled";
-+
-+ dwc_0: usb@8a00000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x08a00000 0x0 0xcd00>;
-+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ clocks = <&xo>;
-+ clock-names = "ref";
-+ tx-fifo-resize;
-+ snps,is-utmi-l1-suspend;
-+ snps,hird-threshold = /bits/ 8 <0x0>;
-+ snps,dis_u2_susphy_quirk;
-+ snps,dis_u3_susphy_quirk;
-+ dr_mode = "host";
-+ };
-+ };
-+
- intc: interrupt-controller@b000000 {
- compatible = "qcom,msm-qgic2";
- #address-cells = <2>;
-@@ -386,130 +582,29 @@
- };
- };
-
-- pcie_phy: phy@84000 {
-- compatible = "qcom,ipq6018-qmp-pcie-phy";
-- reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
-- status = "disabled";
-- #address-cells = <2>;
-- #size-cells = <2>;
-- ranges;
--
-- clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-- <&gcc GCC_PCIE0_AHB_CLK>;
-- clock-names = "aux", "cfg_ahb";
--
-- resets = <&gcc GCC_PCIE0_PHY_BCR>,
-- <&gcc GCC_PCIE0PHY_PHY_BCR>;
-- reset-names = "phy",
-- "common";
-+ watchdog@b017000 {
-+ compatible = "qcom,kpss-wdt";
-+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
-+ reg = <0x0 0x0b017000 0x0 0x40>;
-+ clocks = <&sleep_clk>;
-+ timeout-sec = <10>;
-+ };
-
-- pcie_phy0: phy@84200 {
-- reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
-- <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
-- <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-- <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
-- #phy-cells = <0>;
-+ apcs_glb: mailbox@b111000 {
-+ compatible = "qcom,ipq6018-apcs-apps-global";
-+ reg = <0x0 0x0b111000 0x0 0x1000>;
-+ #clock-cells = <1>;
-+ clocks = <&a53pll>, <&xo>;
-+ clock-names = "pll", "xo";
-+ #mbox-cells = <1>;
-+ };
-
-- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-- clock-names = "pipe0";
-- clock-output-names = "gcc_pcie0_pipe_clk_src";
-- #clock-cells = <0>;
-- };
-- };
--
-- pcie0: pci@20000000 {
-- compatible = "qcom,pcie-ipq6018";
-- reg = <0x0 0x20000000 0x0 0xf1d>,
-- <0x0 0x20000f20 0x0 0xa8>,
-- <0x0 0x20001000 0x0 0x1000>,
-- <0x0 0x80000 0x0 0x4000>,
-- <0x0 0x20100000 0x0 0x1000>;
-- reg-names = "dbi", "elbi", "atu", "parf", "config";
--
-- device_type = "pci";
-- linux,pci-domain = <0>;
-- bus-range = <0x00 0xff>;
-- num-lanes = <1>;
-- max-link-speed = <3>;
-- #address-cells = <3>;
-- #size-cells = <2>;
--
-- phys = <&pcie_phy0>;
-- phy-names = "pciephy";
--
-- ranges = <0x81000000 0 0x20200000 0 0x20200000
-- 0 0x10000>, /* downstream I/O */
-- <0x82000000 0 0x20220000 0 0x20220000
-- 0 0xfde0000>; /* non-prefetchable memory */
--
-- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "msi";
--
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0 0 0 0x7>;
-- interrupt-map = <0 0 0 1 &intc 0 75
-- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-- <0 0 0 2 &intc 0 78
-- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-- <0 0 0 3 &intc 0 79
-- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-- <0 0 0 4 &intc 0 83
-- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
--
-- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
-- <&gcc GCC_PCIE0_AXI_M_CLK>,
-- <&gcc GCC_PCIE0_AXI_S_CLK>,
-- <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
-- <&gcc PCIE0_RCHNG_CLK>;
-- clock-names = "iface",
-- "axi_m",
-- "axi_s",
-- "axi_bridge",
-- "rchng";
--
-- resets = <&gcc GCC_PCIE0_PIPE_ARES>,
-- <&gcc GCC_PCIE0_SLEEP_ARES>,
-- <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
-- <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
-- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
-- <&gcc GCC_PCIE0_AHB_ARES>,
-- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-- <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
-- reset-names = "pipe",
-- "sleep",
-- "sticky",
-- "axi_m",
-- "axi_s",
-- "ahb",
-- "axi_m_sticky",
-- "axi_s_sticky";
--
-- status = "disabled";
-- };
--
-- watchdog@b017000 {
-- compatible = "qcom,kpss-wdt";
-- interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
-- reg = <0x0 0x0b017000 0x0 0x40>;
-- clocks = <&sleep_clk>;
-- timeout-sec = <10>;
-- };
--
-- apcs_glb: mailbox@b111000 {
-- compatible = "qcom,ipq6018-apcs-apps-global";
-- reg = <0x0 0x0b111000 0x0 0x1000>;
-- #clock-cells = <1>;
-- clocks = <&a53pll>, <&xo>;
-- clock-names = "pll", "xo";
-- #mbox-cells = <1>;
-- };
--
-- a53pll: clock@b116000 {
-- compatible = "qcom,ipq6018-a53pll";
-- reg = <0x0 0x0b116000 0x0 0x40>;
-- #clock-cells = <0>;
-- clocks = <&xo>;
-- clock-names = "xo";
-+ a53pll: clock@b116000 {
-+ compatible = "qcom,ipq6018-a53pll";
-+ reg = <0x0 0x0b116000 0x0 0x40>;
-+ #clock-cells = <0>;
-+ clocks = <&xo>;
-+ clock-names = "xo";
- };
-
- timer {
-@@ -627,147 +722,74 @@
- };
- };
-
-- mdio: mdio@90000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
-- reg = <0x0 0x00090000 0x0 0x64>;
-- clocks = <&gcc GCC_MDIO_AHB_CLK>;
-- clock-names = "gcc_mdio_ahb_clk";
-- status = "disabled";
-- };
--
-- qusb_phy_1: qusb@59000 {
-- compatible = "qcom,ipq6018-qusb2-phy";
-- reg = <0x0 0x00059000 0x0 0x180>;
-- #phy-cells = <0>;
--
-- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
-- <&xo>;
-- clock-names = "cfg_ahb", "ref";
--
-- resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
-- status = "disabled";
-- };
--
-- usb2: usb@70f8800 {
-- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-- reg = <0x0 0x070F8800 0x0 0x400>;
-- #address-cells = <2>;
-- #size-cells = <2>;
-- ranges;
-- clocks = <&gcc GCC_USB1_MASTER_CLK>,
-- <&gcc GCC_USB1_SLEEP_CLK>,
-- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-- clock-names = "core",
-- "sleep",
-- "mock_utmi";
--
-- assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
-- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-- assigned-clock-rates = <133330000>,
-- <24000000>;
-- resets = <&gcc GCC_USB1_BCR>;
-- status = "disabled";
--
-- dwc_1: usb@7000000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x07000000 0x0 0xcd00>;
-- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-- phys = <&qusb_phy_1>;
-- phy-names = "usb2-phy";
-- tx-fifo-resize;
-- snps,is-utmi-l1-suspend;
-- snps,hird-threshold = /bits/ 8 <0x0>;
-- snps,dis_u2_susphy_quirk;
-- snps,dis_u3_susphy_quirk;
-- dr_mode = "host";
-- };
-- };
-+ pcie0: pci@20000000 {
-+ compatible = "qcom,pcie-ipq6018";
-+ reg = <0x0 0x20000000 0x0 0xf1d>,
-+ <0x0 0x20000f20 0x0 0xa8>,
-+ <0x0 0x20001000 0x0 0x1000>,
-+ <0x0 0x80000 0x0 0x4000>,
-+ <0x0 0x20100000 0x0 0x1000>;
-+ reg-names = "dbi", "elbi", "atu", "parf", "config";
-
-- ssphy_0: ssphy@78000 {
-- compatible = "qcom,ipq6018-qmp-usb3-phy";
-- reg = <0x0 0x00078000 0x0 0x1c4>;
-- #address-cells = <2>;
-+ device_type = "pci";
-+ linux,pci-domain = <0>;
-+ bus-range = <0x00 0xff>;
-+ num-lanes = <1>;
-+ max-link-speed = <3>;
-+ #address-cells = <3>;
- #size-cells = <2>;
-- ranges;
--
-- clocks = <&gcc GCC_USB0_AUX_CLK>,
-- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
-- clock-names = "aux", "cfg_ahb", "ref";
--
-- resets = <&gcc GCC_USB0_PHY_BCR>,
-- <&gcc GCC_USB3PHY_0_PHY_BCR>;
-- reset-names = "phy","common";
-- status = "disabled";
--
-- usb0_ssphy: phy@78200 {
-- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
-- <0x0 0x00078400 0x0 0x200>, /* Rx */
-- <0x0 0x00078800 0x0 0x1f8>, /* PCS */
-- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
-- #phy-cells = <0>;
-- #clock-cells = <0>;
-- clocks = <&gcc GCC_USB0_PIPE_CLK>;
-- clock-names = "pipe0";
-- clock-output-names = "gcc_usb0_pipe_clk_src";
-- };
-- };
-
-- qusb_phy_0: qusb@79000 {
-- compatible = "qcom,ipq6018-qusb2-phy";
-- reg = <0x0 0x00079000 0x0 0x180>;
-- #phy-cells = <0>;
-+ phys = <&pcie_phy0>;
-+ phy-names = "pciephy";
-
-- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
-- <&xo>;
-- clock-names = "cfg_ahb", "ref";
-+ ranges = <0x81000000 0 0x20200000 0 0x20200000
-+ 0 0x10000>, /* downstream I/O */
-+ <0x82000000 0 0x20220000 0 0x20220000
-+ 0 0xfde0000>; /* non-prefetchable memory */
-
-- resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
-- status = "disabled";
-- };
-+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "msi";
-
-- usb3: usb@8af8800 {
-- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-- reg = <0x0 0x8af8800 0x0 0x400>;
-- #address-cells = <2>;
-- #size-cells = <2>;
-- ranges;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &intc 0 75
-+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 78
-+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 79
-+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 83
-+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
-- clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-- <&gcc GCC_USB0_MASTER_CLK>,
-- <&gcc GCC_USB0_SLEEP_CLK>,
-- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-- clock-names = "cfg_noc",
-- "core",
-- "sleep",
-- "mock_utmi";
-+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
-+ <&gcc GCC_PCIE0_AXI_M_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
-+ <&gcc PCIE0_RCHNG_CLK>;
-+ clock-names = "iface",
-+ "axi_m",
-+ "axi_s",
-+ "axi_bridge",
-+ "rchng";
-
-- assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-- <&gcc GCC_USB0_MASTER_CLK>,
-- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-- assigned-clock-rates = <133330000>,
-- <133330000>,
-- <20000000>;
-+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
-+ <&gcc GCC_PCIE0_SLEEP_ARES>,
-+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
-+ <&gcc GCC_PCIE0_AHB_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
-+ reset-names = "pipe",
-+ "sleep",
-+ "sticky",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "axi_m_sticky",
-+ "axi_s_sticky";
-
-- resets = <&gcc GCC_USB0_BCR>;
- status = "disabled";
--
-- dwc_0: usb@8a00000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x8a00000 0x0 0xcd00>;
-- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-- phys = <&qusb_phy_0>, <&usb0_ssphy>;
-- phy-names = "usb2-phy", "usb3-phy";
-- clocks = <&xo>;
-- clock-names = "ref";
-- tx-fifo-resize;
-- snps,is-utmi-l1-suspend;
-- snps,hird-threshold = /bits/ 8 <0x0>;
-- snps,dis_u2_susphy_quirk;
-- snps,dis_u3_susphy_quirk;
-- dr_mode = "host";
-- };
- };
- };
-
-@@ -794,26 +816,4 @@
- #interrupt-cells = <2>;
- };
- };
--
-- rpm-glink {
-- compatible = "qcom,glink-rpm";
-- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-- qcom,rpm-msg-ram = <&rpm_msg_ram>;
-- mboxes = <&apcs_glb 0>;
--
-- rpm_requests: glink-channel {
-- compatible = "qcom,rpm-ipq6018";
-- qcom,glink-channels = "rpm_requests";
--
-- regulators {
-- compatible = "qcom,rpm-mp5496-regulators";
--
-- ipq6018_s2: s2 {
-- regulator-min-microvolt = <725000>;
-- regulator-max-microvolt = <1062500>;
-- regulator-always-on;
-- };
-- };
-- };
-- };
- };
---
-2.39.2
-
+++ /dev/null
-From a34145ee25f5ef3f4d563091544f097404bca95e Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 12 Dec 2022 12:10:29 +0100
-Subject: arm64: dts: qcom: ipq6018: Use lowercase hex
-
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-
-[ Upstream commit 0431dba3733bf52dacf7382e7b0c1b4c0b59e88d ]
-
-Use lowercase hex, as that's the preferred and overwhermingly present
-style.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221212111037.98160-2-konrad.dybcio@linaro.org
-Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-index f3a4cf6e14c72..dd7f33cda867d 100644
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -687,7 +687,7 @@
-
- ssphy_0: ssphy@78000 {
- compatible = "qcom,ipq6018-qmp-usb3-phy";
-- reg = <0x0 0x78000 0x0 0x1C4>;
-+ reg = <0x0 0x78000 0x0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-@@ -704,7 +704,7 @@
- usb0_ssphy: phy@78200 {
- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
- <0x0 0x00078400 0x0 0x200>, /* Rx */
-- <0x0 0x00078800 0x0 0x1F8>, /* PCS */
-+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */
- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
-@@ -729,7 +729,7 @@
-
- usb3: usb@8af8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-- reg = <0x0 0x8AF8800 0x0 0x400>;
-+ reg = <0x0 0x8af8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-@@ -755,7 +755,7 @@
-
- dwc_0: usb@8a00000 {
- compatible = "snps,dwc3";
-- reg = <0x0 0x8A00000 0x0 0xcd00>;
-+ reg = <0x0 0x8a00000 0x0 0xcd00>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
- phy-names = "usb2-phy", "usb3-phy";
---
-2.39.2
-
arm64-dts-qcom-msm8998-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-sc7280-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-ipq8074-fix-the-pci-i-o-port-range.patch
-arm64-dts-qcom-ipq6018-improve-pcie-phy-pcs-reg-tabl.patch
-arm64-dts-qcom-ipq6018-use-lowercase-hex.patch
-arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch
-arm64-dts-qcom-ipq6018-fix-up-indentation.patch
-arm64-dts-qcom-ipq6018-sort-nodes-properly.patch
-arm64-dts-qcom-ipq6018-add-remove-some-newlines.patch
arm64-dts-qcom-ipq6018-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-msm8996-fix-the-pci-i-o-port-range.patch
arm64-dts-qcom-sm8250-fix-the-pci-i-o-port-range.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
