testsuite: Fix asm-hard-reg-error-{4,5}.c for non-LRA targets

Hard register constraints are only supported for LRA and not old reload.
Targets hppa, m68k, pdp11, rx, sh, vax do not default to LRA which is
why these tests fail there.  Limit the tests to LRA targets, although,
this means that currently on these targets the tests are skipped by
default.  Since the tests are about general logic, the extra coverage we
loose by skipping these targets is negligible.

For hppa, register 0 cannot be used as a general register.  Therefore,
use temporary registers r20 and r21 instead.  Likewise, for AVR use r20
and r24 instead.

gcc/testsuite/ChangeLog:

	* gcc.dg/asm-hard-reg-error-4.c: Limit the test to LRA targets.
	Use registers r20 and r21 for hppa.  Likewise, for AVR use r20
	and r24 instead.
	* gcc.dg/asm-hard-reg-error-5.c: Ditto.

diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-4.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-4.c
index 465f24b1f716c81033ada7f16082f57b9d539398..d1856ad48187ff9fa94e13b9857a851fc8047137 100644 (file)
--- a/gcc/testsuite/gcc.dg/asm-hard-reg-error-4.c
+++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-4.c
@@ -1,21 +1,32 @@
-/* { dg-do compile } */
+/* { dg-do compile { target lra } } */
 
 /* Verify output operands.  */
 
+#if defined __hppa__
+# define R0 "20"
+# define R1 "21"
+#elif defined __AVR__
+# define R0 "20"
+# define R1 "24"
+#else
+# define R0 "0"
+# define R1 "1"
+#endif
+
 int
 test (void)
 {
   int x;
-  register int y __asm__ ("0");
+  register int y __asm__ (R0);
 
   /* Preserve status quo and don't error out.  */
   __asm__ ("" : "=r" (x), "=r" (x));
 
   /* Be more strict for hard register constraints and error out.  */
-  __asm__ ("" : "={0}" (x), "={1}" (x)); /* { dg-error "multiple outputs to lvalue 'x'" } */
+  __asm__ ("" : "={"R0"}" (x), "={"R1"}" (x)); /* { dg-error "multiple outputs to lvalue 'x'" } */
 
   /* Still error out in case of a mixture.  */
-  __asm__ ("" : "=r" (x), "={1}" (x)); /* { dg-error "multiple outputs to lvalue 'x'" } */
+  __asm__ ("" : "=r" (x), "={"R1"}" (x)); /* { dg-error "multiple outputs to lvalue 'x'" } */
 
   return x + y;
 }

diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-5.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-5.c
index 85398f04cc8824382e4a116699ec6828796036b1..7f538ea9b9e0f470f4093352be66c38841ad1c1e 100644 (file)
--- a/gcc/testsuite/gcc.dg/asm-hard-reg-error-5.c
+++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-5.c
@@ -1,13 +1,24 @@
-/* { dg-do compile } */
+/* { dg-do compile { target lra } } */
 
 /* Test clobbers.
    See asm-hard-reg-error-{2,3}.c for tests involving register pairs.  */
 
+#if defined __hppa__
+# define R0 "20"
+# define R1 "21"
+#elif defined __AVR__
+# define R0 "20"
+# define R1 "24"
+#else
+# define R0 "0"
+# define R1 "1"
+#endif
+
 int
 test (void)
 {
   int x, y;
-  __asm__ ("" : "={0}" (x), "={1}" (y) : : "1"); /* { dg-error "hard register constraint for output 1 conflicts with 'asm' clobber list" } */
-  __asm__ ("" : "={0}" (x) : "{0}" (y), "{1}" (y) : "1"); /* { dg-error "hard register constraint for input 1 conflicts with 'asm' clobber list" } */
+  __asm__ ("" : "={"R0"}" (x), "={"R1"}" (y) : : R1); /* { dg-error "hard register constraint for output 1 conflicts with 'asm' clobber list" } */
+  __asm__ ("" : "={"R0"}" (x) : "{"R0"}" (y), "{"R1"}" (y) : R1); /* { dg-error "hard register constraint for input 1 conflicts with 'asm' clobber list" } */
   return x + y;
 }