Special-case rlwnms which are really slwi or srwi. This gives about

1% translated code size improvement for run-of-the-mill integer code.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1416

diff --git a/VEX/priv/guest-ppc32/toIR.c b/VEX/priv/guest-ppc32/toIR.c
index 4853882a237f69594b7899e1ff57d2b98ec7aafc..004e843c019199e319364458dc360f21191c5bc4 100644 (file)
--- a/VEX/priv/guest-ppc32/toIR.c
+++ b/VEX/priv/guest-ppc32/toIR.c
@@ -2153,11 +2153,33 @@ static Bool dis_int_rot ( UInt theInstr )
 
    case 0x15: 
       // rlwinm (Rotate Left Word Immediate then AND with Mask, PPC32 p501)
-      DIP("rlwinm%s r%d,r%d,%d,%d,%d\n", flag_Rc ? "." : "",
-          Ra_addr, Rs_addr, sh_imm, MaskBegin, MaskEnd);
-      // Ra = ROTL(Rs, Imm) & mask
-      assign( Ra, binop(Iop_And32, ROTL32(mkexpr(Rs), mkU32(sh_imm)), 
-                                   mkU32(mask)) );
+      vassert(MaskBegin < 32);
+      vassert(MaskEnd   < 32);
+      vassert(sh_imm    < 32);
+
+      if (MaskBegin == 0 && sh_imm+MaskEnd == 31) {
+         /* Special-case the ,n,0,31-n form as that is just n-bit
+            shift left (PPC32 p501) */
+         DIP("slwi%s r%d,r%d,%d\n", flag_Rc ? "." : "",
+             Ra_addr, Rs_addr, sh_imm);
+         assign( Ra, binop(Iop_Shl32, mkexpr(Rs), mkU8(sh_imm)) );
+      }
+      else
+      if (MaskEnd == 31 && sh_imm+MaskBegin == 32) {
+         /* Special-case the ,32-n,n,31 form as that is just n-bit
+            unsigned shift right (PPC32 p501) */
+         DIP("srwi%s r%d,r%d,%d\n", flag_Rc ? "." : "",
+             Ra_addr, Rs_addr, sh_imm);
+         assign( Ra, binop(Iop_Shr32, mkexpr(Rs), mkU8(MaskBegin)) );
+      }
+      else {
+         /* General case. */
+         DIP("rlwinm%s r%d,r%d,%d,%d,%d\n", flag_Rc ? "." : "",
+             Ra_addr, Rs_addr, sh_imm, MaskBegin, MaskEnd);
+         // Ra = ROTL(Rs, Imm) & mask
+         assign( Ra, binop(Iop_And32, ROTL32(mkexpr(Rs), mkU32(sh_imm)), 
+                                      mkU32(mask)) );
+      }
       break;
 
    case 0x17: