g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps);
}
-#define HVF_SYSREG(crn, crm, op0, op1, op2) \
- ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
-
#define SYSREG_OP0_SHIFT 20
#define SYSREG_OP0_MASK 0x3
#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
struct hvf_sreg_match {
int reg;
- uint32_t key;
uint32_t cp_idx;
};
#undef DEF_SYSREG
-#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \
- { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) },
+#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID },
static struct hvf_sreg_match hvf_sreg_match[] = {
#include "sysreg.c.inc"
pstate_write(env, val);
for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
+ int hvf_id = hvf_sreg_match[i].reg;
+ uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
+
if (hvf_sreg_match[i].cp_idx == -1) {
continue;
}
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
- switch (hvf_sreg_match[i].reg) {
+ switch (hvf_id) {
case HV_SYS_REG_DBGBVR0_EL1:
case HV_SYS_REG_DBGBCR0_EL1:
case HV_SYS_REG_DBGWVR0_EL1:
* vCPU but simply keep the values from the previous
* environment.
*/
- const ARMCPRegInfo *ri;
- ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key);
+ uint32_t key = kvm_to_cpreg_id(kvm_id);
+ const ARMCPRegInfo *ri =
+ get_arm_cp_reginfo(arm_cpu->cp_regs, key);
+
val = read_raw_cp_reg(env, ri);
arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
}
}
- ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val);
+ ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val);
assert_hvf_ok(ret);
arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
assert(write_cpustate_to_list(arm_cpu, false));
for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
+ int hvf_id = hvf_sreg_match[i].reg;
+
if (hvf_sreg_match[i].cp_idx == -1) {
continue;
}
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
- switch (hvf_sreg_match[i].reg) {
+ switch (hvf_id) {
case HV_SYS_REG_DBGBVR0_EL1:
case HV_SYS_REG_DBGBCR0_EL1:
case HV_SYS_REG_DBGWVR0_EL1:
}
val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
- ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val);
+ ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val);
assert_hvf_ok(ret);
}
/* Populate cp list for all known sysregs */
for (i = 0; i < sregs_match_len; i++) {
- const ARMCPRegInfo *ri;
- uint32_t key = hvf_sreg_match[i].key;
+ int hvf_id = hvf_sreg_match[i].reg;
+ uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
+ uint32_t key = kvm_to_cpreg_id(kvm_id);
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
- ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
if (ri) {
assert(!(ri->type & ARM_CP_NO_RAW));
hvf_sreg_match[i].cp_idx = sregs_cnt;
- arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
+ arm_cpu->cpreg_indexes[sregs_cnt++] = kvm_id;
} else {
hvf_sreg_match[i].cp_idx = -1;
}