Add -mapx-features= enumeration to separate subfeatures of APX_F.
-mapxf is treated same as previous ISA flag, while it sets
-mapx-features=apx_all that enables all subfeatures.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro.
(XCR_APX_F_ENABLED_MASK): Likewise.
(get_available_features): Detect APX_F under
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_APX_F_SET): New.
(OPTION_MASK_ISA2_APX_F_UNSET): Likewise.
(ix86_handle_option): Handle -mapxf.
* common/config/i386/i386-cpuinfo.h (FEATURE_APX_F): New.
* common/config/i386/i386-isas.h: Add entry for APX_F.
* config/i386/cpuid.h (bit_APX_F): New.
* config/i386/i386.h (bit_APX_F): (TARGET_APX_EGPR,
TARGET_APX_PUSH2POP2, TARGET_APX_NDD): New define.
* config/i386/i386-opts.h (enum apx_features): New enum.
* config/i386/i386-isa.def (APX_F): New DEF_PTA.
* config/i386/i386-options.cc (ix86_function_specific_save):
Save ix86_apx_features.
(ix86_function_specific_restore): Restore it.
(ix86_valid_target_attribute_inner_p): Add mapxf.
(ix86_option_override_internal): Set ix86_apx_features for PTA
and TARGET_APX_F. Also reports error when APX_F is set but not
having TARGET_64BIT.
* config/i386/i386.opt: (-mapxf): New ISA flag option.
(-mapx=): New enumeration option.
(apx_features): New enum type.
(apx_none): New enum value.
(apx_egpr): Likewise.
(apx_push2pop2): Likewise.
(apx_ndd): Likewise.
(apx_all): Likewise.
* doc/invoke.texi: Document mapxf.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-1.c: New test.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
#define XSTATE_HI_ZMM 0x80
#define XSTATE_TILECFG 0x20000
#define XSTATE_TILEDATA 0x40000
+#define XSTATE_APX_F 0x80000
#define XCR_AVX_ENABLED_MASK \
(XSTATE_SSE | XSTATE_YMM)
(XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
#define XCR_AMX_ENABLED_MASK \
(XSTATE_TILECFG | XSTATE_TILEDATA)
+#define XCR_APX_F_ENABLED_MASK XSTATE_APX_F
- /* Check if AVX and AVX512 are usable. */
+ /* Check if AVX, AVX512 and APX are usable. */
int avx_usable = 0;
int avx512_usable = 0;
int amx_usable = 0;
+ int apx_usable = 0;
/* Check if KL is usable. */
int has_kl = 0;
if ((ecx & bit_OSXSAVE))
}
amx_usable = ((xcrlow & XCR_AMX_ENABLED_MASK)
== XCR_AMX_ENABLED_MASK);
+ apx_usable = ((xcrlow & XCR_APX_F_ENABLED_MASK)
+ == XCR_APX_F_ENABLED_MASK);
}
#define set_feature(f) \
if (edx & bit_AMX_COMPLEX)
set_feature (FEATURE_AMX_COMPLEX);
}
+ if (apx_usable)
+ {
+ if (edx & bit_APX_F)
+ set_feature (FEATURE_APX_F);
+ }
}
}
#define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
#define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
#define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
+#define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
#define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
#define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
#define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
+#define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
}
return true;
+ case OPT_mapxf:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET;
+ opts->x_ix86_apx_features = apx_all;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET;
+ opts->x_ix86_apx_features = apx_none;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
FEATURE_SM3,
FEATURE_SHA512,
FEATURE_SM4,
+ FEATURE_APX_F,
CPU_FEATURE_MAX
};
ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3")
ISA_NAMES_TABLE_ENTRY("sha512", FEATURE_SHA512, P_NONE, "-msha512")
ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
+ ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
ISA_NAMES_TABLE_END
#define bit_AVXNECONVERT (1 << 5)
#define bit_AVXVNNIINT16 (1 << 10)
#define bit_PREFETCHI (1 << 14)
+#define bit_APX_F (1 << 21)
/* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
#define bit_XSAVEOPT (1 << 0)
DEF_PTA(SM3)
DEF_PTA(SHA512)
DEF_PTA(SM4)
+DEF_PTA(APX_F)
ptr->branch_cost = ix86_branch_cost;
ptr->tune_defaulted = ix86_tune_defaulted;
ptr->arch_specified = ix86_arch_specified;
+ ptr->x_ix86_apx_features = opts->x_ix86_apx_features;
ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit;
ptr->x_ix86_isa_flags2_explicit = opts->x_ix86_isa_flags2_explicit;
ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit;
ix86_prefetch_sse = ptr->prefetch_sse;
ix86_tune_defaulted = ptr->tune_defaulted;
ix86_arch_specified = ptr->arch_specified;
+ opts->x_ix86_apx_features = ptr->x_ix86_apx_features;
opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit;
opts->x_ix86_isa_flags2_explicit = ptr->x_ix86_isa_flags2_explicit;
opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit;
IX86_ATTR_ISA ("sm3", OPT_msm3),
IX86_ATTR_ISA ("sha512", OPT_msha512),
IX86_ATTR_ISA ("sm4", OPT_msm4),
+ IX86_ATTR_ISA ("apxf", OPT_mapxf),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
opts->x_ix86_stringop_alg = no_stringop;
}
+ if (TARGET_APX_F && !TARGET_64BIT)
+ error ("%<-mapxf%> is not supported for 32-bit code");
+
if (TARGET_UINTR && !TARGET_64BIT)
error ("%<-muintr%> not supported for 32-bit code");
SET_TARGET_POPCNT (opts);
}
+ /* Enable apx if apxf or apx_features are not
+ explicitly set for -march. */
+ if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
+ && ((processor_alias_table[i].flags & PTA_APX_F) != 0)
+ && !TARGET_EXPLICIT_APX_F_P (opts)
+ && !OPTION_SET_P (ix86_apx_features))
+ opts->x_ix86_apx_features = apx_all;
+
if ((processor_alias_table[i].flags
& (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
ix86_prefetch_sse = true;
/* Arrange to set up i386_stack_locals for all functions. */
init_machine_status = ix86_init_machine_status;
+ /* Override APX flag here if ISA bit is set. */
+ if (TARGET_APX_F && !OPTION_SET_P (ix86_apx_features))
+ opts->x_ix86_apx_features = apx_all;
+
/* Validate -mregparm= value. */
if (opts_set->x_ix86_regparm)
{
lam_u57
};
+enum apx_features {
+ apx_none = 0,
+ apx_egpr = 1 << 0,
+ apx_push2pop2 = 1 << 1,
+ apx_ndd = 1 << 2,
+ apx_all = apx_egpr | apx_push2pop2 | apx_ndd,
+};
+
#endif
#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
+#define TARGET_APX_EGPR (ix86_apx_features & apx_egpr)
+#define TARGET_APX_PUSH2POP2 (ix86_apx_features & apx_push2pop2)
+#define TARGET_APX_NDD (ix86_apx_features & apx_ndd)
+
#include "config/vxworks-dummy.h"
#include "config/i386/i386-opts.h"
mscatter
Target Alias(mtune-ctrl=, use_scatter, ^use_scatter)
Enable vectorization for scatter instruction.
+
+mapxf
+Target Mask(ISA2_APX_F) Var(ix86_isa_flags2) Save
+Support APX code generation.
+
+mapx-features=
+Target Undocumented Joined Enum(apx_features) EnumSet Var(ix86_apx_features) Init(apx_none) Save
+
+Enum
+Name(apx_features) Type(int)
+
+EnumValue
+Enum(apx_features) String(none) Value(apx_none) Set(1)
+
+EnumValue
+Enum(apx_features) String(egpr) Value(apx_egpr) Set(2)
+
+EnumValue
+Enum(apx_features) String(push2pop2) Value(apx_push2pop2) Set(3)
+
+EnumValue
+Enum(apx_features) String(ndd) Value(apx_ndd) Set(4)
+
+EnumValue
+Enum(apx_features) String(all) Value(apx_all) Set(1)
-mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk
-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
--mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4
+-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@need 200
@opindex msm4
@itemx -msm4
+@need 200
+@opindex mapxf
+@itemx -mapxf
These switches enable the use of instructions in the MMX, SSE,
AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
-AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4 or CLDEMOTE extended instruction
-sets. Each has a corresponding @option{-mno-} option to disable use of these
-instructions.
+AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F or CLDEMOTE extended
+instruction sets. Each has a corresponding @option{-mno-} option to disable
+use of these instructions.
These extensions are also available as built-in functions: see
@ref{x86 Built-in Functions}, for details of the functions enabled and
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -mapxf" } */
+/* { dg-error "'-mapxf' is not supported for 32-bit code" "" { target ia32 } 0 } */
+
+void
+apx_hanlder ()
+{
+}