wifi: mt76: mt792x: describe USB WFSYS reset with a descriptor

Prepare mt792xu_wfsys_reset() for chips that share the same USB WFSYS
reset flow but use different register definitions.

This is a pure refactor of the current mt7921u path and keeps the reset
sequence unchanged.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Link: https://patch.msgid.link/20260311002825.15502-1-sean.wang@kernel.org
Signed-off-by: Felix Fietkau <nbd@nbd.name>

diff --git a/drivers/net/wireless/mediatek/mt76/mt792x_usb.c b/drivers/net/wireless/mediatek/mt76/mt792x_usb.c
index 552808458138a67ceff61536bfcc2a2b25a889b6..a92e872226cfe977b214a46150738a5f515d1e95 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/mt792x_usb.c
+++ b/drivers/net/wireless/mediatek/mt76/mt792x_usb.c
@@ -206,6 +206,24 @@ static void mt792xu_epctl_rst_opt(struct mt792x_dev *dev, bool reset)
        mt792xu_uhw_wr(&dev->mt76, MT_SSUSB_EPCTL_CSR_EP_RST_OPT, val);
 }
 
+struct mt792xu_wfsys_desc {
+       u32 rst_reg;
+       u32 done_reg;
+       u32 done_mask;
+       u32 done_val;
+       u32 delay_ms;
+       bool need_status_sel;
+};
+
+static const struct mt792xu_wfsys_desc mt7921_wfsys_desc = {
+       .rst_reg = MT_CBTOP_RGU_WF_SUBSYS_RST,
+       .done_reg = MT_UDMA_CONN_INFRA_STATUS,
+       .done_mask = MT_UDMA_CONN_WFSYS_INIT_DONE,
+       .done_val = MT_UDMA_CONN_WFSYS_INIT_DONE,
+       .delay_ms = 0,
+       .need_status_sel = true,
+};
+
 int mt792xu_dma_init(struct mt792x_dev *dev, bool resume)
 {
        int err;
@@ -236,25 +254,31 @@ EXPORT_SYMBOL_GPL(mt792xu_dma_init);
 
 int mt792xu_wfsys_reset(struct mt792x_dev *dev)
 {
+       const struct mt792xu_wfsys_desc *desc = &mt7921_wfsys_desc;
        u32 val;
        int i;
 
        mt792xu_epctl_rst_opt(dev, false);
 
-       val = mt792xu_uhw_rr(&dev->mt76, MT_CBTOP_RGU_WF_SUBSYS_RST);
+       val = mt792xu_uhw_rr(&dev->mt76, desc->rst_reg);
        val |= MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH;
-       mt792xu_uhw_wr(&dev->mt76, MT_CBTOP_RGU_WF_SUBSYS_RST, val);
+       mt792xu_uhw_wr(&dev->mt76, desc->rst_reg, val);
 
-       usleep_range(10, 20);
+       if (desc->delay_ms)
+               msleep(desc->delay_ms);
+       else
+               usleep_range(10, 20);
 
-       val = mt792xu_uhw_rr(&dev->mt76, MT_CBTOP_RGU_WF_SUBSYS_RST);
+       val = mt792xu_uhw_rr(&dev->mt76, desc->rst_reg);
        val &= ~MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH;
-       mt792xu_uhw_wr(&dev->mt76, MT_CBTOP_RGU_WF_SUBSYS_RST, val);
+       mt792xu_uhw_wr(&dev->mt76, desc->rst_reg, val);
+
+       if (desc->need_status_sel)
+               mt792xu_uhw_wr(&dev->mt76, MT_UDMA_CONN_INFRA_STATUS_SEL, 0);
 
-       mt792xu_uhw_wr(&dev->mt76, MT_UDMA_CONN_INFRA_STATUS_SEL, 0);
        for (i = 0; i < MT792x_WFSYS_INIT_RETRY_COUNT; i++) {
-               val = mt792xu_uhw_rr(&dev->mt76, MT_UDMA_CONN_INFRA_STATUS);
-               if (val & MT_UDMA_CONN_WFSYS_INIT_DONE)
+               val = mt792xu_uhw_rr(&dev->mt76, desc->done_reg);
+               if ((val & desc->done_mask) == desc->done_val)
                        break;
 
                msleep(100);