arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc

The PCIe Gen4x2 PHY found in the SM8450 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided
clocks to the Global Clock Controller (GCC) node clocks inputs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-1-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 3494d507636805b88ff92e5d247af11a6d909640..ee0f092c02a693b1d7a5a76f88d54c937f5ca6bf 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -754,8 +754,8 @@
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&sleep_clk>,
                                 <&pcie0_phy>,
-                                <&pcie1_phy>,
-                                <0>,
+                                <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+                                <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
                                 <&ufs_mem_phy 0>,
                                 <&ufs_mem_phy 1>,
                                 <&ufs_mem_phy 2>,
@@ -2000,8 +2000,8 @@
                                      "rchng",
                                      "pipe";
 
-                       clock-output-names = "pcie_1_pipe_clk";
-                       #clock-cells = <0>;
+                       clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk";
+                       #clock-cells = <1>;
 
                        #phy-cells = <0>;