# SPDX-License-Identifier: GPL-2.0+
VERSION = 2020
-PATCHLEVEL = 01
+PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc0 = &mshc_0;
- mmc1 = &sdhci2;
+ mmc2 = &sdhci2;
};
serial@13810000 {
&sdhci2 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
+ cd-inverted;
cd-gpios = <&gpk2 2 0>;
status = "okay";
};
#include "exynos54xx.dtsi"
/ {
- model = "Odroid XU3 based on EXYNOS5422";
+ model = "Odroid XU3/XU4/HC1/HC2 based on Exynos5422";
compatible = "samsung,odroidxu3", "samsung,exynos5";
aliases {
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
#define EXYNOS4_PRO_ID 0x10000000
+#define EXYNOS4_OP_MODE 0x10000008
#define EXYNOS4_SYSREG_BASE 0x10010000
#define EXYNOS4_POWER_BASE 0x10020000
#define EXYNOS4_SWRESET 0x10020400
clock_enable(CCGR_WDOG3, 1);
}
-void init_usb_clk(void)
-{
- if (!is_usb_boot()) {
- clock_enable(CCGR_USB_CTRL1, 0);
- clock_enable(CCGR_USB_CTRL2, 0);
- clock_enable(CCGR_USB_PHY1, 0);
- clock_enable(CCGR_USB_PHY2, 0);
- /* 500MHz */
- clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
- /* 100MHz */
- clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
- /* 100MHz */
- clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
- clock_enable(CCGR_USB_CTRL1, 1);
- clock_enable(CCGR_USB_CTRL2, 1);
- clock_enable(CCGR_USB_PHY1, 1);
- clock_enable(CCGR_USB_PHY2, 1);
- }
-}
void init_nand_clk(void)
{
;
}
-int frac_pll_init(u32 pll, enum frac_pll_out_val val)
+static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
{
void __iomem *pll_cfg0, __iomem *pll_cfg1;
u32 val_cfg0, val_cfg1;
return 0;
}
-int sscg_pll_init(u32 pll)
-{
- void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
- u32 val_cfg0, val_cfg1, val_cfg2, val;
- u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
- int ret;
-
- switch (pll) {
- case ANATOP_SYSTEM_PLL1:
- pll_cfg0 = &ana_pll->sys_pll1_cfg0;
- pll_cfg1 = &ana_pll->sys_pll1_cfg1;
- pll_cfg2 = &ana_pll->sys_pll1_cfg2;
- /* 800MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- case ANATOP_SYSTEM_PLL2:
- pll_cfg0 = &ana_pll->sys_pll2_cfg0;
- pll_cfg1 = &ana_pll->sys_pll2_cfg1;
- pll_cfg2 = &ana_pll->sys_pll2_cfg2;
- /* 1000MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- case ANATOP_SYSTEM_PLL3:
- pll_cfg0 = &ana_pll->sys_pll3_cfg0;
- pll_cfg1 = &ana_pll->sys_pll3_cfg1;
- pll_cfg2 = &ana_pll->sys_pll3_cfg2;
- /* 800MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- default:
- return -EINVAL;
- }
-
- /*bypass*/
- setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
- /* set value */
- writel(val_cfg2, pll_cfg2);
- writel(val_cfg1, pll_cfg1);
- /*unbypass1 and wait 70us */
- writel(val_cfg0 | bypass2_mask, pll_cfg1);
-
- __udelay(70);
-
- /* unbypass2 and wait lock */
- writel(val_cfg0, pll_cfg1);
- ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
- if (ret)
- printf("%s timeout\n", __func__);
-
- return ret;
-}
int clock_init(void)
{
* Dump some clockes.
*/
#ifndef CONFIG_SPL_BUILD
-int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
u32 freq;
#include <asm/arch/sromc.h>
#include <lcd.h>
#include <i2c.h>
+#include <mmc.h>
+#include <stdio_dev.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <samsung/misc.h>
return 0;
}
+/**
+ * get_boot_mmc_dev() - read boot MMC device id from XOM[7:5] pins.
+ */
+static int get_boot_mmc_dev(void)
+{
+ u32 mode = readl(EXYNOS4_OP_MODE) & 0x1C;
+
+ if (mode == 0x04)
+ return 2; /* MMC2: SD */
+
+ /* MMC0: eMMC or unknown */
+ return 0;
+}
+
#if defined CONFIG_EXYNOS_TMU
/* Boot Time Thermal Analysis for SoC temperature threshold breach */
static void boot_temp_check(void)
{
struct udevice *dev;
int ret;
+ int mmcbootdev = get_boot_mmc_dev();
+ char mmcbootdev_str[16];
stdio_print_current_devices();
ret = uclass_first_device_err(UCLASS_CROS_EC, &dev);
panic("Cannot init cros-ec device");
return -1;
}
+
+ printf("Boot device: MMC(%u)\n", mmcbootdev);
+ sprintf(mmcbootdev_str, "%u", mmcbootdev);
+ env_set("mmcbootdev", mmcbootdev_str);
+
return 0;
}
#endif
#endif
return 0;
}
+
+int mmc_get_env_dev(void)
+{
+ return get_boot_mmc_dev();
+}
unsigned int adcval_prev = 0;
int ret, retries = 20;
- ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN,
+ ret = adc_channel_single_shot("adc@12D10000", CONFIG_ODROID_REV_AIN,
&adcval_prev);
if (ret)
return ret;
while (retries--) {
mdelay(5);
- ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN,
- adcval);
+ ret = adc_channel_single_shot("adc@12D10000",
+ CONFIG_ODROID_REV_AIN, adcval);
if (ret)
return ret;
if (gd->board_type != EXYNOS5_BOARD_ODROID_XU3_REV02)
goto exit;
- ret = pmic_get("s2mps11", &dev);
+ ret = pmic_get("s2mps11_pmic@66", &dev);
if (ret)
goto exit;
int ret;
#ifdef CONFIG_PMIC_S2MPS11
- ret = pmic_get("s2mps11_pmic", &dev);
+ ret = pmic_get("s2mps11_pmic@66", &dev);
#else
- ret = pmic_get("max77686", &dev);
+ ret = pmic_get("max77686_pmic@09", &dev);
if (!ret) {
/* TODO(sjg@chromium.org): Move into the clock/pmic API */
ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
if (ret)
return ret;
} else {
- ret = pmic_get("s5m8767-pmic", &dev);
+ ret = pmic_get("s5m8767_pmic@66", &dev);
/* TODO(sjg@chromium.org): Use driver model to access clock */
#ifdef CONFIG_PMIC_S5M8767
if (!ret)
for (reg = 0; reg < pmic_reg_count(dev); reg++) {
ret = pmic_reg_read(dev, reg);
- if (ret < 0) {
+ if (ret < 0 && ret != -ENODATA) {
printf("Can't read register: %d\n", reg);
return failure(ret);
}
if (!(reg % 16))
printf("\n0x%02x: ", reg);
- printf(fmt, ret);
+ if (ret == -ENODATA) {
+ int i;
+
+ for (i = 0; i < priv->trans_len; i++)
+ puts("--");
+ puts(" ");
+ } else {
+ printf(fmt, ret);
+ }
}
printf("\n");
struct udevice *dev;
int rc;
+ blk_unbind_all(IF_TYPE_SATA);
+
rc = uclass_find_device(UCLASS_AHCI, devnum, &dev);
if (!rc && !dev)
rc = uclass_find_first_device(UCLASS_AHCI, &dev);
static unsigned int bus;
static unsigned int cs;
static unsigned int mode;
+static unsigned int freq;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
str = strdup(name);
if (!str)
return -ENOMEM;
- ret = spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv",
+ ret = spi_get_bus_and_cs(bus, cs, freq, mode, "spi_generic_drv",
str, &dev, &slave);
if (ret)
return ret;
#else
- slave = spi_setup_slave(bus, cs, 1000000, mode);
+ slave = spi_setup_slave(bus, cs, freq, mode);
if (!slave) {
printf("Invalid device %d:%d\n", bus, cs);
return -EINVAL;
* We use the last specified parameters, unless new ones are
* entered.
*/
+ if (freq == 0)
+ freq = 1000000;
if ((flag & CMD_FLAG_REPEAT) == 0)
{
bus = CONFIG_DEFAULT_SPI_BUS;
}
if (*cp == '.')
- mode = simple_strtoul(cp+1, NULL, 10);
+ mode = simple_strtoul(cp+1, &cp, 10);
+ if (*cp == '@')
+ freq = simple_strtoul(cp+1, &cp, 10);
}
if (argc >= 3)
bitlen = simple_strtoul(argv[2], NULL, 10);
U_BOOT_CMD(
sspi, 5, 1, do_spi,
"SPI utility command",
- "[<bus>:]<cs>[.<mode>] <bit_len> <dout> - Send and receive bits\n"
+ "[<bus>:]<cs>[.<mode>][@<freq>] <bit_len> <dout> - Send and receive bits\n"
"<bus> - Identifies the SPI bus\n"
"<cs> - Identifies the chip select\n"
"<mode> - Identifies the SPI mode to use\n"
+ "<freq> - Identifies the SPI bus frequency in Hz\n"
"<bit_len> - Number of bits to send (base 10)\n"
"<dout> - Hexadecimal string that gets sent"
);
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_TYPES=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_BOARD_TYPES=y
CONFIG_SYS_PROMPT="Odroid # "
# CONFIG_CMD_XIMG is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910"
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
return 0;
}
-# endif /* OF_PLATDATA */
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
{
return clk_get_by_index(dev, index, clk);
}
+# endif /* OF_PLATDATA */
int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
{
int ret;
ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
- if (ret)
- printf("%s: UCLASS parent: 0x%p\n", __func__, parent);
+ if (ret) {
+ printf("%s: name: %s parent: %s [0x%p]\n",
+ __func__, name, parent->name, parent);
+ }
debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, parent->name,
parent);
/* CCM clocks */
base = dev_read_addr_ptr(dev);
- if (base == (void *)FDT_ADDR_T_NONE)
+ if (!base)
return -EINVAL;
clk_dm(IMX6QDL_CLK_USDHC1_SEL,
imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
base = dev_read_addr_ptr(dev);
- if (base == (void *)FDT_ADDR_T_NONE)
+ if (!base)
return -EINVAL;
clk_dm(IMX8MM_CLK_A53_SRC,
imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
base = dev_read_addr_ptr(dev);
- if (base == (void *)FDT_ADDR_T_NONE)
+ if (!base)
return -EINVAL;
clk_dm(IMX8MN_CLK_A53_SRC,
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
- unsigned long min_rate = parent_rate * 54 / 2;
- unsigned long max_rate = parent_rate * 108 / 2;
+ unsigned long min_rate;
+ unsigned long max_rate;
u32 val, div;
+ if (parent_rate == 0)
+ return -EINVAL;
+
+ min_rate = parent_rate * 54 / 2;
+ max_rate = parent_rate * 108 / 2;
+
if (rate < min_rate || rate > max_rate)
return -EINVAL;
u32 div = readl(pll->base) & pll->div_mask;
u64 temp64 = (u64)parent_rate;
+ if (mfd == 0)
+ return -EIO;
+
temp64 *= mfn;
do_div(temp64, mfd);
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
- unsigned long min_rate = parent_rate * 27;
- unsigned long max_rate = parent_rate * 54;
+ unsigned long min_rate;
+ unsigned long max_rate;
u32 val, div;
u32 mfn, mfd = 1000000;
u32 max_mfd = 0x3FFFFFFF;
u64 temp64;
+ if (parent_rate == 0)
+ return -EINVAL;
+
+ min_rate = parent_rate * 27;
+ max_rate = parent_rate * 54;
+
if (rate < min_rate || rate > max_rate)
return -EINVAL;
* the accurate frequency.
*/
static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
- const struct driver *drv)
+ const struct driver *drv)
{
struct clk parent = { .id = id, };
if (ret)
return ret;
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
host->mmc = &plat->mmc;
host->mmc->dev = dev;
+
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000);
if (ret)
return ret;
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
SPINAND_SELECT_TARGET(w25m02gv_select_target)),
+ SPINAND_INFO("W25N01GV", 0xAA,
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
};
/**
u16 page_size;
u16 addr_width;
- u16 flags;
+ u32 flags;
#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
#define SST_WRITE BIT(2) /* use SST byte programming */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
+#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
};
extern const struct flash_info spi_nor_ids[];
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
nor->read_reg = spi_nor_read_reg;
nor->write_reg = spi_nor_write_reg;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
functions. It uses an I2C interface and is designed for use with
tablets and smartphones.
+config DM_PMIC_DA9063
+ bool "Enable Driver Model for the Dialog DA9063 PMIC"
+ depends on DM_PMIC
+ help
+ This config enables implementation of driver-model pmic uclass features
+ for PMIC DA9063. The driver implements read/write operations.
+
+config SPL_DM_PMIC_DA9063
+ bool "Enable Driver Model for the Dialog DA9063 PMIC in SPL"
+ depends on DM_PMIC && SPL
+ help
+ This config enables implementation of driver-model pmic uclass features
+ for PMIC DA9063. The driver implements read/write operations.
+
config PMIC_AS3722
bool "Enable support for the Austria Micro Systems (AMS) AS7322 PMIC"
help
obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Flowbird
+ * Martin Fuzzey <martin.fuzzey@flowbird.group>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/da9063_pmic.h>
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = DA9063_LDO_DRIVER },
+ { .prefix = "b", .driver = DA9063_BUCK_DRIVER },
+ { },
+};
+
+/*
+ * The register map is non contiguous and attempts to read in the holes fail.
+ * But "pmic dump" tries to dump the full register map.
+ * So define the holes here so we can fix that.
+ */
+struct da9063_reg_hole {
+ u16 first;
+ u16 last;
+};
+
+static const struct da9063_reg_hole da9063_reg_holes[] = {
+ DA9063_REG_HOLE_1,
+ DA9063_REG_HOLE_2,
+ DA9063_REG_HOLE_3,
+ /* These aren't readable. I can't see why from the datasheet but
+ * attempts to read fail and the kernel marks them unreadable too,
+ */
+ {DA9063_REG_OTP_COUNT, DA9063_REG_OTP_DATA},
+};
+
+static int da9063_reg_count(struct udevice *dev)
+{
+ return DA9063_NUM_OF_REGS;
+}
+
+static bool da9063_reg_valid(uint reg)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(da9063_reg_holes); i++) {
+ const struct da9063_reg_hole *hole = &da9063_reg_holes[i];
+
+ if (reg >= hole->first && reg <= hole->last)
+ return false;
+ }
+
+ return true;
+}
+
+static int da9063_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ pr_err("write error to device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int da9063_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (!da9063_reg_valid(reg))
+ return -ENODATA;
+
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ pr_err("read error from device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int da9063_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static int da9063_probe(struct udevice *dev)
+{
+ return i2c_set_chip_addr_offset_mask(dev, 0x1);
+}
+
+static struct dm_pmic_ops da9063_ops = {
+ .reg_count = da9063_reg_count,
+ .read = da9063_read,
+ .write = da9063_write,
+};
+
+static const struct udevice_id da9063_ids[] = {
+ { .compatible = "dlg,da9063" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_da9063) = {
+ .name = "da9063_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = da9063_ids,
+ .bind = da9063_bind,
+ .probe = da9063_probe,
+ .ops = &da9063_ops,
+};
This config enables implementation of driver-model regulator uclass
features for regulators on ROHM BD71837 and BD71847 in SPL.
+config DM_REGULATOR_DA9063
+ bool "Enable Driver Model for REGULATOR DA9063"
+ depends on DM_REGULATOR && DM_PMIC_DA9063
+ help
+ This config enables implementation of driver-model regulator uclass
+ features for REGULATOR DA9063.
+ The driver implements get/set api for value, enable and mode for all
+ regulators. It also implements the get/set api for current for the
+ buck regulators.
+
+config SPL_DM_REGULATOR_DA9063
+ bool "Enable Driver Model for REGULATOR DA9063 in SPL"
+ depends on DM_REGULATOR && DM_PMIC_DA9063 && SPL
+ help
+ This config enables implementation of driver-model regulator uclass
+ features for REGULATOR DA9063.
+ The driver implements get/set api for value, enable and mode for all
+ regulators. It also implements the get/set api for current for the
+ buck regulators.
+
config DM_REGULATOR_PFUZE100
bool "Enable Driver Model for REGULATOR PFUZE100"
depends on DM_REGULATOR && DM_PMIC_PFUZE100
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Flowbird
+ * Martin Fuzzey <martin.fuzzey@flowbird.group>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power/da9063_pmic.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define DA9063_BUCK_EN 0x01
+#define DA9063_LDO_EN 0x01
+#define DA9063_VBUCK_MASK 0x7F
+#define DA9063_BUCK_SL 0x80
+#define DA9063_LDO_SL 0x80
+
+#define DA9063_VLDO1_MASK 0x3F
+#define DA9063_VLDO2_MASK 0x3F
+#define DA9063_VLDO3_MASK 0x7F
+#define DA9063_VLDO4_MASK 0x7F
+#define DA9063_VLDO5_MASK 0x3F
+#define DA9063_VLDO6_MASK 0x3F
+#define DA9063_VLDO7_MASK 0x3F
+#define DA9063_VLDO8_MASK 0x3F
+#define DA9063_VLDO9_MASK 0x3F
+#define DA9063_VLDO10_MASK 0x3F
+#define DA9063_VLDO11_MASK 0x3F
+
+#define DA9063_BUCK_MODE_MASK 0xC0
+#define DA9063_BUCK_MODE_MANUAL 0x00
+#define DA9063_BUCK_MODE_SLEEP 0x40
+#define DA9063_BUCK_MODE_SYNC 0x80
+#define DA9063_BUCK_MODE_AUTO 0xC0
+
+#define DA9063_BIO_ILIM_MASK 0x0F
+#define DA9063_BMEM_ILIM_MASK 0xF0
+#define DA9063_BPRO_ILIM_MASK 0x0F
+#define DA9063_BPERI_ILIM_MASK 0xF0
+#define DA9063_BCORE1_ILIM_MASK 0x0F
+#define DA9063_BCORE2_ILIM_MASK 0xF0
+
+struct da9063_reg_info {
+ uint min_uV;
+ uint step_uV;
+ uint max_uV;
+ uint min_uA;
+ uint step_uA;
+ uint max_uA;
+ uint en_reg;
+ uint vsel_reg;
+ uint mode_reg;
+ uint ilim_reg;
+ u8 en_mask;
+ u8 vsel_mask;
+ u8 ilim_mask;
+ const char *dt_node_name;
+ const int *current_limits;
+};
+
+struct da9063_priv {
+ const struct da9063_reg_info *reg_info;
+};
+
+static struct dm_regulator_mode da9063_ldo_modes[] = {
+ { .id = DA9063_LDOMODE_SLEEP,
+ .register_value = DA9063_LDO_SL, .name = "SLEEP" },
+ { .id = DA9063_LDOMODE_NORMAL,
+ .register_value = 0, .name = "NORMAL" },
+};
+
+#define DA9063_LDO(regl_name, min_mV, step_mV, max_mV) \
+ .min_uV = (min_mV) * 1000, \
+ .step_uV = (step_mV) * 1000, \
+ .max_uV = (max_mV) * 1000, \
+ .en_reg = DA9063_REG_##regl_name##_CONT, \
+ .en_mask = DA9063_LDO_EN, \
+ .vsel_reg = DA9063_REG_V##regl_name##_A, \
+ .vsel_mask = DA9063_V##regl_name##_MASK, \
+ .mode_reg = DA9063_REG_V##regl_name##_A \
+
+/* This array is directly indexed so must stay in numerical order */
+static const struct da9063_reg_info da9063_ldo_info[] = {
+ { DA9063_LDO(LDO1, 600, 20, 1860) },
+ { DA9063_LDO(LDO2, 600, 20, 1860) },
+ { DA9063_LDO(LDO3, 900, 20, 3440) },
+ { DA9063_LDO(LDO4, 900, 20, 3440) },
+ { DA9063_LDO(LDO5, 900, 50, 3600) },
+ { DA9063_LDO(LDO6, 900, 50, 3600) },
+ { DA9063_LDO(LDO7, 900, 50, 3600) },
+ { DA9063_LDO(LDO8, 900, 50, 3600) },
+ { DA9063_LDO(LDO9, 950, 50, 3600) },
+ { DA9063_LDO(LDO10, 900, 50, 3600) },
+ { DA9063_LDO(LDO11, 900, 50, 3600) },
+};
+
+static struct dm_regulator_mode da9063_buck_modes[] = {
+ { .id = DA9063_BUCKMODE_SLEEP,
+ .register_value = DA9063_BUCK_MODE_SLEEP, .name = "SLEEP" },
+ { .id = DA9063_BUCKMODE_SYNC,
+ .register_value = DA9063_BUCK_MODE_SYNC, .name = "SYNC" },
+ { .id = DA9063_BUCKMODE_AUTO,
+ .register_value = DA9063_BUCK_MODE_AUTO, .name = "AUTO" },
+};
+
+#define DA9063_BUCK(regl_name, dt_name, \
+ min_mV, step_mV, max_mV, \
+ min_mA, step_mA, max_mA, _ilim_reg) \
+ .dt_node_name = dt_name, \
+ .min_uV = (min_mV) * 1000, \
+ .step_uV = (step_mV) * 1000, \
+ .max_uV = (max_mV) * 1000, \
+ .min_uA = (min_mA) * 1000, \
+ .step_uA = (step_mA) * 1000, \
+ .max_uA = (max_mA) * 1000, \
+ .en_reg = DA9063_REG_##regl_name##_CONT, \
+ .en_mask = DA9063_BUCK_EN, \
+ .vsel_reg = DA9063_REG_V##regl_name##_A, \
+ .vsel_mask = DA9063_VBUCK_MASK, \
+ .mode_reg = DA9063_REG_##regl_name##_CFG, \
+ .ilim_reg = DA9063_REG_BUCK_ILIM_##_ilim_reg, \
+ .ilim_mask = DA9063_##regl_name##_ILIM_MASK
+
+static const struct da9063_reg_info da9063_buck_info[] = {
+ /* mV mA */
+ { DA9063_BUCK(BCORE1, "bcore1", 300, 10, 1570, 500, 100, 2000, C) },
+ { DA9063_BUCK(BCORE2, "bcore2", 300, 10, 1570, 500, 100, 2000, C) },
+ { DA9063_BUCK(BPRO, "bpro", 530, 10, 1800, 500, 100, 2000, B) },
+ { DA9063_BUCK(BMEM, "bmem", 800, 20, 3340, 1500, 100, 3000, A) },
+ { DA9063_BUCK(BIO, "bio", 800, 20, 3340, 1500, 100, 3000, A) },
+ { DA9063_BUCK(BPERI, "bperi", 800, 20, 3340, 1500, 100, 3000, B) },
+};
+
+static int da9063_get_enable(struct udevice *dev)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ int ret;
+
+ ret = pmic_reg_read(dev->parent, info->en_reg);
+ if (ret < 0)
+ return ret;
+
+ return ret & info->en_mask ? true : false;
+}
+
+static int da9063_set_enable(struct udevice *dev, bool enable)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+
+ return pmic_clrsetbits(dev->parent, info->en_reg,
+ info->en_mask, enable ? info->en_mask : 0);
+}
+
+static int da9063_get_voltage(struct udevice *dev)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ int ret;
+
+ ret = pmic_reg_read(dev->parent, info->vsel_reg);
+ if (ret < 0)
+ return ret;
+
+ return info->min_uV + (ret & info->vsel_mask) * info->step_uV;
+}
+
+static int da9063_set_voltage(struct udevice *dev, int uV)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ uint sel;
+
+ if (uV < info->min_uV || uV > info->max_uV)
+ return -EINVAL;
+
+ sel = (uV - info->min_uV) / info->step_uV;
+
+ return pmic_clrsetbits(dev->parent, info->vsel_reg,
+ info->vsel_mask, sel);
+}
+
+static const struct dm_regulator_mode
+ *da9063_find_mode_by_id(int id,
+ const struct dm_regulator_mode *modes,
+ uint mode_count)
+{
+ for (; mode_count; mode_count--) {
+ if (modes->id == id)
+ return modes;
+ modes++;
+ }
+ return NULL;
+}
+
+static int ldo_get_mode(struct udevice *dev)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ int val;
+
+ val = pmic_reg_read(dev->parent, info->mode_reg);
+ if (val < 0)
+ return val;
+
+ if (val & DA9063_LDO_SL)
+ return DA9063_LDOMODE_SLEEP;
+ else
+ return DA9063_LDOMODE_NORMAL;
+}
+
+static int ldo_set_mode(struct udevice *dev, int mode_id)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ const struct dm_regulator_mode *mode;
+
+ mode = da9063_find_mode_by_id(mode_id,
+ da9063_ldo_modes,
+ ARRAY_SIZE(da9063_ldo_modes));
+ if (!mode)
+ return -EINVAL;
+
+ return pmic_clrsetbits(dev->parent, info->mode_reg,
+ DA9063_LDO_SL, mode->register_value);
+}
+
+static int buck_get_mode(struct udevice *dev)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ int i;
+ int val;
+
+ val = pmic_reg_read(dev->parent, info->mode_reg);
+ if (val < 0)
+ return val;
+
+ val &= DA9063_BUCK_MODE_MASK;
+ if (val == DA9063_BUCK_MODE_MANUAL) {
+ val = pmic_reg_read(dev->parent, info->vsel_reg);
+ if (val < 0)
+ return val;
+
+ if (val & DA9063_BUCK_SL)
+ return DA9063_BUCKMODE_SLEEP;
+ else
+ return DA9063_BUCKMODE_SYNC;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(da9063_buck_modes); i++) {
+ if (da9063_buck_modes[i].register_value == val)
+ return da9063_buck_modes[i].id;
+ }
+
+ return -EINVAL;
+}
+
+static int buck_set_mode(struct udevice *dev, int mode_id)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ const struct dm_regulator_mode *mode;
+
+ mode = da9063_find_mode_by_id(mode_id,
+ da9063_buck_modes,
+ ARRAY_SIZE(da9063_buck_modes));
+ if (!mode)
+ return -EINVAL;
+
+ return pmic_clrsetbits(dev->parent, info->mode_reg,
+ DA9063_BUCK_MODE_MASK, mode->register_value);
+}
+
+static int buck_get_current_limit(struct udevice *dev)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ int val;
+
+ val = pmic_reg_read(dev->parent, info->ilim_reg);
+ if (val < 0)
+ return val;
+
+ val &= info->ilim_mask;
+ val >>= (ffs(info->ilim_mask) - 1);
+
+ return info->min_uA + val * info->step_uA;
+}
+
+static int buck_set_current_limit(struct udevice *dev, int uA)
+{
+ const struct da9063_priv *priv = dev->priv;
+ const struct da9063_reg_info *info = priv->reg_info;
+ int val;
+
+ if (uA < info->min_uA || uA > info->max_uA)
+ return -EINVAL;
+
+ val = (uA - info->min_uA) / info->step_uA;
+ val <<= (ffs(info->ilim_mask) - 1);
+
+ return pmic_clrsetbits(dev->parent, info->ilim_reg,
+ info->ilim_mask, val);
+}
+
+static int da9063_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct da9063_priv *priv = dev->priv;
+
+ /* LDOs are named numerically in DT so can directly index */
+ if (dev->driver_data < 1 ||
+ dev->driver_data > ARRAY_SIZE(da9063_ldo_info))
+ return -EINVAL;
+ priv->reg_info = &da9063_ldo_info[dev->driver_data - 1];
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+ uc_pdata->mode = da9063_ldo_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(da9063_ldo_modes);
+
+ return 0;
+}
+
+static int da9063_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct da9063_priv *priv = dev->priv;
+ int i;
+
+ /* Bucks have names rather than numbers so need to match with DT */
+ for (i = 0; i < ARRAY_SIZE(da9063_buck_info); i++) {
+ const struct da9063_reg_info *info = &da9063_buck_info[i];
+
+ if (!strcmp(info->dt_node_name, dev->name)) {
+ priv->reg_info = info;
+ break;
+ }
+ }
+ if (!priv->reg_info)
+ return -ENODEV;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+ uc_pdata->mode = da9063_buck_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(da9063_buck_modes);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops da9063_ldo_ops = {
+ .get_value = da9063_get_voltage,
+ .set_value = da9063_set_voltage,
+ .get_enable = da9063_get_enable,
+ .set_enable = da9063_set_enable,
+ .get_mode = ldo_get_mode,
+ .set_mode = ldo_set_mode,
+};
+
+U_BOOT_DRIVER(da9063_ldo) = {
+ .name = DA9063_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &da9063_ldo_ops,
+ .probe = da9063_ldo_probe,
+ .priv_auto_alloc_size = sizeof(struct da9063_priv),
+};
+
+static const struct dm_regulator_ops da9063_buck_ops = {
+ .get_value = da9063_get_voltage,
+ .set_value = da9063_set_voltage,
+ .get_enable = da9063_get_enable,
+ .set_enable = da9063_set_enable,
+ .get_mode = buck_get_mode,
+ .set_mode = buck_set_mode,
+ .get_current = buck_get_current_limit,
+ .set_current = buck_set_current_limit,
+};
+
+U_BOOT_DRIVER(da9063_buck) = {
+ .name = DA9063_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &da9063_buck_ops,
+ .probe = da9063_buck_probe,
+ .priv_auto_alloc_size = sizeof(struct da9063_priv),
+};
#include <linux/bitrev.h>
#include <rtc.h>
-#define S35390A_CMD_STATUS1 0x30
-#define S35390A_CMD_STATUS2 0x31
-#define S35390A_CMD_TIME1 0x32
-#define S35390A_CMD_TIME2 0x33
-#define S35390A_CMD_INT2_REG1 0x35
+#define S35390A_CHIP_ADDR 0x30
+
+#define S35390A_CMD_STATUS1 0x0
+#define S35390A_CMD_STATUS2 0x1
+#define S35390A_CMD_TIME1 0x2
+#define S35390A_CMD_TIME2 0x3
+#define S35390A_CMD_INT2_REG1 0x5
#define S35390A_BYTE_YEAR 0
#define S35390A_BYTE_MONTH 1
int ret;
#ifdef CONFIG_DM_RTC
- /* TODO: we need to tweak the chip address to reg */
- ret = dm_i2c_read(dev, 0, buf, len);
+ ret = dm_i2c_read(dev, reg, buf, len);
#else
(void)dev;
- ret = i2c_read(reg, 0, -1, buf, len);
+ ret = i2c_read(S35390A_CHIP_ADDR | reg, 0, -1, buf, len);
#endif
return ret;
int ret;
#ifdef CONFIG_DM_RTC
- /* TODO: we need to tweak the chip address to reg */
- ret = dm_i2c_write(dev, 0, buf, 1);
+ ret = dm_i2c_write(dev, reg, buf, len);
#else
(void)dev;
- ret = i2c_write(reg, 0, 0, buf, len);
+ ret = i2c_write(S35390A_CHIP_ADDR | reg, 0, 0, buf, len);
#endif
return ret;
static int s35392a_probe(struct udevice *dev)
{
+#if defined(CONFIG_DM_RTC)
+ /* 3-bit "command", or register, is encoded within the device address.
+ */
+ i2c_set_chip_offset_len(dev, 0);
+ i2c_set_chip_addr_offset_mask(dev, 0x7);
+#endif
+
s35392a_rtc_init(dev);
return 0;
}
used to access the SPI NOR flash on platforms embedding this
Marvell IP core.
+config NXP_FSPI
+ bool "NXP FlexSPI driver"
+ depends on SPI_MEM
+ help
+ Enable the NXP FlexSPI (FSPI) driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this NXP IP core.
+
config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
+obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
#include <common.h>
#include <clk.h>
+#include <asm-generic/io.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
#include <reset.h>
#include <spi.h>
+#include <spi-mem.h>
#include <linux/errno.h>
+#include <linux/sizes.h>
#include "cadence_qspi.h"
#define CQSPI_STIG_READ 0
#define CQSPI_STIG_WRITE 1
-#define CQSPI_INDIRECT_READ 2
-#define CQSPI_INDIRECT_WRITE 3
+#define CQSPI_READ 2
+#define CQSPI_WRITE 3
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
{
return 0;
}
+static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
+{
+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(len, idcode, 1));
+
+ return cadence_qspi_apb_command_read(reg_base, &op);
+}
+
/* Calibration sequence to determine the read data capture delay register */
static int spi_calibration(struct udevice *bus, uint hz)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
- u8 opcode_rdid = 0x9F;
unsigned int idcode = 0, temp = 0;
int err = 0, i, range_lo = -1, range_hi = -1;
cadence_qspi_apb_controller_enable(base);
/* read the ID which will be our golden value */
- err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
- 3, (u8 *)&idcode);
+ err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
if (err) {
puts("SF: Calibration failed (read)\n");
return err;
cadence_qspi_apb_controller_enable(base);
/* issue a RDID to get the ID value */
- err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
- 3, (u8 *)&temp);
+ err = cadence_spi_read_id(base, 3, (u8 *)&temp);
if (err) {
puts("SF: Calibration failed (read)\n");
return err;
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
+ struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
/* Disable QSPI */
/* Set SPI mode */
cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
+ /* Enable Direct Access Controller */
+ if (plat->use_dac_mode)
+ cadence_qspi_apb_dac_mode_enable(priv->regbase);
+
/* Enable QSPI */
cadence_qspi_apb_controller_enable(priv->regbase);
return 0;
}
-static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int cadence_spi_mem_exec_op(struct spi_slave *spi,
+ const struct spi_mem_op *op)
{
- struct udevice *bus = dev->parent;
+ struct udevice *bus = spi->dev->parent;
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
void *base = priv->regbase;
- u8 *cmd_buf = priv->cmd_buf;
- size_t data_bytes;
int err = 0;
- u32 mode = CQSPI_STIG_WRITE;
-
- if (flags & SPI_XFER_BEGIN) {
- /* copy command to local buffer */
- priv->cmd_len = bitlen / 8;
- memcpy(cmd_buf, dout, priv->cmd_len);
- }
-
- if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
- /* if start and end bit are set, the data bytes is 0. */
- data_bytes = 0;
- } else {
- data_bytes = bitlen / 8;
- }
- debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
+ u32 mode;
/* Set Chip select */
- cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
+ cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
plat->is_decoded_cs);
- if ((flags & SPI_XFER_END) || (flags == 0)) {
- if (priv->cmd_len == 0) {
- printf("QSPI: Error, command is empty.\n");
- return -1;
- }
-
- if (din && data_bytes) {
- /* read */
- /* Use STIG if no address. */
- if (!CQSPI_IS_ADDR(priv->cmd_len))
- mode = CQSPI_STIG_READ;
- else
- mode = CQSPI_INDIRECT_READ;
- } else if (dout && !(flags & SPI_XFER_BEGIN)) {
- /* write */
- if (!CQSPI_IS_ADDR(priv->cmd_len))
- mode = CQSPI_STIG_WRITE;
- else
- mode = CQSPI_INDIRECT_WRITE;
- }
-
- switch (mode) {
- case CQSPI_STIG_READ:
- err = cadence_qspi_apb_command_read(
- base, priv->cmd_len, cmd_buf,
- data_bytes, din);
+ if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
+ if (!op->addr.nbytes)
+ mode = CQSPI_STIG_READ;
+ else
+ mode = CQSPI_READ;
+ } else {
+ if (!op->addr.nbytes || !op->data.buf.out)
+ mode = CQSPI_STIG_WRITE;
+ else
+ mode = CQSPI_WRITE;
+ }
+ switch (mode) {
+ case CQSPI_STIG_READ:
+ err = cadence_qspi_apb_command_read(base, op);
break;
- case CQSPI_STIG_WRITE:
- err = cadence_qspi_apb_command_write(base,
- priv->cmd_len, cmd_buf,
- data_bytes, dout);
+ case CQSPI_STIG_WRITE:
+ err = cadence_qspi_apb_command_write(base, op);
break;
- case CQSPI_INDIRECT_READ:
- err = cadence_qspi_apb_indirect_read_setup(plat,
- priv->cmd_len, dm_plat->mode, cmd_buf);
- if (!err) {
- err = cadence_qspi_apb_indirect_read_execute
- (plat, data_bytes, din);
- }
+ case CQSPI_READ:
+ err = cadence_qspi_apb_read_setup(plat, op);
+ if (!err)
+ err = cadence_qspi_apb_read_execute(plat, op);
break;
- case CQSPI_INDIRECT_WRITE:
- err = cadence_qspi_apb_indirect_write_setup
- (plat, priv->cmd_len, dm_plat->mode, cmd_buf);
- if (!err) {
- err = cadence_qspi_apb_indirect_write_execute
- (plat, data_bytes, dout);
- }
+ case CQSPI_WRITE:
+ err = cadence_qspi_apb_write_setup(plat, op);
+ if (!err)
+ err = cadence_qspi_apb_write_execute(plat, op);
+ break;
+ default:
+ err = -1;
break;
- default:
- err = -1;
- break;
- }
-
- if (flags & SPI_XFER_END) {
- /* clear command buffer */
- memset(cmd_buf, 0, sizeof(priv->cmd_buf));
- priv->cmd_len = 0;
- }
}
return err;
int ret;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
- plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
+ plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
+ &plat->ahbsize);
plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
plat->trigger_address = dev_read_u32_default(bus,
"cdns,trigger-address",
0);
+ /* Use DAC mode only when MMIO window is at least 8M wide */
+ if (plat->ahbsize >= SZ_8M)
+ plat->use_dac_mode = true;
/* All other paramters are embedded in the child node */
subnode = dev_read_first_subnode(bus);
return 0;
}
+static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
+ .exec_op = cadence_spi_mem_exec_op,
+};
+
static const struct dm_spi_ops cadence_spi_ops = {
- .xfer = cadence_spi_xfer,
.set_speed = cadence_spi_set_speed,
.set_mode = cadence_spi_set_mode,
+ .mem_ops = &cadence_spi_mem_ops,
/*
* cs_info is not needed, since we require all chip selects to be
* in the device tree explicitly
static const struct udevice_id cadence_spi_ids[] = {
{ .compatible = "cdns,qspi-nor" },
+ { .compatible = "ti,am654-ospi" },
{ }
};
u32 fifo_depth;
u32 fifo_width;
u32 trigger_address;
+ fdt_addr_t ahbsize;
+ bool use_dac_mode;
/* Flash parameters */
u32 page_size;
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
+void cadence_qspi_apb_dac_mode_enable(void *reg_base);
int cadence_qspi_apb_command_read(void *reg_base_addr,
- unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
+ const struct spi_mem_op *op);
int cadence_qspi_apb_command_write(void *reg_base_addr,
- unsigned int cmdlen, const u8 *cmdbuf,
- unsigned int txlen, const u8 *txbuf);
+ const struct spi_mem_op *op);
-int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
- unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
-int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
- unsigned int rxlen, u8 *rxbuf);
-int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
- unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
-int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
- unsigned int txlen, const u8 *txbuf);
+int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op);
+int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op);
+int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op);
+int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op);
void cadence_qspi_apb_chipselect(void *reg_base,
unsigned int chip_select, unsigned int decoder_enable);
#include <common.h>
#include <asm/io.h>
+#include <dma.h>
#include <linux/errno.h>
#include <wait_bit.h>
#include <spi.h>
+#include <spi-mem.h>
#include <malloc.h>
#include "cadence_qspi.h"
#define CQSPI_INST_TYPE_SINGLE 0
#define CQSPI_INST_TYPE_DUAL 1
#define CQSPI_INST_TYPE_QUAD 2
+#define CQSPI_INST_TYPE_OCTAL 3
#define CQSPI_STIG_DATA_LEN_MAX 8
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
-static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
- unsigned int addr_width)
-{
- unsigned int addr;
-
- addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
-
- if (addr_width == 4)
- addr = (addr << 8) | addr_buf[3];
-
- return addr;
-}
-
void cadence_qspi_apb_controller_enable(void *reg_base)
{
unsigned int reg;
writel(reg, reg_base + CQSPI_REG_CONFIG);
}
+void cadence_qspi_apb_dac_mode_enable(void *reg_base)
+{
+ unsigned int reg;
+
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ reg |= CQSPI_REG_CONFIG_DIRECT;
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+}
+
/* Return 1 if idle, otherwise return 0 (busy). */
static unsigned int cadence_qspi_wait_idle(void *reg_base)
{
}
/* For command RDID, RDSR. */
-int cadence_qspi_apb_command_read(void *reg_base,
- unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
- u8 *rxbuf)
+int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
{
unsigned int reg;
unsigned int read_len;
int status;
+ unsigned int rxlen = op->data.nbytes;
+ void *rxbuf = op->data.buf.in;
- if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
- printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
- cmdlen, rxlen);
+ if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
+ printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
return -EINVAL;
}
- reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+ reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
}
/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
-int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
- const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
+int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
{
unsigned int reg = 0;
- unsigned int addr_value;
unsigned int wr_data;
unsigned int wr_len;
+ unsigned int txlen = op->data.nbytes;
+ const void *txbuf = op->data.buf.out;
+ u32 addr;
+
+ /* Reorder address to SPI bus order if only transferring address */
+ if (!txlen) {
+ addr = cpu_to_be32(op->addr.val);
+ if (op->addr.nbytes == 3)
+ addr >>= 8;
+ txbuf = &addr;
+ txlen = op->addr.nbytes;
+ }
- if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
- printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
- cmdlen, txlen);
+ if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
+ printf("QSPI: Invalid input arguments txlen %u\n", txlen);
return -EINVAL;
}
- reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
-
- if (cmdlen == 4 || cmdlen == 5) {
- /* Command with address */
- reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
- /* Number of bytes to write. */
- reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
- << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
- /* Get address */
- addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
- cmdlen >= 5 ? 4 : 3);
-
- writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
- }
+ reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
if (txlen) {
/* writing data = yes */
}
/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
-int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
- unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
+int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op)
{
unsigned int reg;
unsigned int rd_reg;
- unsigned int addr_value;
unsigned int dummy_clk;
- unsigned int dummy_bytes;
- unsigned int addr_bytes;
-
- /*
- * Identify addr_byte. All NOR flash device drivers are using fast read
- * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
- * With that, the length is in value of 5 or 6. Only FRAM chip from
- * ramtron using normal read (which won't need dummy byte).
- * Unlikely NOR flash using normal read due to performance issue.
- */
- if (cmdlen >= 5)
- /* to cater fast read where cmd + addr + dummy */
- addr_bytes = cmdlen - 2;
- else
- /* for normal read (only ramtron as of now) */
- addr_bytes = cmdlen - 1;
+ unsigned int dummy_bytes = op->dummy.nbytes;
/* Setup the indirect trigger address */
writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
- rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
+ rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
- if (rx_width & SPI_RX_QUAD)
+ if (op->data.buswidth == 8)
+ /* Instruction and address at DQ0, data at DQ0-7. */
+ rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
+ else if (op->data.buswidth == 4)
/* Instruction and address at DQ0, data at DQ0-3. */
rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
- /* Get address */
- addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
- writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+ writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
- /* The remaining lenght is dummy bytes. */
- dummy_bytes = cmdlen - addr_bytes - 1;
if (dummy_bytes) {
if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
- rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
-#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
- writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
-#else
- writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
-#endif
-
/* Convert to clock cycles. */
dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
- /* Need to minus the mode byte (8 clocks). */
- dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
if (dummy_clk)
rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
/* set device size */
reg = readl(plat->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
- reg |= (addr_bytes - 1);
+ reg |= (op->addr.nbytes - 1);
writel(reg, plat->regbase + CQSPI_REG_SIZE);
return 0;
}
return -ETIMEDOUT;
}
-int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
- unsigned int n_rx, u8 *rxbuf)
+static int
+cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
+ unsigned int n_rx, u8 *rxbuf)
{
unsigned int remaining = n_rx;
unsigned int bytes_to_read = 0;
return ret;
}
+int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op)
+{
+ u64 from = op->addr.val;
+ void *buf = op->data.buf.in;
+ size_t len = op->data.nbytes;
+
+ if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
+ if (len < 256 ||
+ dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
+ memcpy_fromio(buf, plat->ahbbase + from, len);
+ }
+ if (!cadence_qspi_wait_idle(plat->regbase))
+ return -EIO;
+ return 0;
+ }
+
+ return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
+}
+
/* Opcode + Address (3/4 bytes) */
-int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
- unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf)
+int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op)
{
unsigned int reg;
- unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
- if (cmdlen < 4 || cmdbuf == NULL) {
- printf("QSPI: Invalid input argument, len %d cmdbuf %p\n",
- cmdlen, cmdbuf);
- return -EINVAL;
- }
/* Setup the indirect trigger address */
writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
- reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
-
- if (tx_width & SPI_TX_QUAD)
- reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
-
+ reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
- /* Setup write address. */
- reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
- writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
+ writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
reg = readl(plat->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
- reg |= (addr_bytes - 1);
+ reg |= (op->addr.nbytes - 1);
writel(reg, plat->regbase + CQSPI_REG_SIZE);
return 0;
}
-int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
- unsigned int n_tx, const u8 *txbuf)
+static int
+cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
+ unsigned int n_tx, const u8 *txbuf)
{
unsigned int page_size = plat->page_size;
unsigned int remaining = n_tx;
return ret;
}
+int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
+ const struct spi_mem_op *op)
+{
+ u32 to = op->addr.val;
+ const void *buf = op->data.buf.out;
+ size_t len = op->data.nbytes;
+
+ if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
+ memcpy_toio(plat->ahbbase + to, buf, len);
+ if (!cadence_qspi_wait_idle(plat->regbase))
+ return -EIO;
+ return 0;
+ }
+
+ return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
+}
+
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
{
unsigned int reg;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP FlexSPI(FSPI) controller driver.
+ *
+ * Copyright (c) 2019 Michael Walle <michael@walle.cc>
+ * Copyright (c) 2019 NXP
+ *
+ * This driver was originally ported from the linux kernel v5.4-rc3, which had
+ * the following notes:
+ *
+ * FlexSPI is a flexsible SPI host controller which supports two SPI
+ * channels and up to 4 external devices. Each channel supports
+ * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
+ * data lines).
+ *
+ * FlexSPI controller is driven by the LUT(Look-up Table) registers
+ * LUT registers are a look-up-table for sequences of instructions.
+ * A valid sequence consists of four LUT registers.
+ * Maximum 32 LUT sequences can be programmed simultaneously.
+ *
+ * LUTs are being created at run-time based on the commands passed
+ * from the spi-mem framework, thus using single LUT index.
+ *
+ * Software triggered Flash read/write access by IP Bus.
+ *
+ * Memory mapped read access by AHB Bus.
+ *
+ * Based on SPI MEM interface and spi-fsl-qspi.c driver.
+ *
+ * Author:
+ * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
+ * Boris Brezillon <bbrezillon@kernel.org>
+ * Frieder Schrempf <frieder.schrempf@kontron.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <dm.h>
+#include <clk.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+#include <linux/iopoll.h>
+#include <linux/bug.h>
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (31).
+ */
+#define SEQID_LUT 31
+
+/* Registers used by the driver */
+#define FSPI_MCR0 0x00
+#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
+#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
+#define FSPI_MCR0_LEARN_EN BIT(15)
+#define FSPI_MCR0_SCRFRUN_EN BIT(14)
+#define FSPI_MCR0_OCTCOMB_EN BIT(13)
+#define FSPI_MCR0_DOZE_EN BIT(12)
+#define FSPI_MCR0_HSEN BIT(11)
+#define FSPI_MCR0_SERCLKDIV BIT(8)
+#define FSPI_MCR0_ATDF_EN BIT(7)
+#define FSPI_MCR0_ARDF_EN BIT(6)
+#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
+#define FSPI_MCR0_END_CFG(x) ((x) << 2)
+#define FSPI_MCR0_MDIS BIT(1)
+#define FSPI_MCR0_SWRST BIT(0)
+
+#define FSPI_MCR1 0x04
+#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
+#define FSPI_MCR1_AHB_TIMEOUT(x) (x)
+
+#define FSPI_MCR2 0x08
+#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
+#define FSPI_MCR2_SAMEDEVICEEN BIT(15)
+#define FSPI_MCR2_CLRLRPHS BIT(14)
+#define FSPI_MCR2_ABRDATSZ BIT(8)
+#define FSPI_MCR2_ABRLEARN BIT(7)
+#define FSPI_MCR2_ABR_READ BIT(6)
+#define FSPI_MCR2_ABRWRITE BIT(5)
+#define FSPI_MCR2_ABRDUMMY BIT(4)
+#define FSPI_MCR2_ABR_MODE BIT(3)
+#define FSPI_MCR2_ABRCADDR BIT(2)
+#define FSPI_MCR2_ABRRADDR BIT(1)
+#define FSPI_MCR2_ABR_CMD BIT(0)
+
+#define FSPI_AHBCR 0x0c
+#define FSPI_AHBCR_RDADDROPT BIT(6)
+#define FSPI_AHBCR_PREF_EN BIT(5)
+#define FSPI_AHBCR_BUFF_EN BIT(4)
+#define FSPI_AHBCR_CACH_EN BIT(3)
+#define FSPI_AHBCR_CLRTXBUF BIT(2)
+#define FSPI_AHBCR_CLRRXBUF BIT(1)
+#define FSPI_AHBCR_PAR_EN BIT(0)
+
+#define FSPI_INTEN 0x10
+#define FSPI_INTEN_SCLKSBWR BIT(9)
+#define FSPI_INTEN_SCLKSBRD BIT(8)
+#define FSPI_INTEN_DATALRNFL BIT(7)
+#define FSPI_INTEN_IPTXWE BIT(6)
+#define FSPI_INTEN_IPRXWA BIT(5)
+#define FSPI_INTEN_AHBCMDERR BIT(4)
+#define FSPI_INTEN_IPCMDERR BIT(3)
+#define FSPI_INTEN_AHBCMDGE BIT(2)
+#define FSPI_INTEN_IPCMDGE BIT(1)
+#define FSPI_INTEN_IPCMDDONE BIT(0)
+
+#define FSPI_INTR 0x14
+#define FSPI_INTR_SCLKSBWR BIT(9)
+#define FSPI_INTR_SCLKSBRD BIT(8)
+#define FSPI_INTR_DATALRNFL BIT(7)
+#define FSPI_INTR_IPTXWE BIT(6)
+#define FSPI_INTR_IPRXWA BIT(5)
+#define FSPI_INTR_AHBCMDERR BIT(4)
+#define FSPI_INTR_IPCMDERR BIT(3)
+#define FSPI_INTR_AHBCMDGE BIT(2)
+#define FSPI_INTR_IPCMDGE BIT(1)
+#define FSPI_INTR_IPCMDDONE BIT(0)
+
+#define FSPI_LUTKEY 0x18
+#define FSPI_LUTKEY_VALUE 0x5AF05AF0
+
+#define FSPI_LCKCR 0x1C
+
+#define FSPI_LCKER_LOCK 0x1
+#define FSPI_LCKER_UNLOCK 0x2
+
+#define FSPI_BUFXCR_INVALID_MSTRID 0xE
+#define FSPI_AHBRX_BUF0CR0 0x20
+#define FSPI_AHBRX_BUF1CR0 0x24
+#define FSPI_AHBRX_BUF2CR0 0x28
+#define FSPI_AHBRX_BUF3CR0 0x2C
+#define FSPI_AHBRX_BUF4CR0 0x30
+#define FSPI_AHBRX_BUF5CR0 0x34
+#define FSPI_AHBRX_BUF6CR0 0x38
+#define FSPI_AHBRX_BUF7CR0 0x3C
+#define FSPI_AHBRXBUF0CR7_PREF BIT(31)
+
+#define FSPI_AHBRX_BUF0CR1 0x40
+#define FSPI_AHBRX_BUF1CR1 0x44
+#define FSPI_AHBRX_BUF2CR1 0x48
+#define FSPI_AHBRX_BUF3CR1 0x4C
+#define FSPI_AHBRX_BUF4CR1 0x50
+#define FSPI_AHBRX_BUF5CR1 0x54
+#define FSPI_AHBRX_BUF6CR1 0x58
+#define FSPI_AHBRX_BUF7CR1 0x5C
+
+#define FSPI_FLSHA1CR0 0x60
+#define FSPI_FLSHA2CR0 0x64
+#define FSPI_FLSHB1CR0 0x68
+#define FSPI_FLSHB2CR0 0x6C
+#define FSPI_FLSHXCR0_SZ_KB 10
+#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
+
+#define FSPI_FLSHA1CR1 0x70
+#define FSPI_FLSHA2CR1 0x74
+#define FSPI_FLSHB1CR1 0x78
+#define FSPI_FLSHB2CR1 0x7C
+#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
+#define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
+#define FSPI_FLSHXCR1_WA BIT(10)
+#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
+#define FSPI_FLSHXCR1_TCSS(x) (x)
+
+#define FSPI_FLSHA1CR2 0x80
+#define FSPI_FLSHA2CR2 0x84
+#define FSPI_FLSHB1CR2 0x88
+#define FSPI_FLSHB2CR2 0x8C
+#define FSPI_FLSHXCR2_CLRINSP BIT(24)
+#define FSPI_FLSHXCR2_AWRWAIT BIT(16)
+#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
+#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
+#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
+#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
+
+#define FSPI_IPCR0 0xA0
+
+#define FSPI_IPCR1 0xA4
+#define FSPI_IPCR1_IPAREN BIT(31)
+#define FSPI_IPCR1_SEQNUM_SHIFT 24
+#define FSPI_IPCR1_SEQID_SHIFT 16
+#define FSPI_IPCR1_IDATSZ(x) (x)
+
+#define FSPI_IPCMD 0xB0
+#define FSPI_IPCMD_TRG BIT(0)
+
+#define FSPI_DLPR 0xB4
+
+#define FSPI_IPRXFCR 0xB8
+#define FSPI_IPRXFCR_CLR BIT(0)
+#define FSPI_IPRXFCR_DMA_EN BIT(1)
+#define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
+
+#define FSPI_IPTXFCR 0xBC
+#define FSPI_IPTXFCR_CLR BIT(0)
+#define FSPI_IPTXFCR_DMA_EN BIT(1)
+#define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
+
+#define FSPI_DLLACR 0xC0
+#define FSPI_DLLACR_OVRDEN BIT(8)
+
+#define FSPI_DLLBCR 0xC4
+#define FSPI_DLLBCR_OVRDEN BIT(8)
+
+#define FSPI_STS0 0xE0
+#define FSPI_STS0_DLPHB(x) ((x) << 8)
+#define FSPI_STS0_DLPHA(x) ((x) << 4)
+#define FSPI_STS0_CMD_SRC(x) ((x) << 2)
+#define FSPI_STS0_ARB_IDLE BIT(1)
+#define FSPI_STS0_SEQ_IDLE BIT(0)
+
+#define FSPI_STS1 0xE4
+#define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
+#define FSPI_STS1_IP_ERRID(x) ((x) << 16)
+#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
+#define FSPI_STS1_AHB_ERRID(x) (x)
+
+#define FSPI_AHBSPNST 0xEC
+#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
+#define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
+#define FSPI_AHBSPNST_ACTIVE BIT(0)
+
+#define FSPI_IPRXFSTS 0xF0
+#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
+#define FSPI_IPRXFSTS_FILL(x) (x)
+
+#define FSPI_IPTXFSTS 0xF4
+#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
+#define FSPI_IPTXFSTS_FILL(x) (x)
+
+#define FSPI_RFDR 0x100
+#define FSPI_TFDR 0x180
+
+#define FSPI_LUT_BASE 0x200
+#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
+#define FSPI_LUT_REG(idx) \
+ (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
+
+/* register map end */
+
+/* Instruction set for the LUT register. */
+#define LUT_STOP 0x00
+#define LUT_CMD 0x01
+#define LUT_ADDR 0x02
+#define LUT_CADDR_SDR 0x03
+#define LUT_MODE 0x04
+#define LUT_MODE2 0x05
+#define LUT_MODE4 0x06
+#define LUT_MODE8 0x07
+#define LUT_NXP_WRITE 0x08
+#define LUT_NXP_READ 0x09
+#define LUT_LEARN_SDR 0x0A
+#define LUT_DATSZ_SDR 0x0B
+#define LUT_DUMMY 0x0C
+#define LUT_DUMMY_RWDS_SDR 0x0D
+#define LUT_JMP_ON_CS 0x1F
+#define LUT_CMD_DDR 0x21
+#define LUT_ADDR_DDR 0x22
+#define LUT_CADDR_DDR 0x23
+#define LUT_MODE_DDR 0x24
+#define LUT_MODE2_DDR 0x25
+#define LUT_MODE4_DDR 0x26
+#define LUT_MODE8_DDR 0x27
+#define LUT_WRITE_DDR 0x28
+#define LUT_READ_DDR 0x29
+#define LUT_LEARN_DDR 0x2A
+#define LUT_DATSZ_DDR 0x2B
+#define LUT_DUMMY_DDR 0x2C
+#define LUT_DUMMY_RWDS_DDR 0x2D
+
+/*
+ * Calculate number of required PAD bits for LUT register.
+ *
+ * The pad stands for the number of IO lines [0:7].
+ * For example, the octal read needs eight IO lines,
+ * so you should use LUT_PAD(8). This macro
+ * returns 3 i.e. use eight (2^3) IP lines for read.
+ */
+#define LUT_PAD(x) (fls(x) - 1)
+
+/*
+ * Macro for constructing the LUT entries with the following
+ * register layout:
+ *
+ * ---------------------------------------------------
+ * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
+ * ---------------------------------------------------
+ */
+#define PAD_SHIFT 8
+#define INSTR_SHIFT 10
+#define OPRND_SHIFT 16
+
+/* Macros for constructing the LUT register. */
+#define LUT_DEF(idx, ins, pad, opr) \
+ ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
+ (opr)) << (((idx) % 2) * OPRND_SHIFT))
+
+#define POLL_TOUT 5000
+#define NXP_FSPI_MAX_CHIPSELECT 4
+
+struct nxp_fspi_devtype_data {
+ unsigned int rxfifo;
+ unsigned int txfifo;
+ unsigned int ahb_buf_size;
+ unsigned int quirks;
+ bool little_endian;
+};
+
+static const struct nxp_fspi_devtype_data lx2160a_data = {
+ .rxfifo = SZ_512, /* (64 * 64 bits) */
+ .txfifo = SZ_1K, /* (128 * 64 bits) */
+ .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
+ .quirks = 0,
+ .little_endian = true, /* little-endian */
+};
+
+struct nxp_fspi {
+ struct udevice *dev;
+ void __iomem *iobase;
+ void __iomem *ahb_addr;
+ u32 memmap_phy;
+ u32 memmap_phy_size;
+ struct clk clk, clk_en;
+ const struct nxp_fspi_devtype_data *devtype_data;
+};
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The FSPI controller's endianness is independent of
+ * the CPU core's endianness. So far, although the CPU
+ * core is little-endian the FSPI controller can use
+ * big-endian or little-endian.
+ */
+static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
+{
+ if (f->devtype_data->little_endian)
+ out_le32(addr, val);
+ else
+ out_be32(addr, val);
+}
+
+static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
+{
+ if (f->devtype_data->little_endian)
+ return in_le32(addr);
+ else
+ return in_be32(addr);
+}
+
+static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
+{
+ switch (width) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ return 0;
+ }
+
+ return -ENOTSUPP;
+}
+
+static bool nxp_fspi_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct nxp_fspi *f;
+ struct udevice *bus;
+ int ret;
+
+ bus = slave->dev->parent;
+ f = dev_get_priv(bus);
+
+ ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
+
+ if (op->addr.nbytes)
+ ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
+
+ if (op->dummy.nbytes)
+ ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
+
+ if (op->data.nbytes)
+ ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
+
+ if (ret)
+ return false;
+
+ /*
+ * The number of address bytes should be equal to or less than 4 bytes.
+ */
+ if (op->addr.nbytes > 4)
+ return false;
+
+ /*
+ * If requested address value is greater than controller assigned
+ * memory mapped space, return error as it didn't fit in the range
+ * of assigned address space.
+ */
+ if (op->addr.val >= f->memmap_phy_size)
+ return false;
+
+ /* Max 64 dummy clock cycles supported */
+ if (op->dummy.buswidth &&
+ (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
+ return false;
+
+ /* Max data length, check controller limits and alignment */
+ if (op->data.dir == SPI_MEM_DATA_IN &&
+ (op->data.nbytes > f->devtype_data->ahb_buf_size ||
+ (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
+ !IS_ALIGNED(op->data.nbytes, 8))))
+ return false;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT &&
+ op->data.nbytes > f->devtype_data->txfifo)
+ return false;
+
+ return true;
+}
+
+/* Instead of busy looping invoke readl_poll_timeout functionality. */
+static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
+ u32 mask, u32 delay_us,
+ u32 timeout_us, bool c)
+{
+ u32 reg;
+
+ if (!f->devtype_data->little_endian)
+ mask = (u32)cpu_to_be32(mask);
+
+ if (c)
+ return readl_poll_timeout(base, reg, (reg & mask),
+ timeout_us);
+ else
+ return readl_poll_timeout(base, reg, !(reg & mask),
+ timeout_us);
+}
+
+/*
+ * If the slave device content being changed by Write/Erase, need to
+ * invalidate the AHB buffer. This can be achieved by doing the reset
+ * of controller after setting MCR0[SWRESET] bit.
+ */
+static inline void nxp_fspi_invalid(struct nxp_fspi *f)
+{
+ u32 reg;
+ int ret;
+
+ reg = fspi_readl(f, f->iobase + FSPI_MCR0);
+ fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
+
+ /* w1c register, wait unit clear */
+ ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
+ FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
+ WARN_ON(ret);
+}
+
+static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = f->iobase;
+ u32 lutval[4] = {};
+ int lutidx = 1, i;
+
+ /* cmd */
+ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode);
+
+ /* addr bytes */
+ if (op->addr.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
+ LUT_PAD(op->addr.buswidth),
+ op->addr.nbytes * 8);
+ lutidx++;
+ }
+
+ /* dummy bytes, if needed */
+ if (op->dummy.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+ /*
+ * Due to FlexSPI controller limitation number of PAD for dummy
+ * buswidth needs to be programmed as equal to data buswidth.
+ */
+ LUT_PAD(op->data.buswidth),
+ op->dummy.nbytes * 8 /
+ op->dummy.buswidth);
+ lutidx++;
+ }
+
+ /* read/write data bytes */
+ if (op->data.nbytes) {
+ lutval[lutidx / 2] |= LUT_DEF(lutidx,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ LUT_NXP_READ : LUT_NXP_WRITE,
+ LUT_PAD(op->data.buswidth),
+ 0);
+ lutidx++;
+ }
+
+ /* stop condition. */
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
+
+ /* unlock LUT */
+ fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
+ fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
+
+ /* fill LUT */
+ for (i = 0; i < ARRAY_SIZE(lutval); i++)
+ fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
+
+ dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
+ op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
+
+ /* lock LUT */
+ fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
+ fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
+}
+
+#if CONFIG_IS_ENABLED(CONFIG_CLK)
+static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
+{
+ int ret;
+
+ ret = clk_enable(&f->clk_en);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&f->clk);
+ if (ret) {
+ clk_disable(&f->clk_en);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
+{
+ clk_disable(&f->clk);
+ clk_disable(&f->clk_en);
+}
+#endif
+
+/*
+ * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
+ * register and start base address of the slave device.
+ *
+ * (Higher address)
+ * -------- <-- FLSHB2CR0
+ * | B2 |
+ * | |
+ * B2 start address --> -------- <-- FLSHB1CR0
+ * | B1 |
+ * | |
+ * B1 start address --> -------- <-- FLSHA2CR0
+ * | A2 |
+ * | |
+ * A2 start address --> -------- <-- FLSHA1CR0
+ * | A1 |
+ * | |
+ * A1 start address --> -------- (Lower address)
+ *
+ *
+ * Start base address defines the starting address range for given CS and
+ * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
+ *
+ * But, different targets are having different combinations of number of CS,
+ * some targets only have single CS or two CS covering controller's full
+ * memory mapped space area.
+ * Thus, implementation is being done as independent of the size and number
+ * of the connected slave device.
+ * Assign controller memory mapped space size as the size to the connected
+ * slave device.
+ * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
+ * chip-select Flash configuration register.
+ *
+ * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
+ * memory mapped size of the controller.
+ * Value for rest of the CS FLSHxxCR0 register would be zero.
+ *
+ */
+static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
+{
+ u64 size_kb;
+
+ /* Reset FLSHxxCR0 registers */
+ fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
+ fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
+ fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
+ fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
+
+ /* Assign controller memory mapped space as size, KBytes, of flash. */
+ size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
+
+ fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
+ 4 * chip_select);
+
+ dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
+}
+
+static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
+{
+ u32 len = op->data.nbytes;
+
+ /* Read out the data directly from the AHB buffer. */
+ memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
+}
+
+static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = f->iobase;
+ int i, ret;
+ u8 *buf = (u8 *)op->data.buf.out;
+
+ /* clear the TX FIFO. */
+ fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
+
+ /*
+ * Default value of water mark level is 8 bytes, hence in single
+ * write request controller can write max 8 bytes of data.
+ */
+
+ for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
+ /* Wait for TXFIFO empty */
+ ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
+ FSPI_INTR_IPTXWE, 0,
+ POLL_TOUT, true);
+ WARN_ON(ret);
+
+ fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
+ fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
+ fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
+ }
+
+ if (i < op->data.nbytes) {
+ u32 data = 0;
+ int j;
+ /* Wait for TXFIFO empty */
+ ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
+ FSPI_INTR_IPTXWE, 0,
+ POLL_TOUT, true);
+ WARN_ON(ret);
+
+ for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
+ memcpy(&data, buf + i + j, 4);
+ fspi_writel(f, data, base + FSPI_TFDR + j);
+ }
+ fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
+ }
+}
+
+static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
+ const struct spi_mem_op *op)
+{
+ void __iomem *base = f->iobase;
+ int i, ret;
+ int len = op->data.nbytes;
+ u8 *buf = (u8 *)op->data.buf.in;
+
+ /*
+ * Default value of water mark level is 8 bytes, hence in single
+ * read request controller can read max 8 bytes of data.
+ */
+ for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
+ /* Wait for RXFIFO available */
+ ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
+ FSPI_INTR_IPRXWA, 0,
+ POLL_TOUT, true);
+ WARN_ON(ret);
+
+ *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
+ *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
+ /* move the FIFO pointer */
+ fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
+ }
+
+ if (i < len) {
+ u32 tmp;
+ int size, j;
+
+ buf = op->data.buf.in + i;
+ /* Wait for RXFIFO available */
+ ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
+ FSPI_INTR_IPRXWA, 0,
+ POLL_TOUT, true);
+ WARN_ON(ret);
+
+ len = op->data.nbytes - i;
+ for (j = 0; j < op->data.nbytes - i; j += 4) {
+ tmp = fspi_readl(f, base + FSPI_RFDR + j);
+ size = min(len, 4);
+ memcpy(buf + j, &tmp, size);
+ len -= size;
+ }
+ }
+
+ /* invalid the RXFIFO */
+ fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
+ /* move the FIFO pointer */
+ fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
+}
+
+static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
+{
+ void __iomem *base = f->iobase;
+ int seqnum = 0;
+ int err = 0;
+ u32 reg;
+
+ reg = fspi_readl(f, base + FSPI_IPRXFCR);
+ /* invalid RXFIFO first */
+ reg &= ~FSPI_IPRXFCR_DMA_EN;
+ reg = reg | FSPI_IPRXFCR_CLR;
+ fspi_writel(f, reg, base + FSPI_IPRXFCR);
+
+ fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
+ /*
+ * Always start the sequence at the same index since we update
+ * the LUT at each exec_op() call. And also specify the DATA
+ * length, since it's has not been specified in the LUT.
+ */
+ fspi_writel(f, op->data.nbytes |
+ (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
+ (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
+ base + FSPI_IPCR1);
+
+ /* Trigger the LUT now. */
+ fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
+
+ /* Wait for the completion. */
+ err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
+ FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
+
+ /* Invoke IP data read, if request is of data read. */
+ if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ nxp_fspi_read_rxfifo(f, op);
+
+ return err;
+}
+
+static int nxp_fspi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct nxp_fspi *f;
+ struct udevice *bus;
+ int err = 0;
+
+ bus = slave->dev->parent;
+ f = dev_get_priv(bus);
+
+ /* Wait for controller being ready. */
+ err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
+ FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
+ WARN_ON(err);
+
+ nxp_fspi_prepare_lut(f, op);
+ /*
+ * If we have large chunks of data, we read them through the AHB bus
+ * by accessing the mapped memory. In all other cases we use
+ * IP commands to access the flash.
+ */
+ if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
+ op->data.dir == SPI_MEM_DATA_IN) {
+ nxp_fspi_read_ahb(f, op);
+ } else {
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+ nxp_fspi_fill_txfifo(f, op);
+
+ err = nxp_fspi_do_op(f, op);
+ }
+
+ /* Invalidate the data in the AHB buffer. */
+ nxp_fspi_invalid(f);
+
+ return err;
+}
+
+static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ struct nxp_fspi *f;
+ struct udevice *bus;
+
+ bus = slave->dev->parent;
+ f = dev_get_priv(bus);
+
+ if (op->data.dir == SPI_MEM_DATA_OUT) {
+ if (op->data.nbytes > f->devtype_data->txfifo)
+ op->data.nbytes = f->devtype_data->txfifo;
+ } else {
+ if (op->data.nbytes > f->devtype_data->ahb_buf_size)
+ op->data.nbytes = f->devtype_data->ahb_buf_size;
+ else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
+ op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
+ }
+
+ return 0;
+}
+
+static int nxp_fspi_default_setup(struct nxp_fspi *f)
+{
+ void __iomem *base = f->iobase;
+ int ret, i;
+ u32 reg;
+
+#if CONFIG_IS_ENABLED(CONFIG_CLK)
+ /* disable and unprepare clock to avoid glitch pass to controller */
+ nxp_fspi_clk_disable_unprep(f);
+
+ /* the default frequency, we will change it later if necessary. */
+ ret = clk_set_rate(&f->clk, 20000000);
+ if (ret)
+ return ret;
+
+ ret = nxp_fspi_clk_prep_enable(f);
+ if (ret)
+ return ret;
+#endif
+
+ /* Reset the module */
+ /* w1c register, wait unit clear */
+ ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
+ FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
+ WARN_ON(ret);
+
+ /* Disable the module */
+ fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
+
+ /* Reset the DLL register to default value */
+ fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
+ fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
+
+ /* enable module */
+ fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
+ base + FSPI_MCR0);
+
+ /*
+ * Disable same device enable bit and configure all slave devices
+ * independently.
+ */
+ reg = fspi_readl(f, f->iobase + FSPI_MCR2);
+ reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
+ fspi_writel(f, reg, base + FSPI_MCR2);
+
+ /* AHB configuration for access buffer 0~7. */
+ for (i = 0; i < 7; i++)
+ fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
+
+ /*
+ * Set ADATSZ with the maximum AHB buffer size to improve the read
+ * performance.
+ */
+ fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
+ FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
+
+ /* prefetch and no start address alignment limitation */
+ fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
+ base + FSPI_AHBCR);
+
+ /* AHB Read - Set lut sequence ID for all CS. */
+ fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
+ fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
+ fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
+ fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
+
+ return 0;
+}
+
+static int nxp_fspi_probe(struct udevice *bus)
+{
+ struct nxp_fspi *f = dev_get_priv(bus);
+
+ f->devtype_data =
+ (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
+ nxp_fspi_default_setup(f);
+
+ return 0;
+}
+
+static int nxp_fspi_claim_bus(struct udevice *dev)
+{
+ struct nxp_fspi *f;
+ struct udevice *bus;
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ bus = dev->parent;
+ f = dev_get_priv(bus);
+
+ nxp_fspi_select_mem(f, slave_plat->cs);
+
+ return 0;
+}
+
+static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
+{
+#if CONFIG_IS_ENABLED(CONFIG_CLK)
+ struct nxp_fspi *f = dev_get_priv(bus);
+ int ret;
+
+ nxp_fspi_clk_disable_unprep(f);
+
+ ret = clk_set_rate(&f->clk, speed);
+ if (ret)
+ return ret;
+
+ ret = nxp_fspi_clk_prep_enable(f);
+ if (ret)
+ return ret;
+#endif
+ return 0;
+}
+
+static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
+{
+ /* Nothing to do */
+ return 0;
+}
+
+static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct nxp_fspi *f = dev_get_priv(bus);
+#if CONFIG_IS_ENABLED(CONFIG_CLK)
+ int ret;
+#endif
+
+ fdt_addr_t iobase;
+ fdt_addr_t iobase_size;
+ fdt_addr_t ahb_addr;
+ fdt_addr_t ahb_size;
+
+ f->dev = bus;
+
+ iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
+ if (iobase == FDT_ADDR_T_NONE) {
+ dev_err(bus, "fspi_base regs missing\n");
+ return -ENODEV;
+ }
+ f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
+
+ ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
+ if (ahb_addr == FDT_ADDR_T_NONE) {
+ dev_err(bus, "fspi_mmap regs missing\n");
+ return -ENODEV;
+ }
+ f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
+ f->memmap_phy_size = ahb_size;
+
+#if CONFIG_IS_ENABLED(CONFIG_CLK)
+ ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
+ if (ret) {
+ dev_err(bus, "failed to get fspi_en clock\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(bus, "fspi", &f->clk);
+ if (ret) {
+ dev_err(bus, "failed to get fspi clock\n");
+ return ret;
+ }
+#endif
+
+ dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
+ .adjust_op_size = nxp_fspi_adjust_op_size,
+ .supports_op = nxp_fspi_supports_op,
+ .exec_op = nxp_fspi_exec_op,
+};
+
+static const struct dm_spi_ops nxp_fspi_ops = {
+ .claim_bus = nxp_fspi_claim_bus,
+ .set_speed = nxp_fspi_set_speed,
+ .set_mode = nxp_fspi_set_mode,
+ .mem_ops = &nxp_fspi_mem_ops,
+};
+
+static const struct udevice_id nxp_fspi_ids[] = {
+ { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
+ { }
+};
+
+U_BOOT_DRIVER(nxp_fspi) = {
+ .name = "nxp_fspi",
+ .id = UCLASS_SPI,
+ .of_match = nxp_fspi_ids,
+ .ops = &nxp_fspi_ops,
+ .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct nxp_fspi),
+ .probe = nxp_fspi_probe,
+};
return 0;
break;
+ case 8:
+ if ((tx && (mode & SPI_TX_OCTAL)) ||
+ (!tx && (mode & SPI_RX_OCTAL)))
+ return 0;
+
+ break;
default:
break;
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
{
+ struct dm_spi_ops *ops;
+ struct spi_cs_info info;
struct udevice *dev;
+ int ret;
+
+ /*
+ * Ask the driver. For the moment we don't have CS info.
+ * When we do we could provide the driver with a helper function
+ * to figure out what chip selects are valid, or just handle the
+ * request.
+ */
+ ops = spi_get_ops(bus);
+ if (ops->cs_info) {
+ ret = ops->cs_info(bus, cs, &info);
+ } else {
+ /*
+ * We could assume there is at least one valid chip select.
+ * The driver didn't care enough to tell us.
+ */
+ ret = 0;
+ }
+
+ if (ret) {
+ printf("Invalid cs %d (err=%d)\n", cs, ret);
+ return ret;
+ }
for (device_find_first_child(bus, &dev); dev;
device_find_next_child(&dev)) {
int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info)
{
struct spi_cs_info local_info;
- struct dm_spi_ops *ops;
int ret;
if (!info)
/* If there is a device attached, return it */
info->dev = NULL;
ret = spi_find_chip_select(bus, cs, &info->dev);
- if (!ret)
- return 0;
-
- /*
- * Otherwise ask the driver. For the moment we don't have CS info.
- * When we do we could provide the driver with a helper function
- * to figure out what chip selects are valid, or just handle the
- * request.
- */
- ops = spi_get_ops(bus);
- if (ops->cs_info)
- return ops->cs_info(bus, cs, info);
-
- /*
- * We could assume there is at least one valid chip select.
- * The driver didn't care enough to tell us.
- */
- return 0;
+ return ret == -ENODEV ? 0 : ret;
}
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
{
struct udevice *bus, *dev;
struct dm_spi_slave_platdata *plat;
+ struct spi_slave *slave;
bool created = false;
int ret;
slave->dev = dev;
}
- plat = dev_get_parent_platdata(dev);
+ slave = dev_get_parent_priv(dev);
- /* get speed and mode from platdata when available */
- if (plat->max_hz) {
- speed = plat->max_hz;
- mode = plat->mode;
+ /*
+ * In case the operation speed is not yet established by
+ * dm_spi_claim_bus() ensure the bus is configured properly.
+ */
+ if (!slave->speed) {
+ ret = spi_claim_bus(slave);
+ if (ret)
+ goto err;
}
- ret = spi_set_speed_mode(bus, speed, mode);
- if (ret)
- goto err;
*busp = bus;
- *devp = dev_get_parent_priv(dev);
+ *devp = slave;
debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp);
return 0;
case 4:
mode |= SPI_TX_QUAD;
break;
+ case 8:
+ mode |= SPI_TX_OCTAL;
+ break;
default:
warn_non_spl("spi-tx-bus-width %d not supported\n", value);
break;
case 4:
mode |= SPI_RX_QUAD;
break;
+ case 8:
+ mode |= SPI_RX_OCTAL;
+ break;
default:
warn_non_spl("spi-rx-bus-width %d not supported\n", value);
break;
#define QSPI_SETUP0_ADDR_SHIFT (8)
#define QSPI_SETUP0_DBITS_SHIFT (10)
+#define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
+
/* ti qspi register set */
struct ti_qspi_regs {
u32 pid;
*((unsigned int *)offset) += len;
}
-static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
- u8 data_nbits, u8 addr_width,
+static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
+ u8 opcode, u8 data_nbits, u8 addr_width,
u8 dummy_bytes)
{
u32 memval = opcode;
memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
- writel(memval, &priv->base->setup0);
+ writel(memval, TI_QSPI_SETUP_REG(priv, cs));
}
static int ti_qspi_set_mode(struct udevice *bus, uint mode)
static int ti_qspi_exec_mem_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
+ struct dm_spi_slave_platdata *slave_plat;
struct ti_qspi_priv *priv;
struct udevice *bus;
+ u32 from = 0;
+ int ret = 0;
bus = slave->dev->parent;
priv = dev_get_priv(bus);
- u32 from = 0;
- int ret = 0;
+ slave_plat = dev_get_parent_platdata(slave->dev);
/* Only optimize read path. */
if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
if (from + op->data.nbytes > priv->mmap_size)
return -ENOTSUPP;
- ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
- op->addr.nbytes, op->dummy.nbytes);
+ ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
+ op->data.buswidth, op->addr.nbytes,
+ op->dummy.nbytes);
ti_qspi_copy_mmap((void *)op->data.buf.in,
(void *)priv->memory_map + from, op->data.nbytes);
writel(0, &priv->base->dc);
writel(0, &priv->base->cmd);
writel(0, &priv->base->data);
- writel(0, &priv->base->setup0);
+ writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
return 0;
}
can be discarded. This option defines the list of properties to
discard.
+config OF_DTB_PROPS_REMOVE
+ bool "Enable removal of device tree properties"
+ depends on OF_CONTROL
+ help
+ Some boards have restricted amount of storage for U-Boot image.
+ If the generated binary doesn't fit into available image storage,
+ the built-in device tree could probably be cut down by removing
+ some not required device tree properties to reduce the image size.
+ Enable this option and define the properties to be removed in the
+ CONFIG_OF_REMOVE_PROPS list. Do not enable this option if you must
+ pass the built-in DTB directly to the kernel!
+
+config OF_REMOVE_PROPS
+ string "List of device tree properties to drop"
+ depends on OF_DTB_PROPS_REMOVE
+ default "interrupt-parent interrupts" if PINCTRL
+ help
+ Some properties are not used by U-Boot and can be discarded.
+ This option defines the list of properties to discard.
+
config SPL_OF_PLATDATA
bool "Generate platform data for use in SPL"
depends on SPL_OF_CONTROL
$(obj)/dt-spl.dtb: $(DTB) $(objtree)/tools/fdtgrep FORCE
$(call if_changed,fdtgrep)
+ifeq ($(CONFIG_OF_DTB_PROPS_REMOVE),y)
+$(obj)/dt.dtb: $(DTB) $(objtree)/tools/fdtgrep FORCE
+ $(call if_changed,fdt_rm_props)
+else
$(obj)/dt.dtb: $(DTB) FORCE
$(call if_changed,shipped)
+endif
targets += dt.dtb dt-spl.dtb
"tzsw raw 0x83f 0x138\0"
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
func(MMC, mmc, 0)
#include <config_distro_bootcmd.h>
"run kernel_args;" \
"bootz ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \
"autoboot=" \
- "if test -e mmc 0 boot.scr; then; " \
+ "if test -e mmc ${mmcbootdev} boot.scr; then; " \
"run boot_script; " \
- "elif test -e mmc 0 Image.itb; then; " \
+ "elif test -e mmc ${mmcbootdev} Image.itb; then; " \
"run boot_fit;" \
- "elif test -e mmc 0 zImage; then; " \
+ "elif test -e mmc ${mmcbootdev} zImage; then; " \
"run boot_zimg;" \
- "elif test -e mmc 0 uImage; then; " \
+ "elif test -e mmc ${mmcbootdev} uImage; then; " \
"run boot_uimg;" \
"fi;\0" \
"console=" CONFIG_DEFAULT_CONSOLE \
*/
#ifndef __LINUX_CLK_PROVIDER_H
#define __LINUX_CLK_PROVIDER_H
+
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
#include <clk-uclass.h>
static inline void clk_dm(ulong id, struct clk *clk)
#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Flowbird
+ * Martin Fuzzey <martin.fuzzey@flowbird.group>
+ */
+
+#ifndef __DA9063_PMIC_H_
+#define __DA9063_PMIC_H_
+
+/* Register definitions below taken from the kernel */
+
+/* Page selection I2C or SPI always in the beginning of any page. */
+/* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
+/* Page 1 : SPI access 0x080 - 0x0FF */
+/* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x100 - 0x17F */
+/* Page 3 : SPI access 0x180 - 0x1FF */
+#define DA9063_REG_PAGE_CON 0x00
+
+/* System Control and Event Registers */
+#define DA9063_REG_STATUS_A 0x01
+#define DA9063_REG_STATUS_B 0x02
+#define DA9063_REG_STATUS_C 0x03
+#define DA9063_REG_STATUS_D 0x04
+#define DA9063_REG_FAULT_LOG 0x05
+#define DA9063_REG_EVENT_A 0x06
+#define DA9063_REG_EVENT_B 0x07
+#define DA9063_REG_EVENT_C 0x08
+#define DA9063_REG_EVENT_D 0x09
+#define DA9063_REG_IRQ_MASK_A 0x0A
+#define DA9063_REG_IRQ_MASK_B 0x0B
+#define DA9063_REG_IRQ_MASK_C 0x0C
+#define DA9063_REG_IRQ_MASK_D 0x0D
+#define DA9063_REG_CONTROL_A 0x0E
+#define DA9063_REG_CONTROL_B 0x0F
+#define DA9063_REG_CONTROL_C 0x10
+#define DA9063_REG_CONTROL_D 0x11
+#define DA9063_REG_CONTROL_E 0x12
+#define DA9063_REG_CONTROL_F 0x13
+#define DA9063_REG_PD_DIS 0x14
+
+/* GPIO Control Registers */
+#define DA9063_REG_GPIO_0_1 0x15
+#define DA9063_REG_GPIO_2_3 0x16
+#define DA9063_REG_GPIO_4_5 0x17
+#define DA9063_REG_GPIO_6_7 0x18
+#define DA9063_REG_GPIO_8_9 0x19
+#define DA9063_REG_GPIO_10_11 0x1A
+#define DA9063_REG_GPIO_12_13 0x1B
+#define DA9063_REG_GPIO_14_15 0x1C
+#define DA9063_REG_GPIO_MODE0_7 0x1D
+#define DA9063_REG_GPIO_MODE8_15 0x1E
+#define DA9063_REG_SWITCH_CONT 0x1F
+
+/* Regulator Control Registers */
+#define DA9063_REG_BCORE2_CONT 0x20
+#define DA9063_REG_BCORE1_CONT 0x21
+#define DA9063_REG_BPRO_CONT 0x22
+#define DA9063_REG_BMEM_CONT 0x23
+#define DA9063_REG_BIO_CONT 0x24
+#define DA9063_REG_BPERI_CONT 0x25
+#define DA9063_REG_LDO1_CONT 0x26
+#define DA9063_REG_LDO2_CONT 0x27
+#define DA9063_REG_LDO3_CONT 0x28
+#define DA9063_REG_LDO4_CONT 0x29
+#define DA9063_REG_LDO5_CONT 0x2A
+#define DA9063_REG_LDO6_CONT 0x2B
+#define DA9063_REG_LDO7_CONT 0x2C
+#define DA9063_REG_LDO8_CONT 0x2D
+#define DA9063_REG_LDO9_CONT 0x2E
+#define DA9063_REG_LDO10_CONT 0x2F
+#define DA9063_REG_LDO11_CONT 0x30
+#define DA9063_REG_SUPPLIES 0x31
+#define DA9063_REG_DVC_1 0x32
+#define DA9063_REG_DVC_2 0x33
+
+/* GP-ADC Control Registers */
+#define DA9063_REG_ADC_MAN 0x34
+#define DA9063_REG_ADC_CONT 0x35
+#define DA9063_REG_VSYS_MON 0x36
+#define DA9063_REG_ADC_RES_L 0x37
+#define DA9063_REG_ADC_RES_H 0x38
+#define DA9063_REG_VSYS_RES 0x39
+#define DA9063_REG_ADCIN1_RES 0x3A
+#define DA9063_REG_ADCIN2_RES 0x3B
+#define DA9063_REG_ADCIN3_RES 0x3C
+#define DA9063_REG_MON_A8_RES 0x3D
+#define DA9063_REG_MON_A9_RES 0x3E
+#define DA9063_REG_MON_A10_RES 0x3F
+
+/* RTC Calendar and Alarm Registers */
+#define DA9063_REG_COUNT_S 0x40
+#define DA9063_REG_COUNT_MI 0x41
+#define DA9063_REG_COUNT_H 0x42
+#define DA9063_REG_COUNT_D 0x43
+#define DA9063_REG_COUNT_MO 0x44
+#define DA9063_REG_COUNT_Y 0x45
+
+#define DA9063_AD_REG_ALARM_MI 0x46
+#define DA9063_AD_REG_ALARM_H 0x47
+#define DA9063_AD_REG_ALARM_D 0x48
+#define DA9063_AD_REG_ALARM_MO 0x49
+#define DA9063_AD_REG_ALARM_Y 0x4A
+#define DA9063_AD_REG_SECOND_A 0x4B
+#define DA9063_AD_REG_SECOND_B 0x4C
+#define DA9063_AD_REG_SECOND_C 0x4D
+#define DA9063_AD_REG_SECOND_D 0x4E
+
+#define DA9063_BB_REG_ALARM_S 0x46
+#define DA9063_BB_REG_ALARM_MI 0x47
+#define DA9063_BB_REG_ALARM_H 0x48
+#define DA9063_BB_REG_ALARM_D 0x49
+#define DA9063_BB_REG_ALARM_MO 0x4A
+#define DA9063_BB_REG_ALARM_Y 0x4B
+#define DA9063_BB_REG_SECOND_A 0x4C
+#define DA9063_BB_REG_SECOND_B 0x4D
+#define DA9063_BB_REG_SECOND_C 0x4E
+#define DA9063_BB_REG_SECOND_D 0x4F
+
+#define DA9063_REG_HOLE_1 {0x50, 0x7F}
+
+/* Sequencer Control Registers */
+#define DA9063_REG_SEQ 0x81
+#define DA9063_REG_SEQ_TIMER 0x82
+#define DA9063_REG_ID_2_1 0x83
+#define DA9063_REG_ID_4_3 0x84
+#define DA9063_REG_ID_6_5 0x85
+#define DA9063_REG_ID_8_7 0x86
+#define DA9063_REG_ID_10_9 0x87
+#define DA9063_REG_ID_12_11 0x88
+#define DA9063_REG_ID_14_13 0x89
+#define DA9063_REG_ID_16_15 0x8A
+#define DA9063_REG_ID_18_17 0x8B
+#define DA9063_REG_ID_20_19 0x8C
+#define DA9063_REG_ID_22_21 0x8D
+#define DA9063_REG_ID_24_23 0x8E
+#define DA9063_REG_ID_26_25 0x8F
+#define DA9063_REG_ID_28_27 0x90
+#define DA9063_REG_ID_30_29 0x91
+#define DA9063_REG_ID_32_31 0x92
+#define DA9063_REG_SEQ_A 0x95
+#define DA9063_REG_SEQ_B 0x96
+#define DA9063_REG_WAIT 0x97
+#define DA9063_REG_EN_32K 0x98
+#define DA9063_REG_RESET 0x99
+
+/* Regulator Setting Registers */
+#define DA9063_REG_BUCK_ILIM_A 0x9A
+#define DA9063_REG_BUCK_ILIM_B 0x9B
+#define DA9063_REG_BUCK_ILIM_C 0x9C
+#define DA9063_REG_BCORE2_CFG 0x9D
+#define DA9063_REG_BCORE1_CFG 0x9E
+#define DA9063_REG_BPRO_CFG 0x9F
+#define DA9063_REG_BIO_CFG 0xA0
+#define DA9063_REG_BMEM_CFG 0xA1
+#define DA9063_REG_BPERI_CFG 0xA2
+#define DA9063_REG_VBCORE2_A 0xA3
+#define DA9063_REG_VBCORE1_A 0xA4
+#define DA9063_REG_VBPRO_A 0xA5
+#define DA9063_REG_VBMEM_A 0xA6
+#define DA9063_REG_VBIO_A 0xA7
+#define DA9063_REG_VBPERI_A 0xA8
+#define DA9063_REG_VLDO1_A 0xA9
+#define DA9063_REG_VLDO2_A 0xAA
+#define DA9063_REG_VLDO3_A 0xAB
+#define DA9063_REG_VLDO4_A 0xAC
+#define DA9063_REG_VLDO5_A 0xAD
+#define DA9063_REG_VLDO6_A 0xAE
+#define DA9063_REG_VLDO7_A 0xAF
+#define DA9063_REG_VLDO8_A 0xB0
+#define DA9063_REG_VLDO9_A 0xB1
+#define DA9063_REG_VLDO10_A 0xB2
+#define DA9063_REG_VLDO11_A 0xB3
+#define DA9063_REG_VBCORE2_B 0xB4
+#define DA9063_REG_VBCORE1_B 0xB5
+#define DA9063_REG_VBPRO_B 0xB6
+#define DA9063_REG_VBMEM_B 0xB7
+#define DA9063_REG_VBIO_B 0xB8
+#define DA9063_REG_VBPERI_B 0xB9
+#define DA9063_REG_VLDO1_B 0xBA
+#define DA9063_REG_VLDO2_B 0xBB
+#define DA9063_REG_VLDO3_B 0xBC
+#define DA9063_REG_VLDO4_B 0xBD
+#define DA9063_REG_VLDO5_B 0xBE
+#define DA9063_REG_VLDO6_B 0xBF
+#define DA9063_REG_VLDO7_B 0xC0
+#define DA9063_REG_VLDO8_B 0xC1
+#define DA9063_REG_VLDO9_B 0xC2
+#define DA9063_REG_VLDO10_B 0xC3
+#define DA9063_REG_VLDO11_B 0xC4
+
+/* Backup Battery Charger Control Register */
+#define DA9063_REG_BBAT_CONT 0xC5
+
+/* GPIO PWM (LED) */
+#define DA9063_REG_GPO11_LED 0xC6
+#define DA9063_REG_GPO14_LED 0xC7
+#define DA9063_REG_GPO15_LED 0xC8
+
+/* GP-ADC Threshold Registers */
+#define DA9063_REG_ADC_CFG 0xC9
+#define DA9063_REG_AUTO1_HIGH 0xCA
+#define DA9063_REG_AUTO1_LOW 0xCB
+#define DA9063_REG_AUTO2_HIGH 0xCC
+#define DA9063_REG_AUTO2_LOW 0xCD
+#define DA9063_REG_AUTO3_HIGH 0xCE
+#define DA9063_REG_AUTO3_LOW 0xCF
+
+#define DA9063_REG_HOLE_2 {0xD0, 0xFF}
+
+/* DA9063 Configuration registers */
+/* OTP */
+#define DA9063_REG_OTP_COUNT 0x101
+#define DA9063_REG_OTP_ADDR 0x102
+#define DA9063_REG_OTP_DATA 0x103
+
+/* Customer Trim and Configuration */
+#define DA9063_REG_T_OFFSET 0x104
+#define DA9063_REG_INTERFACE 0x105
+#define DA9063_REG_CONFIG_A 0x106
+#define DA9063_REG_CONFIG_B 0x107
+#define DA9063_REG_CONFIG_C 0x108
+#define DA9063_REG_CONFIG_D 0x109
+#define DA9063_REG_CONFIG_E 0x10A
+#define DA9063_REG_CONFIG_F 0x10B
+#define DA9063_REG_CONFIG_G 0x10C
+#define DA9063_REG_CONFIG_H 0x10D
+#define DA9063_REG_CONFIG_I 0x10E
+#define DA9063_REG_CONFIG_J 0x10F
+#define DA9063_REG_CONFIG_K 0x110
+#define DA9063_REG_CONFIG_L 0x111
+
+#define DA9063_AD_REG_MON_REG_1 0x112
+#define DA9063_AD_REG_MON_REG_2 0x113
+#define DA9063_AD_REG_MON_REG_3 0x114
+#define DA9063_AD_REG_MON_REG_4 0x115
+#define DA9063_AD_REG_MON_REG_5 0x116
+#define DA9063_AD_REG_MON_REG_6 0x117
+#define DA9063_AD_REG_TRIM_CLDR 0x118
+
+#define DA9063_AD_REG_GP_ID_0 0x119
+#define DA9063_AD_REG_GP_ID_1 0x11A
+#define DA9063_AD_REG_GP_ID_2 0x11B
+#define DA9063_AD_REG_GP_ID_3 0x11C
+#define DA9063_AD_REG_GP_ID_4 0x11D
+#define DA9063_AD_REG_GP_ID_5 0x11E
+#define DA9063_AD_REG_GP_ID_6 0x11F
+#define DA9063_AD_REG_GP_ID_7 0x120
+#define DA9063_AD_REG_GP_ID_8 0x121
+#define DA9063_AD_REG_GP_ID_9 0x122
+#define DA9063_AD_REG_GP_ID_10 0x123
+#define DA9063_AD_REG_GP_ID_11 0x124
+#define DA9063_AD_REG_GP_ID_12 0x125
+#define DA9063_AD_REG_GP_ID_13 0x126
+#define DA9063_AD_REG_GP_ID_14 0x127
+#define DA9063_AD_REG_GP_ID_15 0x128
+#define DA9063_AD_REG_GP_ID_16 0x129
+#define DA9063_AD_REG_GP_ID_17 0x12A
+#define DA9063_AD_REG_GP_ID_18 0x12B
+#define DA9063_AD_REG_GP_ID_19 0x12C
+
+#define DA9063_BB_REG_CONFIG_M 0x112
+#define DA9063_BB_REG_CONFIG_N 0x113
+
+#define DA9063_BB_REG_MON_REG_1 0x114
+#define DA9063_BB_REG_MON_REG_2 0x115
+#define DA9063_BB_REG_MON_REG_3 0x116
+#define DA9063_BB_REG_MON_REG_4 0x117
+#define DA9063_BB_REG_MON_REG_5 0x11E
+#define DA9063_BB_REG_MON_REG_6 0x11F
+#define DA9063_BB_REG_TRIM_CLDR 0x120
+/* General Purpose Registers */
+#define DA9063_BB_REG_GP_ID_0 0x121
+#define DA9063_BB_REG_GP_ID_1 0x122
+#define DA9063_BB_REG_GP_ID_2 0x123
+#define DA9063_BB_REG_GP_ID_3 0x124
+#define DA9063_BB_REG_GP_ID_4 0x125
+#define DA9063_BB_REG_GP_ID_5 0x126
+#define DA9063_BB_REG_GP_ID_6 0x127
+#define DA9063_BB_REG_GP_ID_7 0x128
+#define DA9063_BB_REG_GP_ID_8 0x129
+#define DA9063_BB_REG_GP_ID_9 0x12A
+#define DA9063_BB_REG_GP_ID_10 0x12B
+#define DA9063_BB_REG_GP_ID_11 0x12C
+#define DA9063_BB_REG_GP_ID_12 0x12D
+#define DA9063_BB_REG_GP_ID_13 0x12E
+#define DA9063_BB_REG_GP_ID_14 0x12F
+#define DA9063_BB_REG_GP_ID_15 0x130
+#define DA9063_BB_REG_GP_ID_16 0x131
+#define DA9063_BB_REG_GP_ID_17 0x132
+#define DA9063_BB_REG_GP_ID_18 0x133
+#define DA9063_BB_REG_GP_ID_19 0x134
+
+/* 0x135 - 0x13f are readable, but not documented */
+#define DA9063_REG_HOLE_3 {0x140, 0x17F}
+
+/* Chip ID and variant */
+#define DA9063_REG_CHIP_ID 0x181
+#define DA9063_REG_CHIP_VARIANT 0x182
+#define DA9063_REG_CUSTOMER_ID 0x183
+#define DA9063_REG_CONFIG_ID 0x184
+
+#define DA9063_NUM_OF_REGS (DA9063_REG_CONFIG_ID + 1)
+
+/* Drivers name */
+#define DA9063_LDO_DRIVER "da9063_ldo"
+#define DA9063_BUCK_DRIVER "da9063_buck"
+
+/* Regulator modes */
+enum {
+ DA9063_LDOMODE_SLEEP,
+ DA9063_LDOMODE_NORMAL
+};
+
+enum {
+ DA9063_BUCKMODE_SLEEP,
+ DA9063_BUCKMODE_SYNC,
+ DA9063_BUCKMODE_AUTO,
+};
+
+#endif
#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */
#define SPI_RX_DUAL BIT(12) /* receive with 2 wires */
#define SPI_RX_QUAD BIT(13) /* receive with 4 wires */
+#define SPI_TX_OCTAL BIT(14) /* transmit with 8 wires */
+#define SPI_RX_OCTAL BIT(15) /* receive with 8 wires */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
* @bus: SPI bus to search
* @cs: Chip select to look for
* @devp: Returns the slave device if found
- * @return 0 if found, -ENODEV on error
+ * @return 0 if found, -EINVAL if cs is invalid, -ENODEV if no device attached,
+ * other -ve value on error
*/
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
$(objtree)/tools/fdtgrep -r -O dtb - -o $@ \
-P u-boot,dm-pre-reloc -P u-boot,dm-spl -P u-boot,dm-tpl \
$(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS)))
+
+# fdt_rm_props
+# ---------------------------------------------------------------------------
+# Pass the original device tree file through fdtgrep. This removes various
+# unused properties. The output is typically a smaller device tree file.
+quiet_cmd_fdt_rm_props = FDTGREP $@
+ cmd_fdt_rm_props = cat $< | $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \
+ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_REMOVE_PROPS)))
/* We should be able to add something to another chip select */
ut_assertok(sandbox_sf_bind_emul(state, busnum, cs_b, bus, node,
"name"));
- ut_assertok(spi_get_bus_and_cs(busnum, cs_b, speed, mode,
+ ut_asserteq(-EINVAL, spi_get_bus_and_cs(busnum, cs_b, speed, mode,
"spi_flash_std", "name", &bus, &slave));
- ut_assertok(spi_cs_info(bus, cs_b, &info));
- ut_asserteq_ptr(info.dev, slave->dev);
+ ut_asserteq(-EINVAL, spi_cs_info(bus, cs_b, &info));
+ ut_asserteq_ptr(NULL, info.dev);
/*
* Since we are about to destroy all devices, we must tell sandbox
projects / thirdparty / u-boot.git / commitdiff
