arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

As per S922X datasheet add missing cache information to the Amlogic
S922X SoC.

- Each Cortex-A53 core has 32 KB of instruction cache and
	32 KB of L1 data cache available.
- Each Cortex-A73 core has 64 KB of L1 instruction cache and
	64 KB of L1 data cache available.
- The little (A53) cluster has 256 KB of unified L2 cache available.
- The big (A73) cluster has 1 MB of unified L2 cache available.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-11-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index 86e6ceb31d5e2683644d078f0605091b5847ba7f..f04efa8282561cec866c38a27a2ce15c67498c66 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -49,7 +49,13 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        capacity-dmips-mhz = <592>;
-                       next-level-cache = <&l2>;
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                        #cooling-cells = <2>;
                };
 
@@ -59,7 +65,13 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        capacity-dmips-mhz = <592>;
-                       next-level-cache = <&l2>;
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                        #cooling-cells = <2>;
                };
 
@@ -69,7 +81,13 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        capacity-dmips-mhz = <1024>;
-                       next-level-cache = <&l2>;
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                        #cooling-cells = <2>;
                };
 
@@ -79,7 +97,13 @@
                        reg = <0x0 0x101>;
                        enable-method = "psci";
                        capacity-dmips-mhz = <1024>;
-                       next-level-cache = <&l2>;
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                        #cooling-cells = <2>;
                };
 
@@ -89,7 +113,13 @@
                        reg = <0x0 0x102>;
                        enable-method = "psci";
                        capacity-dmips-mhz = <1024>;
-                       next-level-cache = <&l2>;
+                       d-cache-line-size = <64>;
+                       d-cache-size = <0x10000>;
+                       d-cache-sets = <64>;
+                       i-cache-line-size = <64>;
+                       i-cache-size = <0x10000>;
+                       i-cache-sets = <64>;
+                       next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
                };
 
@@ -99,14 +129,32 @@
                        reg = <0x0 0x103>;
                        enable-method = "psci";
                        capacity-dmips-mhz = <1024>;
-                       next-level-cache = <&l2>;
+                       d-cache-line-size = <64>;
+                       d-cache-size = <0x10000>;
+                       d-cache-sets = <64>;
+                       i-cache-line-size = <64>;
+                       i-cache-size = <0x10000>;
+                       i-cache-sets = <64>;
+                       next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
                };
 
-               l2: l2-cache0 {
+               l2_cache_l: l2-cache-cluster0 {
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;
+                       cache-size = <0x40000>;  /* L2. 256 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
+               };
+
+               l2_cache_b: l2-cache-cluster1 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x100000>; /* L2. 1MB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };
 };