RISC-V: Add RVV constraints.

gcc/ChangeLog:

	* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add
	"vr" constraint.
	(TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint.
	(TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint.
	(vp): Add poly constraint.

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2873d533cb5af0477079e97286f9109946c44b5a..8997284f32e71593d0c43851e2abc533ebb8ea8c 100644 (file)
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -108,3 +108,23 @@
    A constant @code{move_operand}."
   (and (match_operand 0 "move_operand")
        (match_test "CONSTANT_P (op)")))
+
+;; Vector constraints.
+
+(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
+  "A vector register (if available).")
+
+(define_register_constraint "vd" "TARGET_VECTOR ? VD_REGS : NO_REGS"
+  "A vector register except mask register (if available).")
+
+(define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS"
+  "A vector mask register (if available).")
+
+;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov<mode>".
+;; VLENB is a run-time constant which represent the vector register length in bytes.
+;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register length in bytes.
+;; We should only allow the poly equal to BYTES_PER_RISCV_VECTOR.
+(define_constraint "vp"
+  "POLY_INT"
+  (and (match_code "const_poly_int")
+       (match_test "known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR)")))