arm64: dts: s32g: add FlexCAN[0..3] support for s32g2 and s32g3

Add FlexCAN[0..3] for S32G2 and S32G3 SoCs.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index e38f1f87879081e45c5e10915bc0682f7e528f0c..ea1456d361a35b0521d8217b001cdc08d2d359d9 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -334,6 +334,32 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               can0: can@401b4000 {
+                       compatible = "nxp,s32g2-flexcan";
+                       reg = <0x401b4000 0xa000>;
+                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
+               can1: can@401be000 {
+                       compatible = "nxp,s32g2-flexcan";
+                       reg = <0x401be000 0xa000>;
+                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
                uart0: serial@401c8000 {
                        compatible = "nxp,s32g2-linflexuart",
                                     "fsl,s32v234-linflexuart";
@@ -400,6 +426,32 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               can2: can@402a8000 {
+                       compatible = "nxp,s32g2-flexcan";
+                       reg = <0x402a8000 0xa000>;
+                       interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
+               can3: can@402b2000 {
+                       compatible = "nxp,s32g2-flexcan";
+                       reg = <0x402b2000 0xa000>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
                uart2: serial@402bc000 {
                        compatible = "nxp,s32g2-linflexuart",
                                     "fsl,s32v234-linflexuart";

diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index d849edfd26f552d09a4fc1d9f1d1331abebed274..991dbfbfa2033c3759afa88be29ed4f454f0e20e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -391,6 +391,34 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               can0: can@401b4000 {
+                       compatible = "nxp,s32g3-flexcan",
+                                          "nxp,s32g2-flexcan";
+                       reg = <0x401b4000 0xa000>;
+                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
+               can1: can@401be000 {
+                       compatible = "nxp,s32g3-flexcan",
+                                          "nxp,s32g2-flexcan";
+                       reg = <0x401be000 0xa000>;
+                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
                uart0: serial@401c8000 {
                        compatible = "nxp,s32g3-linflexuart",
                                     "fsl,s32v234-linflexuart";
@@ -460,6 +488,34 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               can2: can@402a8000 {
+                       compatible = "nxp,s32g3-flexcan",
+                                          "nxp,s32g2-flexcan";
+                       reg = <0x402a8000 0xa000>;
+                       interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
+               can3: can@402b2000 {
+                       compatible = "nxp,s32g3-flexcan",
+                                          "nxp,s32g2-flexcan";
+                       reg = <0x402b2000 0xa000>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mb-0", "state", "berr", "mb-1";
+                       clocks = <&clks 9>, <&clks 11>;
+                       clock-names = "ipg", "per";
+                       status = "disabled";
+               };
+
                uart2: serial@402bc000 {
                        compatible = "nxp,s32g3-linflexuart",
                                     "fsl,s32v234-linflexuart";

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
index a44eff28073a282c49e054fb52a76c6af9b7fca9..d26af0fb8be7b0a0b904c3125c368ffb1421606b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -8,6 +8,60 @@
  */
 
 &pinctrl {
+       can0_pins: can0-pins {
+               can0-grp0 {
+                       pinmux = <0x2c1>;
+                       output-enable;
+                       slew-rate = <133>;
+               };
+
+               can0-grp1 {
+                       pinmux = <0x2b0>;
+                       input-enable;
+                       slew-rate = <133>;
+               };
+
+               can0-grp2 {
+                       pinmux = <0x2012>;
+               };
+       };
+
+       can2_pins: can2-pins {
+               can2-grp0 {
+                       pinmux = <0x1b2>;
+                       output-enable;
+                       slew-rate = <133>;
+               };
+
+               can2-grp1 {
+                       pinmux = <0x1c0>;
+                       input-enable;
+                       slew-rate = <133>;
+               };
+
+               can2-grp2 {
+                       pinmux = <0x2782>;
+               };
+       };
+
+       can3_pins: can3-pins {
+               can3-grp0 {
+                       pinmux = <0x192>;
+                       output-enable;
+                       slew-rate = <133>;
+               };
+
+               can3-grp1 {
+                       pinmux = <0x1a0>;
+                       input-enable;
+                       slew-rate = <133>;
+               };
+
+               can3-grp2 {
+                       pinmux = <0x2792>;
+               };
+       };
+
        i2c0_pins: i2c0-pins {
                i2c0-grp0 {
                        pinmux = <0x101>, <0x111>;
@@ -121,6 +175,24 @@
        };
 };
 
+&can0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&can0_pins>;
+       status = "okay";
+};
+
+&can2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&can2_pins>;
+       status = "okay";
+};
+
+&can3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&can3_pins>;
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default", "gpio";
        pinctrl-0 = <&i2c0_pins>;

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
index 91fd8dbf2224ca3912a2c47b1a757da3c3c2db2e..ba53ec622f0b5463ddbe0e89ca586c8d166b0865 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -8,6 +8,42 @@
  */
 
 &pinctrl {
+       can0_pins: can0-pins {
+               can0-grp0 {
+                       pinmux = <0x112>;
+                       output-enable;
+                       slew-rate = <133>;
+               };
+
+               can0-grp1 {
+                       pinmux = <0x120>;
+                       input-enable;
+                       slew-rate = <133>;
+               };
+
+               can0-grp2 {
+                       pinmux = <0x2013>;
+               };
+       };
+
+       can1_pins: can1-pins {
+               can1-grp0 {
+                       pinmux = <0x132>;
+                       output-enable;
+                       slew-rate = <133>;
+               };
+
+               can1-grp1 {
+                       pinmux = <0x140>;
+                       input-enable;
+                       slew-rate = <133>;
+               };
+
+               can1-grp2 {
+                       pinmux = <0x2772>;
+               };
+       };
+
        i2c0_pins: i2c0-pins {
                i2c0-grp0 {
                        pinmux = <0x1f2>, <0x201>;
@@ -93,6 +129,18 @@
        };
 };
 
+&can0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&can0_pins>;
+       status = "okay";
+};
+
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&can1_pins>;
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default", "gpio";
        pinctrl-0 = <&i2c0_pins>;