--- /dev/null
+From 0824cca340d450f7cf6774cd577b4f28db3eca04 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 5 Oct 2022 14:14:52 +0100
+Subject: coresight: cti: Fix hang in cti_disable_hw()
+
+From: James Clark <james.clark@arm.com>
+
+[ Upstream commit 665c157e0204176023860b51a46528ba0ba62c33 ]
+
+cti_enable_hw() and cti_disable_hw() are called from an atomic context
+so shouldn't use runtime PM because it can result in a sleep when
+communicating with firmware.
+
+Since commit 3c6656337852 ("Revert "firmware: arm_scmi: Add clock
+management to the SCMI power domain""), this causes a hang on Juno when
+running the Perf Coresight tests or running this command:
+
+ perf record -e cs_etm//u -- ls
+
+This was also missed until the revert commit because pm_runtime_put()
+was called with the wrong device until commit 692c9a499b28 ("coresight:
+cti: Correct the parameter for pm_runtime_put")
+
+With lock and scheduler debugging enabled the following is output:
+
+ coresight cti_sys0: cti_enable_hw -- dev:cti_sys0 parent: 20020000.cti
+ BUG: sleeping function called from invalid context at drivers/base/power/runtime.c:1151
+ in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 330, name: perf-exec
+ preempt_count: 2, expected: 0
+ RCU nest depth: 0, expected: 0
+ INFO: lockdep is turned off.
+ irq event stamp: 0
+ hardirqs last enabled at (0): [<0000000000000000>] 0x0
+ hardirqs last disabled at (0): [<ffff80000822b394>] copy_process+0xa0c/0x1948
+ softirqs last enabled at (0): [<ffff80000822b394>] copy_process+0xa0c/0x1948
+ softirqs last disabled at (0): [<0000000000000000>] 0x0
+ CPU: 3 PID: 330 Comm: perf-exec Not tainted 6.0.0-00053-g042116d99298 #7
+ Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Sep 13 2022
+ Call trace:
+ dump_backtrace+0x134/0x140
+ show_stack+0x20/0x58
+ dump_stack_lvl+0x8c/0xb8
+ dump_stack+0x18/0x34
+ __might_resched+0x180/0x228
+ __might_sleep+0x50/0x88
+ __pm_runtime_resume+0xac/0xb0
+ cti_enable+0x44/0x120
+ coresight_control_assoc_ectdev+0xc0/0x150
+ coresight_enable_path+0xb4/0x288
+ etm_event_start+0x138/0x170
+ etm_event_add+0x48/0x70
+ event_sched_in.isra.122+0xb4/0x280
+ merge_sched_in+0x1fc/0x3d0
+ visit_groups_merge.constprop.137+0x16c/0x4b0
+ ctx_sched_in+0x114/0x1f0
+ perf_event_sched_in+0x60/0x90
+ ctx_resched+0x68/0xb0
+ perf_event_exec+0x138/0x508
+ begin_new_exec+0x52c/0xd40
+ load_elf_binary+0x6b8/0x17d0
+ bprm_execve+0x360/0x7f8
+ do_execveat_common.isra.47+0x218/0x238
+ __arm64_sys_execve+0x48/0x60
+ invoke_syscall+0x4c/0x110
+ el0_svc_common.constprop.4+0xfc/0x120
+ do_el0_svc+0x34/0xc0
+ el0_svc+0x40/0x98
+ el0t_64_sync_handler+0x98/0xc0
+ el0t_64_sync+0x170/0x174
+
+Fix the issue by removing the runtime PM calls completely. They are not
+needed here because it must have already been done when building the
+path for a trace.
+
+Fixes: 835d722ba10a ("coresight: cti: Initial CoreSight CTI Driver")
+Reported-by: Aishwarya TCV <Aishwarya.TCV@arm.com>
+Reported-by: Cristian Marussi <Cristian.Marussi@arm.com>
+Suggested-by: Suzuki Poulose <Suzuki.Poulose@arm.com>
+Signed-off-by: James Clark <james.clark@arm.com>
+Reviewed-by: Mike Leach <mike.leach@linaro.org>
+Tested-by: Mike Leach <mike.leach@linaro.org>
+Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
+Link: https://lore.kernel.org/r/20221005131452.1506328-1-james.clark@arm.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hwtracing/coresight/coresight-cti-core.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
+index 0276700c246d..7e264a267240 100644
+--- a/drivers/hwtracing/coresight/coresight-cti-core.c
++++ b/drivers/hwtracing/coresight/coresight-cti-core.c
+@@ -94,7 +94,6 @@ static int cti_enable_hw(struct cti_drvdata *drvdata)
+ unsigned long flags;
+ int rc = 0;
+
+- pm_runtime_get_sync(dev->parent);
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+
+ /* no need to do anything if enabled or unpowered*/
+@@ -119,7 +118,6 @@ static int cti_enable_hw(struct cti_drvdata *drvdata)
+ /* cannot enable due to error */
+ cti_err_not_enabled:
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+- pm_runtime_put(dev->parent);
+ return rc;
+ }
+
+@@ -174,7 +172,6 @@ static int cti_disable_hw(struct cti_drvdata *drvdata)
+ coresight_disclaim_device_unlocked(drvdata->base);
+ CS_LOCK(drvdata->base);
+ spin_unlock(&drvdata->spinlock);
+- pm_runtime_put(dev->parent);
+ return 0;
+
+ /* not disabled this call */
+--
+2.35.1
+
--- /dev/null
+From ae7cf98897d643d135ef6ee23a28f360b912b8cf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Sep 2022 10:53:18 +0200
+Subject: drm/msm/hdmi: fix IRQ lifetime
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 152d394842bb564148e68b92486a87db0bf54859 ]
+
+Device-managed resources allocated post component bind must be tied to
+the lifetime of the aggregate DRM device or they will not necessarily be
+released when binding of the aggregate device is deferred.
+
+This is specifically true for the HDMI IRQ, which will otherwise remain
+requested so that the next bind attempt fails when requesting the IRQ a
+second time.
+
+Fix this by tying the device-managed lifetime of the HDMI IRQ to the DRM
+device so that it is released when bind fails.
+
+Fixes: 067fef372c73 ("drm/msm/hdmi: refactor bind/init")
+Cc: stable@vger.kernel.org # 3.19
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
+Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/502666/
+Link: https://lore.kernel.org/r/20220913085320.8577-9-johan+linaro@kernel.org
+Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
+index 28823fd94f9f..bd65dc9b8892 100644
+--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
++++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
+@@ -326,7 +326,7 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
+ goto fail;
+ }
+
+- ret = devm_request_irq(&pdev->dev, hdmi->irq,
++ ret = devm_request_irq(dev->dev, hdmi->irq,
+ msm_hdmi_irq, IRQF_TRIGGER_HIGH,
+ "hdmi_isr", hdmi);
+ if (ret < 0) {
+--
+2.35.1
+
--- /dev/null
+From cec164c9df134634cc964c924f71d6d81358b4be Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Feb 2022 17:47:33 +0000
+Subject: drm/msm/hdmi: Remove spurious IRQF_ONESHOT flag
+
+From: Daniel Thompson <daniel.thompson@linaro.org>
+
+[ Upstream commit 088604d37e23e9ec01a501d0e3630bc4f02027a0 ]
+
+Quoting the header comments, IRQF_ONESHOT is "Used by threaded interrupts
+which need to keep the irq line disabled until the threaded handler has
+been run.". When applied to an interrupt that doesn't request a threaded
+irq then IRQF_ONESHOT has a lesser known (undocumented?) side effect,
+which it to disable the forced threading of irqs. For "normal" kernels
+if there is no thread_fn then IRQF_ONESHOT is a nop.
+
+In this case disabling forced threading is not appropriate because the
+driver calls wake_up_all() (via msm_hdmi_i2c_irq) and also directly uses
+the regular spinlock API for locking (in msm_hdmi_hdcp_irq() ). Neither
+of these APIs can be called from no-thread interrupt handlers on
+PREEMPT_RT systems.
+
+Fix this by removing IRQF_ONESHOT.
+
+Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220201174734.196718-3-daniel.thompson@linaro.org
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Stable-dep-of: 152d394842bb ("drm/msm/hdmi: fix IRQ lifetime")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
+index 47796e12b432..28823fd94f9f 100644
+--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
++++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
+@@ -327,7 +327,7 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
+ }
+
+ ret = devm_request_irq(&pdev->dev, hdmi->irq,
+- msm_hdmi_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
++ msm_hdmi_irq, IRQF_TRIGGER_HIGH,
+ "hdmi_isr", hdmi);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dev->dev, "failed to request IRQ%u: %d\n",
+--
+2.35.1
+
--- /dev/null
+From 53392bcacdf699568e453926bd3499bc0d7c44cf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 14 Oct 2022 20:01:17 +0200
+Subject: fbdev: stifb: Fall back to cfb_fillrect() on 32-bit HCRX cards
+
+From: Helge Deller <deller@gmx.de>
+
+[ Upstream commit 776d875fd4cbb3884860ea7f63c3958f02b0c80e ]
+
+When the text console is scrolling text upwards it calls the fillrect()
+function to empty the new line. The current implementation doesn't seem
+to work correctly on HCRX cards in 32-bit mode and leave garbage in that
+line instead. Fix it by falling back to standard cfb_fillrect() in that
+case.
+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/video/fbdev/stifb.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/video/fbdev/stifb.c b/drivers/video/fbdev/stifb.c
+index 7753e586e65a..3feb6e40d56d 100644
+--- a/drivers/video/fbdev/stifb.c
++++ b/drivers/video/fbdev/stifb.c
+@@ -1055,7 +1055,8 @@ stifb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
+ {
+ struct stifb_info *fb = container_of(info, struct stifb_info, info);
+
+- if (rect->rop != ROP_COPY)
++ if (rect->rop != ROP_COPY ||
++ (fb->id == S9000_ID_HCRX && fb->info.var.bits_per_pixel == 32))
+ return cfb_fillrect(info, rect);
+
+ SETUP_HW(fb);
+--
+2.35.1
+
--- /dev/null
+From eedea481f50596e456f0bdba368bbc9d8a1b9c37 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 13 Oct 2022 11:32:48 +0200
+Subject: mmc: sdhci-esdhc-imx: Propagate ESDHC_FLAG_HS400* only on 8bit bus
+
+From: Sascha Hauer <s.hauer@pengutronix.de>
+
+[ Upstream commit 1ed5c3b22fc78735c539e4767832aea58db6761c ]
+
+The core issues the warning "drop HS400 support since no 8-bit bus" when
+one of the ESDHC_FLAG_HS400* flags is set on a non 8bit capable host. To
+avoid this warning set these flags only on hosts that actually can do
+8bit, i.e. have bus-width = <8> set in the device tree.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
+Fixes: 029e2476f9e6 ("mmc: sdhci-esdhc-imx: add HS400_ES support for i.MX8QXP")
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20221013093248.2220802-1-s.hauer@pengutronix.de
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci-esdhc-imx.c | 17 ++++++++---------
+ 1 file changed, 8 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
+index a4bd85b200a3..be4e5cdda1fa 100644
+--- a/drivers/mmc/host/sdhci-esdhc-imx.c
++++ b/drivers/mmc/host/sdhci-esdhc-imx.c
+@@ -1692,6 +1692,10 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
+ host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
+ }
+
++ err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
++ if (err)
++ goto disable_ahb_clk;
++
+ if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
+ sdhci_esdhc_ops.platform_execute_tuning =
+ esdhc_executing_tuning;
+@@ -1699,13 +1703,15 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
+ if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
+ host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
+- if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
++ if (host->caps & MMC_CAP_8_BIT_DATA &&
++ imx_data->socdata->flags & ESDHC_FLAG_HS400)
+ host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
+
+ if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
+ host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
+
+- if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
++ if (host->caps & MMC_CAP_8_BIT_DATA &&
++ imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
+ host->mmc->caps2 |= MMC_CAP2_HS400_ES;
+ host->mmc_host_ops.hs400_enhanced_strobe =
+ esdhc_hs400_enhanced_strobe;
+@@ -1727,13 +1733,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
+ goto disable_ahb_clk;
+ }
+
+- if (of_id)
+- err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
+- else
+- err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
+- if (err)
+- goto disable_ahb_clk;
+-
+ sdhci_esdhc_imx_hwinit(host);
+
+ err = sdhci_add_host(host);
+--
+2.35.1
+
--- /dev/null
+From c9c995b9195a6450ea8e6c468f96d16a374724bf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Mar 2021 18:14:32 +0800
+Subject: mmc: sdhci-pci: Avoid comma separated statements
+
+From: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
+
+[ Upstream commit ba8734dfbe87b9dd68c9d525c0a3a52e8da42167 ]
+
+Use semicolons.
+
+Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/20210311181432.6385cd2b@xhacker.debian
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Stable-dep-of: 9dc0033e4658 ("mmc: sdhci-pci-core: Disable ES for ASUS BIOS on Jasper Lake")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci-pci-core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
+index a78b060ce847..422ea3a1817a 100644
+--- a/drivers/mmc/host/sdhci-pci-core.c
++++ b/drivers/mmc/host/sdhci-pci-core.c
+@@ -975,7 +975,7 @@ static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
+ slot->host->mmc->caps2 |= MMC_CAP2_CQE;
+
+ if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
+- slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
++ slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES;
+ slot->host->mmc_host_ops.hs400_enhanced_strobe =
+ intel_hs400_enhanced_strobe;
+ slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
+--
+2.35.1
+
--- /dev/null
+From 5a3ccf3be4149d6daa771d2a1743c952c0159158 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 13 Oct 2022 17:00:17 -0400
+Subject: mmc: sdhci-pci-core: Disable ES for ASUS BIOS on Jasper Lake
+
+From: Patrick Thompson <ptf@google.com>
+
+[ Upstream commit 9dc0033e4658d6f9d9952c3c0c6be3ec25bc2985 ]
+
+Enhanced Strobe (ES) does not work correctly on the ASUS 1100 series of
+devices. Jasper Lake eMMCs (pci_id 8086:4dc4) are supposed to support
+ES. There are also two system families under the series, thus this is
+being scoped to the ASUS BIOS.
+
+The failing ES prevents the installer from writing to disk. Falling back
+to HS400 without ES fixes the issue.
+
+Signed-off-by: Patrick Thompson <ptf@google.com>
+Fixes: 315e3bd7ac19 ("mmc: sdhci-pci: Add support for Intel JSL")
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20221013210017.3751025-1-ptf@google.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci-pci-core.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
+index 422ea3a1817a..7eb9a62ee074 100644
+--- a/drivers/mmc/host/sdhci-pci-core.c
++++ b/drivers/mmc/host/sdhci-pci-core.c
+@@ -967,6 +967,12 @@ static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
+ dmi_match(DMI_SYS_VENDOR, "IRBIS"));
+ }
+
++static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot)
++{
++ return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC &&
++ dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC.");
++}
++
+ static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
+ {
+ int ret = byt_emmc_probe_slot(slot);
+@@ -975,9 +981,11 @@ static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
+ slot->host->mmc->caps2 |= MMC_CAP2_CQE;
+
+ if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
+- slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES;
+- slot->host->mmc_host_ops.hs400_enhanced_strobe =
+- intel_hs400_enhanced_strobe;
++ if (!jsl_broken_hs400es(slot)) {
++ slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES;
++ slot->host->mmc_host_ops.hs400_enhanced_strobe =
++ intel_hs400_enhanced_strobe;
++ }
+ slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From d26ffcc6c1bb8e181fa00a8fc0009d2fbf3f837c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 18 Oct 2022 11:11:29 +0200
+Subject: mtd: parsers: bcm47xxpart: Fix halfblock reads
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Linus Walleij <linus.walleij@linaro.org>
+
+[ Upstream commit 05e258c6ec669d6d18c494ea03d35962d6f5b545 ]
+
+There is some code in the parser that tries to read 0x8000
+bytes into a block to "read in the middle" of the block. Well
+that only works if the block is also 0x10000 bytes all the time,
+else we get these parse errors as we reach the end of the flash:
+
+spi-nor spi0.0: mx25l1606e (2048 Kbytes)
+mtd_read error while parsing (offset: 0x200000): -22
+mtd_read error while parsing (offset: 0x201000): -22
+(...)
+
+Fix the code to do what I think was intended.
+
+Cc: stable@vger.kernel.org
+Fixes: f0501e81fbaa ("mtd: bcm47xxpart: alternative MAGIC for board_data partition")
+Cc: Rafał Miłecki <zajec5@gmail.com>
+Cc: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20221018091129.280026-1-linus.walleij@linaro.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/parsers/bcm47xxpart.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mtd/parsers/bcm47xxpart.c b/drivers/mtd/parsers/bcm47xxpart.c
+index 50fcf4c2174b..13daf9bffd08 100644
+--- a/drivers/mtd/parsers/bcm47xxpart.c
++++ b/drivers/mtd/parsers/bcm47xxpart.c
+@@ -233,11 +233,11 @@ static int bcm47xxpart_parse(struct mtd_info *master,
+ }
+
+ /* Read middle of the block */
+- err = mtd_read(master, offset + 0x8000, 0x4, &bytes_read,
++ err = mtd_read(master, offset + (blocksize / 2), 0x4, &bytes_read,
+ (uint8_t *)buf);
+ if (err && !mtd_is_bitflip(err)) {
+ pr_err("mtd_read error while parsing (offset: 0x%X): %d\n",
+- offset + 0x8000, err);
++ offset + (blocksize / 2), err);
+ continue;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 5fcac175aa8e8dae577d5b09492d6a7c996084d3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 17 Mar 2022 12:43:16 +0100
+Subject: mtd: parsers: bcm47xxpart: print correct offset on read error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Rafał Miłecki <rafal@milecki.pl>
+
+[ Upstream commit 4c38eded807043f40f4dc49da6df097f9dcac393 ]
+
+mtd_read() gets called with offset + 0x8000 as argument so use the same
+value in pr_err().
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220317114316.29827-1-zajec5@gmail.com
+Stable-dep-of: 05e258c6ec66 ("mtd: parsers: bcm47xxpart: Fix halfblock reads")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mtd/parsers/bcm47xxpart.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/parsers/bcm47xxpart.c b/drivers/mtd/parsers/bcm47xxpart.c
+index 6012a10f10c8..50fcf4c2174b 100644
+--- a/drivers/mtd/parsers/bcm47xxpart.c
++++ b/drivers/mtd/parsers/bcm47xxpart.c
+@@ -237,7 +237,7 @@ static int bcm47xxpart_parse(struct mtd_info *master,
+ (uint8_t *)buf);
+ if (err && !mtd_is_bitflip(err)) {
+ pr_err("mtd_read error while parsing (offset: 0x%X): %d\n",
+- offset, err);
++ offset + 0x8000, err);
+ continue;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 472492b314cf1cd12c994679dc6c3245f5c54bb5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 16 Sep 2022 15:01:36 +0200
+Subject: s390/boot: add secure boot trailer
+
+From: Peter Oberparleiter <oberpar@linux.ibm.com>
+
+[ Upstream commit aa127a069ef312aca02b730d5137e1778d0c3ba7 ]
+
+This patch enhances the kernel image adding a trailer as required for
+secure boot by future firmware versions.
+
+Cc: <stable@vger.kernel.org> # 5.2+
+Signed-off-by: Peter Oberparleiter <oberpar@linux.ibm.com>
+Reviewed-by: Sven Schnelle <svens@linux.ibm.com>
+Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/s390/boot/compressed/vmlinux.lds.S | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/arch/s390/boot/compressed/vmlinux.lds.S b/arch/s390/boot/compressed/vmlinux.lds.S
+index 9427e2cd0c15..11bf3919610e 100644
+--- a/arch/s390/boot/compressed/vmlinux.lds.S
++++ b/arch/s390/boot/compressed/vmlinux.lds.S
+@@ -91,8 +91,17 @@ SECTIONS
+ _compressed_start = .;
+ *(.vmlinux.bin.compressed)
+ _compressed_end = .;
+- FILL(0xff);
+- . = ALIGN(4096);
++ }
++
++#define SB_TRAILER_SIZE 32
++ /* Trailer needed for Secure Boot */
++ . += SB_TRAILER_SIZE; /* make sure .sb.trailer does not overwrite the previous section */
++ . = ALIGN(4096) - SB_TRAILER_SIZE;
++ .sb.trailer : {
++ QUAD(0)
++ QUAD(0)
++ QUAD(0)
++ QUAD(0x000000207a49504c)
+ }
+ _end = .;
+
+--
+2.35.1
+
net-mdio-fix-undefined-behavior-in-bit-shift-for-__m.patch
net-neigh-fix-null-ptr-deref-in-neigh_table_clear.patch
ipv6-fix-warning-in-ip6_route_net_exit_late.patch
+drm-msm-hdmi-remove-spurious-irqf_oneshot-flag.patch
+drm-msm-hdmi-fix-irq-lifetime.patch
+mmc-sdhci-esdhc-imx-propagate-esdhc_flag_hs400-only-.patch
+mmc-sdhci-pci-avoid-comma-separated-statements.patch
+mmc-sdhci-pci-core-disable-es-for-asus-bios-on-jaspe.patch
+video-fbdev-stifb-implement-the-stifb_fillrect-funct.patch
+fbdev-stifb-fall-back-to-cfb_fillrect-on-32-bit-hcrx.patch
+mtd-parsers-bcm47xxpart-print-correct-offset-on-read.patch
+mtd-parsers-bcm47xxpart-fix-halfblock-reads.patch
+coresight-cti-fix-hang-in-cti_disable_hw.patch
+xhci-pci-set-runtime-pm-as-default-policy-on-all-xhc.patch
+s390-boot-add-secure-boot-trailer.patch
--- /dev/null
+From 3bd29bc94940f477dcb2ed2bf023b5e141bb6768 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 13 Jan 2022 16:35:53 +0100
+Subject: video/fbdev/stifb: Implement the stifb_fillrect() function
+
+From: Helge Deller <deller@gmx.de>
+
+[ Upstream commit 9c379c65241707e44072139d782bc2dfec9b4ab3 ]
+
+The stifb driver (for Artist/HCRX graphics on PA-RISC) was missing
+the fillrect function.
+Tested on a 715/64 PA-RISC machine and in qemu.
+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Stable-dep-of: 776d875fd4cb ("fbdev: stifb: Fall back to cfb_fillrect() on 32-bit HCRX cards")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/video/fbdev/stifb.c | 45 +++++++++++++++++++++++++++++++++++--
+ 1 file changed, 43 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/fbdev/stifb.c b/drivers/video/fbdev/stifb.c
+index b0470f4f595e..7753e586e65a 100644
+--- a/drivers/video/fbdev/stifb.c
++++ b/drivers/video/fbdev/stifb.c
+@@ -1041,6 +1041,47 @@ stifb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
+ SETUP_FB(fb);
+ }
+
++#define ARTIST_VRAM_SIZE 0x000804
++#define ARTIST_VRAM_SRC 0x000808
++#define ARTIST_VRAM_SIZE_TRIGGER_WINFILL 0x000a04
++#define ARTIST_VRAM_DEST_TRIGGER_BLOCKMOVE 0x000b00
++#define ARTIST_SRC_BM_ACCESS 0x018008
++#define ARTIST_FGCOLOR 0x018010
++#define ARTIST_BGCOLOR 0x018014
++#define ARTIST_BITMAP_OP 0x01801c
++
++static void
++stifb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
++{
++ struct stifb_info *fb = container_of(info, struct stifb_info, info);
++
++ if (rect->rop != ROP_COPY)
++ return cfb_fillrect(info, rect);
++
++ SETUP_HW(fb);
++
++ if (fb->info.var.bits_per_pixel == 32) {
++ WRITE_WORD(0xBBA0A000, fb, REG_10);
++
++ NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff);
++ } else {
++ WRITE_WORD(fb->id == S9000_ID_HCRX ? 0x13a02000 : 0x13a01000, fb, REG_10);
++
++ NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xff);
++ }
++
++ WRITE_WORD(0x03000300, fb, ARTIST_BITMAP_OP);
++ WRITE_WORD(0x2ea01000, fb, ARTIST_SRC_BM_ACCESS);
++ NGLE_QUICK_SET_DST_BM_ACCESS(fb, 0x2ea01000);
++ NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, rect->color);
++ WRITE_WORD(0, fb, ARTIST_BGCOLOR);
++
++ NGLE_SET_DSTXY(fb, (rect->dx << 16) | (rect->dy));
++ SET_LENXY_START_RECFILL(fb, (rect->width << 16) | (rect->height));
++
++ SETUP_FB(fb);
++}
++
+ static void __init
+ stifb_init_display(struct stifb_info *fb)
+ {
+@@ -1105,7 +1146,7 @@ static const struct fb_ops stifb_ops = {
+ .owner = THIS_MODULE,
+ .fb_setcolreg = stifb_setcolreg,
+ .fb_blank = stifb_blank,
+- .fb_fillrect = cfb_fillrect,
++ .fb_fillrect = stifb_fillrect,
+ .fb_copyarea = stifb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ };
+@@ -1297,7 +1338,7 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref)
+ goto out_err0;
+ }
+ info->screen_size = fix->smem_len;
+- info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA;
++ info->flags = FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
+ info->pseudo_palette = &fb->pseudo_palette;
+
+ /* This has to be done !!! */
+--
+2.35.1
+
--- /dev/null
+From d952847aaa72588fc21a921a58a344682542d954 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 24 Oct 2022 17:27:19 +0300
+Subject: xhci-pci: Set runtime PM as default policy on all xHC 1.2 or later
+ devices
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[ Upstream commit a611bf473d1f77b70f7188b5577542cb39b4701b ]
+
+For optimal power consumption of USB4 routers the XHCI PCIe endpoint
+used for tunneling must be in D3. Historically this is accomplished
+by a long list of PCIe IDs that correspond to these endpoints because
+the xhci_hcd driver will not default to allowing runtime PM for all
+devices.
+
+As both AMD and Intel have released new products with new XHCI controllers
+this list continues to grow. In reviewing the XHCI specification v1.2 on
+page 607 there is already a requirement that the PCI power management
+states D3hot and D3cold must be supported.
+
+In the quirk list, use this to indicate that runtime PM should be allowed
+on XHCI controllers. The following controllers are known to be xHC 1.2 and
+dropped explicitly:
+* AMD Yellow Carp
+* Intel Alder Lake
+* Intel Meteor Lake
+* Intel Raptor Lake
+
+[keep PCI ID for Alder Lake PCH for recently added quirk -Mathias]
+
+Cc: stable@vger.kernel.org
+Suggested-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Link: https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Link: https://lore.kernel.org/r/20221024142720.4122053-4-mathias.nyman@intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/host/xhci-pci.c | 32 ++++----------------------------
+ 1 file changed, 4 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
+index 64d5a593682b..0ee11a937011 100644
+--- a/drivers/usb/host/xhci-pci.c
++++ b/drivers/usb/host/xhci-pci.c
+@@ -58,24 +58,12 @@
+ #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
+ #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
+ #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
+-#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
+-#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI 0x464e
+-#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
+-#define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI 0xa71e
+-#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI 0x7ec0
++#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
+
+ #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
+ #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
+ #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
+ #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c
+-#define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f
+
+ #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
+ #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
+@@ -268,12 +256,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
+ pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
+ pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
+ pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
+- pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
+- pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
+- pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI ||
+- pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
+- pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI ||
+- pdev->device == PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI))
++ pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
+ xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
+
+ if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
+@@ -342,15 +325,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
+ pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
+ xhci->quirks |= XHCI_NO_SOFT_RETRY;
+
+- if (pdev->vendor == PCI_VENDOR_ID_AMD &&
+- (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
+- pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
+- pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
+- pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
+- pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
+- pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
+- pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
+- pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
++ /* xHC spec requires PCI devices to support D3hot and D3cold */
++ if (xhci->hci_version >= 0x120)
+ xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
+
+ if (xhci->quirks & XHCI_RESET_ON_RESUME)
+--
+2.35.1
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
