]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file
authorSiddharth Vadapalli <s-vadapalli@ti.com>
Wed, 15 Oct 2025 11:13:33 +0000 (16:43 +0530)
committerVignesh Raghavendra <vigneshr@ti.com>
Thu, 6 Nov 2025 06:18:29 +0000 (11:48 +0530)
Following the existing convention of disabling nodes in the SoC file and
enabling only the required ones in the board file, disable "cpsw3g" node
in the SoC file "k3-am62-main.dtsi" and enable it in the board (or board
include) files:
a) k3-am62-lp-sk.dts
b) k3-am62-phycore-som.dtsi
c) k3-am625-beagleplay.dts
d) k3-am625-sk-common.dtsi

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://patch.msgid.link/20251015111344.3639415-2-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi

index cb63db337b2bc4c83b48dde693b95dd9fd93cd26..3e2d8f669535132a7dee8705c294abb5f6f59d9f 100644 (file)
        vqmmc-supply = <&vddshv_sdio>;
 };
 
+&cpsw3g {
+       status = "okay";
+};
+
 &cpsw_port2 {
        status = "disabled";
 };
index a290a674767bee194c3d5f29583b79b214c2d677..c5ee263d34a62ef46b416ffa45bc2ec5c28d010a 100644 (file)
                dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
                            "tx7", "rx";
 
+               status = "disabled";
+
                ethernet-ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
index 985963774c002286aed02555ebe9fb3209f5e082..878d267bc663bc380283f3fd8e9060c460899505 100644 (file)
 &cpsw3g {
        pinctrl-names = "default";
        pinctrl-0 = <&main_rgmii1_pins_default>;
+       status = "okay";
 };
 
 &cpsw_port1 {
index 7b9ae467e95aeac4970405da50f5ce102e6e6755..c468b9c5fc09ad336b0fc9dd0f200f7699036e1d 100644 (file)
                    <&gbe_pmx_obsclk>;
        assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;
        assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;
+       status = "okay";
 };
 
 &cpsw_port1 {
index 7eb9066bff82c8ed018b5f335590a56009a9b1fd..9c8362682645325608317cc0e3ad9c99e85be1c4 100644 (file)
 &cpsw3g {
        pinctrl-names = "default";
        pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
+       status = "okay";
 };
 
 &cpsw_port2 {