drm/amdgpu: update RLC_PG_DELAY_3 Value to 200us for yellow carp

For yellow carp, the desired CGPG hysteresis value is 0x4E20.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 90a834dc40084e36f41cf8a03723552420f49a83..b53b36f5ae92e6798fe320bd0867e29a3c6a834a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8316,11 +8316,8 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
        if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
                switch (adev->ip_versions[GC_HWIP][0]) {
                case IP_VERSION(10, 3, 1):
-                       data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
-                       WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
-                       break;
                case IP_VERSION(10, 3, 3):
-                       data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+                       data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
                        WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
                        break;
                default: