Fixes for 5.10

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-5.10/alsa-emu10k1-roll-up-loops-in-dsp-setup-code-for-aud.patch b/queue-5.10/alsa-emu10k1-roll-up-loops-in-dsp-setup-code-for-aud.patch
new file mode 100644 (file)
index 0000000..19f530f
--- /dev/null
+++ b/queue-5.10/alsa-emu10k1-roll-up-loops-in-dsp-setup-code-for-aud.patch
@@ -0,0 +1,153 @@
+From be2ef4a8cd77ed900153d7ac0e46f8aa7de278fc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 10 May 2023 19:39:05 +0200
+Subject: ALSA: emu10k1: roll up loops in DSP setup code for Audigy
+
+From: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
+
+[ Upstream commit 8cabf83c7aa54530e699be56249fb44f9505c4f3 ]
+
+There is no apparent reason for the massive code duplication.
+
+Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
+Link: https://lore.kernel.org/r/20230510173917.3073107-3-oswald.buddenhagen@gmx.de
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/pci/emu10k1/emufx.c | 112 +++-----------------------------------
+ 1 file changed, 9 insertions(+), 103 deletions(-)
+
+diff --git a/sound/pci/emu10k1/emufx.c b/sound/pci/emu10k1/emufx.c
+index 4e76ed0e91d5d..e17b93b25d2ff 100644
+--- a/sound/pci/emu10k1/emufx.c
++++ b/sound/pci/emu10k1/emufx.c
+@@ -1560,14 +1560,8 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
+       gpr += 2;
+ 
+       /* Master volume (will be renamed later) */
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
+-      A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
++      for (z = 0; z < 8; z++)
++              A_OP(icode, &ptr, iMAC0, A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS));
+       snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
+       gpr += 2;
+ 
+@@ -1651,102 +1645,14 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
+                       dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
+                              gpr, tmp);
+                       */
+-                      /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
+-                      /* A_P16VIN(0) is delayed by one sample,
+-                       * so all other A_P16VIN channels will need to also be delayed
+-                       */
+-                      /* Left ADC in. 1 of 2 */
+                       snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
+-                      /* Right ADC in 1 of 2 */
+-                      gpr_map[gpr++] = 0x00000000;
+-                      /* Delaying by one sample: instead of copying the input
+-                       * value A_P16VIN to output A_FXBUS2 as in the first channel,
+-                       * we use an auxiliary register, delaying the value by one
+-                       * sample
+-                       */
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
+-                      /* For 96kHz mode */
+-                      /* Left ADC in. 2 of 2 */
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
+-                      /* Right ADC in 2 of 2 */
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
+-                      /* Pavel Hofman - we still have voices, A_FXBUS2s, and
+-                       * A_P16VINs available -
+-                       * let's add 8 more capture channels - total of 16
+-                       */
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x10));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
+-                           A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x12));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
+-                           A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x14));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
+-                           A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x16));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
+-                           A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x18));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
+-                           A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x1a));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
+-                           A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x1c));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
+-                           A_C_00000000, A_C_00000000);
+-                      gpr_map[gpr++] = 0x00000000;
+-                      snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
+-                                                                bit_shifter16,
+-                                                                A_GPR(gpr - 1),
+-                                                                A_FXBUS2(0x1e));
+-                      A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
+-                           A_C_00000000, A_C_00000000);
++                      /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
++                       * will need to also be delayed; we use an auxiliary register for that. */
++                      for (z = 1; z < 0x10; z++) {
++                              snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) );
++                              A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000);
++                              gpr_map[gpr++] = 0x00000000;
++                      }
+               }
+ 
+ #if 0
+-- 
+2.40.1
+

diff --git a/queue-5.10/alsa-hda-fix-a-possible-null-pointer-dereference-due.patch b/queue-5.10/alsa-hda-fix-a-possible-null-pointer-dereference-due.patch
new file mode 100644 (file)
index 0000000..f1e7484
--- /dev/null
+++ b/queue-5.10/alsa-hda-fix-a-possible-null-pointer-dereference-due.patch
@@ -0,0 +1,62 @@
+From af78180717ccd7213a5e8df2988282d21df07fcc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 3 Jul 2023 11:10:16 +0800
+Subject: ALSA: hda: fix a possible null-pointer dereference due to data race
+ in snd_hdac_regmap_sync()
+
+From: Tuo Li <islituo@gmail.com>
+
+[ Upstream commit 1f4a08fed450db87fbb5ff5105354158bdbe1a22 ]
+
+The variable codec->regmap is often protected by the lock
+codec->regmap_lock when is accessed. However, it is accessed without
+holding the lock when is accessed in snd_hdac_regmap_sync():
+
+  if (codec->regmap)
+
+In my opinion, this may be a harmful race, because if codec->regmap is
+set to NULL right after the condition is checked, a null-pointer
+dereference can occur in the called function regcache_sync():
+
+  map->lock(map->lock_arg); --> Line 360 in drivers/base/regmap/regcache.c
+
+To fix this possible null-pointer dereference caused by data race, the
+mutex_lock coverage is extended to protect the if statement as well as the
+function call to regcache_sync().
+
+[ Note: the lack of the regmap_lock itself is harmless for the current
+  codec driver implementations, as snd_hdac_regmap_sync() is only for
+  PM runtime resume that is prohibited during the codec probe.
+  But the change makes the whole code more consistent, so it's merged
+  as is -- tiwai ]
+
+Reported-by: BassCheck <bass@buaa.edu.cn>
+Signed-off-by: Tuo Li <islituo@gmail.com>
+Link: https://lore.kernel.org/r/20230703031016.1184711-1-islituo@gmail.com
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/hda/hdac_regmap.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/sound/hda/hdac_regmap.c b/sound/hda/hdac_regmap.c
+index d75f31eb9d78f..bf35acca5ea0e 100644
+--- a/sound/hda/hdac_regmap.c
++++ b/sound/hda/hdac_regmap.c
+@@ -597,10 +597,9 @@ EXPORT_SYMBOL_GPL(snd_hdac_regmap_update_raw_once);
+  */
+ void snd_hdac_regmap_sync(struct hdac_device *codec)
+ {
+-      if (codec->regmap) {
+-              mutex_lock(&codec->regmap_lock);
++      mutex_lock(&codec->regmap_lock);
++      if (codec->regmap)
+               regcache_sync(codec->regmap);
+-              mutex_unlock(&codec->regmap_lock);
+-      }
++      mutex_unlock(&codec->regmap_lock);
+ }
+ EXPORT_SYMBOL_GPL(snd_hdac_regmap_sync);
+-- 
+2.40.1
+

diff --git a/queue-5.10/alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch b/queue-5.10/alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch
new file mode 100644 (file)
index 0000000..1540ed1
--- /dev/null
+++ b/queue-5.10/alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch
@@ -0,0 +1,59 @@
+From f0f7e663d18679422cf7cf992c93419c0418491d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 3 Jul 2023 10:17:51 +0800
+Subject: ALSA: hda/realtek: Add quirks for Unis H3C Desktop B760 & Q760
+
+From: dengxiang <dengxiang@nfschina.com>
+
+[ Upstream commit 73f1c75d5e6bd8ce2a887ef493a66ad1b16ed704 ]
+
+These models use NSIWAY amplifiers for internal speaker, but cannot put
+sound outside from these amplifiers. So eapd verbs are needed to initialize
+the amplifiers. They can be added during boot to get working sound out
+of internal speaker.
+
+Signed-off-by: dengxiang <dengxiang@nfschina.com>
+Link: https://lore.kernel.org/r/20230703021751.2945750-1-dengxiang@nfschina.com
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/pci/hda/patch_realtek.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
+index db8593d794315..09a9e21675341 100644
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -10719,6 +10719,7 @@ enum {
+       ALC897_FIXUP_HP_HSMIC_VERB,
+       ALC897_FIXUP_LENOVO_HEADSET_MODE,
+       ALC897_FIXUP_HEADSET_MIC_PIN2,
++      ALC897_FIXUP_UNIS_H3C_X500S,
+ };
+ 
+ static const struct hda_fixup alc662_fixups[] = {
+@@ -11158,6 +11159,13 @@ static const struct hda_fixup alc662_fixups[] = {
+               .chained = true,
+               .chain_id = ALC897_FIXUP_LENOVO_HEADSET_MODE
+       },
++      [ALC897_FIXUP_UNIS_H3C_X500S] = {
++              .type = HDA_FIXUP_VERBS,
++              .v.verbs = (const struct hda_verb[]) {
++                      { 0x14, AC_VERB_SET_EAPD_BTLENABLE, 0 },
++                      {}
++              },
++      },
+ };
+ 
+ static const struct snd_pci_quirk alc662_fixup_tbl[] = {
+@@ -11319,6 +11327,7 @@ static const struct hda_model_fixup alc662_fixup_models[] = {
+       {.id = ALC662_FIXUP_USI_HEADSET_MODE, .name = "usi-headset"},
+       {.id = ALC662_FIXUP_LENOVO_MULTI_CODECS, .name = "dual-codecs"},
+       {.id = ALC669_FIXUP_ACER_ASPIRE_ETHOS, .name = "aspire-ethos"},
++      {.id = ALC897_FIXUP_UNIS_H3C_X500S, .name = "unis-h3c-x500s"},
+       {}
+ };
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch b/queue-5.10/apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch
new file mode 100644 (file)
index 0000000..d80a31b
--- /dev/null
+++ b/queue-5.10/apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch
@@ -0,0 +1,78 @@
+From 49ae1294b3a9f52f0dec083b0c0ad13b6e41388d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 27 Jan 2023 20:12:19 +0000
+Subject: apparmor: fix use of strcpy in policy_unpack_test
+
+From: Rae Moar <rmoar@google.com>
+
+[ Upstream commit b54aebd4411134b525a82d663a26b2f135ecb7e8 ]
+
+Replace the use of strcpy() in build_aa_ext_struct() in
+policy_unpack_test.c with strscpy().
+
+strscpy() is the safer method to use to ensure the buffer does not
+overflow. This was found by kernel test robot:
+https://lore.kernel.org/all/202301040348.NbfVsXO0-lkp@intel.com/.
+
+Reported-by: kernel test robot <lkp@intel.com>
+
+Signed-off-by: Rae Moar <rmoar@google.com>
+Signed-off-by: John Johansen <john.johansen@canonical.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ security/apparmor/policy_unpack_test.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/security/apparmor/policy_unpack_test.c b/security/apparmor/policy_unpack_test.c
+index 533137f45361c..3c84981aa1f48 100644
+--- a/security/apparmor/policy_unpack_test.c
++++ b/security/apparmor/policy_unpack_test.c
+@@ -66,31 +66,30 @@ struct aa_ext *build_aa_ext_struct(struct policy_unpack_fixture *puf,
+ 
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_STRING_NAME) + 1;
+-      strcpy(buf + 3, TEST_STRING_NAME);
++      strscpy(buf + 3, TEST_STRING_NAME, e->end - (void *)(buf + 3));
+ 
+       buf = e->start + TEST_STRING_BUF_OFFSET;
+       *buf = AA_STRING;
+       *(buf + 1) = strlen(TEST_STRING_DATA) + 1;
+-      strcpy(buf + 3, TEST_STRING_DATA);
+-
++      strscpy(buf + 3, TEST_STRING_DATA, e->end - (void *)(buf + 3));
+       buf = e->start + TEST_NAMED_U32_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_U32_NAME) + 1;
+-      strcpy(buf + 3, TEST_U32_NAME);
++      strscpy(buf + 3, TEST_U32_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_U32_NAME) + 1) = AA_U32;
+       *((u32 *)(buf + 3 + strlen(TEST_U32_NAME) + 2)) = TEST_U32_DATA;
+ 
+       buf = e->start + TEST_NAMED_U64_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_U64_NAME) + 1;
+-      strcpy(buf + 3, TEST_U64_NAME);
++      strscpy(buf + 3, TEST_U64_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_U64_NAME) + 1) = AA_U64;
+       *((u64 *)(buf + 3 + strlen(TEST_U64_NAME) + 2)) = TEST_U64_DATA;
+ 
+       buf = e->start + TEST_NAMED_BLOB_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_BLOB_NAME) + 1;
+-      strcpy(buf + 3, TEST_BLOB_NAME);
++      strscpy(buf + 3, TEST_BLOB_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_BLOB_NAME) + 1) = AA_BLOB;
+       *(buf + 3 + strlen(TEST_BLOB_NAME) + 2) = TEST_BLOB_DATA_SIZE;
+       memcpy(buf + 3 + strlen(TEST_BLOB_NAME) + 6,
+@@ -99,7 +98,7 @@ struct aa_ext *build_aa_ext_struct(struct policy_unpack_fixture *puf,
+       buf = e->start + TEST_NAMED_ARRAY_BUF_OFFSET;
+       *buf = AA_NAME;
+       *(buf + 1) = strlen(TEST_ARRAY_NAME) + 1;
+-      strcpy(buf + 3, TEST_ARRAY_NAME);
++      strscpy(buf + 3, TEST_ARRAY_NAME, e->end - (void *)(buf + 3));
+       *(buf + 3 + strlen(TEST_ARRAY_NAME) + 1) = AA_ARRAY;
+       *((u16 *)(buf + 3 + strlen(TEST_ARRAY_NAME) + 2)) = TEST_ARRAY_SIZE;
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch b/queue-5.10/arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch
new file mode 100644 (file)
index 0000000..0a101ef
--- /dev/null
+++ b/queue-5.10/arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch
@@ -0,0 +1,79 @@
+From c6077399069606f3548bf71985b00bfa5d03f729 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 May 2023 14:03:44 +0200
+Subject: ARM: dts: imx6dl: prtrvt, prtvt7, prti6q, prtwd2: fix USB related
+ warnings
+
+From: Oleksij Rempel <o.rempel@pengutronix.de>
+
+[ Upstream commit 1d14bd943fa2bbdfda1efbcc080b298fed5f1803 ]
+
+Fix USB-related warnings in prtrvt, prtvt7, prti6q and prtwd2 device trees
+by disabling unused usbphynop1 and usbphynop2 USB PHYs and providing proper
+configuration for the over-current detection. This fixes the following
+warnings with the current kernel:
+ usb_phy_generic usbphynop1: dummy supplies not allowed for exclusive requests
+ usb_phy_generic usbphynop2: dummy supplies not allowed for exclusive requests
+ imx_usb 2184200.usb: No over current polarity defined
+
+By the way, fix over-current detection on usbotg port for prtvt7, prti6q
+and prtwd2 boards. Only prtrvt do not have OC on USB OTG port.
+
+Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/imx6dl-prtrvt.dts   |  4 ++++
+ arch/arm/boot/dts/imx6qdl-prti6q.dtsi | 11 ++++++++++-
+ 2 files changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts
+index 5ac84445e9cc1..90e01de8c2c15 100644
+--- a/arch/arm/boot/dts/imx6dl-prtrvt.dts
++++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts
+@@ -126,6 +126,10 @@ &usbh1 {
+       status = "disabled";
+ };
+ 
++&usbotg {
++      disable-over-current;
++};
++
+ &vpu {
+       status = "disabled";
+ };
+diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
+index 19578f660b092..70dfa07a16981 100644
+--- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
+@@ -69,6 +69,7 @@ &usbh1 {
+       vbus-supply = <&reg_usb_h1_vbus>;
+       phy_type = "utmi";
+       dr_mode = "host";
++      disable-over-current;
+       status = "okay";
+ };
+ 
+@@ -78,10 +79,18 @@ &usbotg {
+       pinctrl-0 = <&pinctrl_usbotg>;
+       phy_type = "utmi";
+       dr_mode = "host";
+-      disable-over-current;
++      over-current-active-low;
+       status = "okay";
+ };
+ 
++&usbphynop1 {
++      status = "disabled";
++};
++
++&usbphynop2 {
++      status = "disabled";
++};
++
+ &usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+-- 
+2.40.1
+

diff --git a/queue-5.10/asoc-intel-sof_sdw-add-quirk-for-lnl-rvp.patch b/queue-5.10/asoc-intel-sof_sdw-add-quirk-for-lnl-rvp.patch
new file mode 100644 (file)
index 0000000..fcaebca
--- /dev/null
+++ b/queue-5.10/asoc-intel-sof_sdw-add-quirk-for-lnl-rvp.patch
@@ -0,0 +1,44 @@
+From fb98286aa3092546e963bc9bcc8468e49a64a1c6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 12 May 2023 12:33:05 -0500
+Subject: ASoC: Intel: sof_sdw: add quirk for LNL RVP
+
+From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+
+[ Upstream commit dfe25fea968dc4884e12d471c8263f0f611b380a ]
+
+We should use RT711_JD2_100K for on board rt711
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com
+Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com
+Link: https://lore.kernel.org/r/20230512173305.65399-9-pierre-louis.bossart@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/intel/boards/sof_sdw.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/sound/soc/intel/boards/sof_sdw.c b/sound/soc/intel/boards/sof_sdw.c
+index 91a7cb33042d8..30cc8bbceb79b 100644
+--- a/sound/soc/intel/boards/sof_sdw.c
++++ b/sound/soc/intel/boards/sof_sdw.c
+@@ -207,6 +207,15 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = {
+               },
+               .driver_data = (void *)(RT711_JD2_100K),
+       },
++      /* LunarLake devices */
++      {
++              .callback = sof_sdw_quirk_cb,
++              .matches = {
++                      DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
++                      DMI_MATCH(DMI_PRODUCT_NAME, "Lunar Lake Client Platform"),
++              },
++              .driver_data = (void *)(RT711_JD2_100K),
++      },
+       {}
+ };
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/asoc-intel-sof_sdw-add-quirk-for-mtl-rvp.patch b/queue-5.10/asoc-intel-sof_sdw-add-quirk-for-mtl-rvp.patch
new file mode 100644 (file)
index 0000000..c4ffdc7
--- /dev/null
+++ b/queue-5.10/asoc-intel-sof_sdw-add-quirk-for-mtl-rvp.patch
@@ -0,0 +1,43 @@
+From 58f7c8a52bb3e283087ed62267dadcd0366ea39d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 12 May 2023 12:33:00 -0500
+Subject: ASoC: Intel: sof_sdw: add quirk for MTL RVP
+
+From: Bard Liao <yung-chuan.liao@linux.intel.com>
+
+[ Upstream commit 289e1df00e49a229a1c924c059242e759a552f01 ]
+
+We should use RT711_JD2_100K for on board rt711.
+
+Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com
+Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com
+Link: https://lore.kernel.org/r/20230512173305.65399-4-pierre-louis.bossart@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/intel/boards/sof_sdw.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/sound/soc/intel/boards/sof_sdw.c b/sound/soc/intel/boards/sof_sdw.c
+index f5d8f7951cfc3..91a7cb33042d8 100644
+--- a/sound/soc/intel/boards/sof_sdw.c
++++ b/sound/soc/intel/boards/sof_sdw.c
+@@ -199,6 +199,14 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = {
+                                       SOF_RT715_DAI_ID_FIX |
+                                       SOF_SDW_PCH_DMIC),
+       },
++      {
++              .callback = sof_sdw_quirk_cb,
++              .matches = {
++                      DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
++                      DMI_MATCH(DMI_PRODUCT_NAME, "Meteor Lake Client Platform"),
++              },
++              .driver_data = (void *)(RT711_JD2_100K),
++      },
+       {}
+ };
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/asoc-intel-sof_sdw-add-support-for-rex-soundwire.patch b/queue-5.10/asoc-intel-sof_sdw-add-support-for-rex-soundwire.patch
new file mode 100644 (file)
index 0000000..16640da
--- /dev/null
+++ b/queue-5.10/asoc-intel-sof_sdw-add-support-for-rex-soundwire.patch
@@ -0,0 +1,45 @@
+From d47ff88027aa8cece4800d91bb8b913e1512a922 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Jun 2023 15:22:24 -0500
+Subject: ASoC: Intel: sof_sdw: Add support for Rex soundwire
+
+From: Uday M Bhat <uday.m.bhat@intel.com>
+
+[ Upstream commit 164e5dc17525181c05563f0a06796f1a363801d5 ]
+
+Add rex entry in the soundwire quirk table
+
+Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
+Signed-off-by: Yong Zhi <yong.zhi@intel.com>
+Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com>
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Link: https://lore.kernel.org/r/20230602202225.249209-28-pierre-louis.bossart@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/intel/boards/sof_sdw.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/sound/soc/intel/boards/sof_sdw.c b/sound/soc/intel/boards/sof_sdw.c
+index 30cc8bbceb79b..cbbb50ddc7954 100644
+--- a/sound/soc/intel/boards/sof_sdw.c
++++ b/sound/soc/intel/boards/sof_sdw.c
+@@ -207,6 +207,14 @@ static const struct dmi_system_id sof_sdw_quirk_table[] = {
+               },
+               .driver_data = (void *)(RT711_JD2_100K),
+       },
++      {
++              .callback = sof_sdw_quirk_cb,
++              .matches = {
++                      DMI_MATCH(DMI_SYS_VENDOR, "Google"),
++                      DMI_MATCH(DMI_PRODUCT_NAME, "Rex"),
++              },
++              .driver_data = (void *)(SOF_SDW_PCH_DMIC),
++      },
+       /* LunarLake devices */
+       {
+               .callback = sof_sdw_quirk_cb,
+-- 
+2.40.1
+

diff --git a/queue-5.10/bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch b/queue-5.10/bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch
new file mode 100644 (file)
index 0000000..e7e1e0f
--- /dev/null
+++ b/queue-5.10/bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch
@@ -0,0 +1,37 @@
+From 5f5ee2082d52c1522ba3089904dfa00d41fbca5c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 24 Jun 2023 12:08:10 -0500
+Subject: Bluetooth: btusb: Add MT7922 bluetooth ID for the Asus Ally
+
+From: Matthew Anderson <ruinairas1992@gmail.com>
+
+[ Upstream commit fa01eba11f0e57c767a5eab5291c7a01407a00be ]
+
+Adding the device ID from the Asus Ally gets the bluetooth working
+on the device.
+
+Signed-off-by: Matthew Anderson <ruinairas1992@gmail.com>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bluetooth/btusb.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
+index 2695ece47eb0e..49d5375b04f40 100644
+--- a/drivers/bluetooth/btusb.c
++++ b/drivers/bluetooth/btusb.c
+@@ -432,6 +432,9 @@ static const struct usb_device_id blacklist_table[] = {
+       { USB_DEVICE(0x0489, 0xe0d9), .driver_info = BTUSB_MEDIATEK |
+                                                    BTUSB_WIDEBAND_SPEECH |
+                                                    BTUSB_VALID_LE_STATES },
++      { USB_DEVICE(0x0489, 0xe0f5), .driver_info = BTUSB_MEDIATEK |
++                                                   BTUSB_WIDEBAND_SPEECH |
++                                                   BTUSB_VALID_LE_STATES },
+       { USB_DEVICE(0x13d3, 0x3568), .driver_info = BTUSB_MEDIATEK |
+                                                    BTUSB_WIDEBAND_SPEECH |
+                                                    BTUSB_VALID_LE_STATES },
+-- 
+2.40.1
+

diff --git a/queue-5.10/bluetooth-l2cap-fix-use-after-free.patch b/queue-5.10/bluetooth-l2cap-fix-use-after-free.patch
new file mode 100644 (file)
index 0000000..577619b
--- /dev/null
+++ b/queue-5.10/bluetooth-l2cap-fix-use-after-free.patch
@@ -0,0 +1,41 @@
+From f8675d61b7c8f37417c7ce906ac1522ab69917d2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 May 2023 17:04:15 -0700
+Subject: Bluetooth: L2CAP: Fix use-after-free
+
+From: Zhengping Jiang <jiangzp@google.com>
+
+[ Upstream commit f752a0b334bb95fe9b42ecb511e0864e2768046f ]
+
+Fix potential use-after-free in l2cap_le_command_rej.
+
+Signed-off-by: Zhengping Jiang <jiangzp@google.com>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bluetooth/l2cap_core.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
+index 568f0f072b3df..7b40e4737a2bb 100644
+--- a/net/bluetooth/l2cap_core.c
++++ b/net/bluetooth/l2cap_core.c
+@@ -6370,9 +6370,14 @@ static inline int l2cap_le_command_rej(struct l2cap_conn *conn,
+       if (!chan)
+               goto done;
+ 
++      chan = l2cap_chan_hold_unless_zero(chan);
++      if (!chan)
++              goto done;
++
+       l2cap_chan_lock(chan);
+       l2cap_chan_del(chan, ECONNREFUSED);
+       l2cap_chan_unlock(chan);
++      l2cap_chan_put(chan);
+ 
+ done:
+       mutex_unlock(&conn->chan_lock);
+-- 
+2.40.1
+

diff --git a/queue-5.10/bus-mhi-add-mhi-pci-support-for-wwan-modems.patch b/queue-5.10/bus-mhi-add-mhi-pci-support-for-wwan-modems.patch
new file mode 100644 (file)
index 0000000..07888b1
--- /dev/null
+++ b/queue-5.10/bus-mhi-add-mhi-pci-support-for-wwan-modems.patch
@@ -0,0 +1,415 @@
+From 0a446e132250ee94fd75756946ce9c966c041022 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Oct 2020 19:18:19 +0200
+Subject: bus: mhi: Add MHI PCI support for WWAN modems
+
+From: Loic Poulain <loic.poulain@linaro.org>
+
+[ Upstream commit 855a70c12021bdc5df60512f1d3f6d492dc715be ]
+
+This is a generic MHI-over-PCI controller driver for MHI only devices
+such as QCOM modems. For now it supports registering of Qualcomm SDX55
+based PCIe modules. The MHI channels have been extracted from mhi
+downstream driver.
+
+This driver is for MHI-only devices which have all functionalities
+exposed through MHI channels and accessed by the corresponding MHI
+device drivers (no out-of-band communication).
+
+Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
+Reviewed-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
+Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+[mani: fixed up the Makefile rule]
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Stable-dep-of: 6a0c637bfee6 ("bus: mhi: host: Range check CHDBOFF and ERDBOFF")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bus/mhi/Kconfig       |   9 +
+ drivers/bus/mhi/Makefile      |   4 +
+ drivers/bus/mhi/pci_generic.c | 345 ++++++++++++++++++++++++++++++++++
+ 3 files changed, 358 insertions(+)
+ create mode 100644 drivers/bus/mhi/pci_generic.c
+
+diff --git a/drivers/bus/mhi/Kconfig b/drivers/bus/mhi/Kconfig
+index e841c1097fb4d..da5cd0c9fc620 100644
+--- a/drivers/bus/mhi/Kconfig
++++ b/drivers/bus/mhi/Kconfig
+@@ -20,3 +20,12 @@ config MHI_BUS_DEBUG
+         Enable debugfs support for use with the MHI transport. Allows
+         reading and/or modifying some values within the MHI controller
+         for debug and test purposes.
++
++config MHI_BUS_PCI_GENERIC
++      tristate "MHI PCI controller driver"
++      depends on MHI_BUS
++      depends on PCI
++      help
++        This driver provides MHI PCI controller driver for devices such as
++        Qualcomm SDX55 based PCIe modems.
++
+diff --git a/drivers/bus/mhi/Makefile b/drivers/bus/mhi/Makefile
+index 19e6443b72df4..0a2d778d6fb42 100644
+--- a/drivers/bus/mhi/Makefile
++++ b/drivers/bus/mhi/Makefile
+@@ -1,2 +1,6 @@
+ # core layer
+ obj-y += core/
++
++obj-$(CONFIG_MHI_BUS_PCI_GENERIC) += mhi_pci_generic.o
++mhi_pci_generic-y += pci_generic.o
++
+diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
+new file mode 100644
+index 0000000000000..e3df838c3c80e
+--- /dev/null
++++ b/drivers/bus/mhi/pci_generic.c
+@@ -0,0 +1,345 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * MHI PCI driver - MHI over PCI controller driver
++ *
++ * This module is a generic driver for registering MHI-over-PCI devices,
++ * such as PCIe QCOM modems.
++ *
++ * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
++ */
++
++#include <linux/device.h>
++#include <linux/mhi.h>
++#include <linux/module.h>
++#include <linux/pci.h>
++
++#define MHI_PCI_DEFAULT_BAR_NUM 0
++
++/**
++ * struct mhi_pci_dev_info - MHI PCI device specific information
++ * @config: MHI controller configuration
++ * @name: name of the PCI module
++ * @fw: firmware path (if any)
++ * @edl: emergency download mode firmware path (if any)
++ * @bar_num: PCI base address register to use for MHI MMIO register space
++ * @dma_data_width: DMA transfer word size (32 or 64 bits)
++ */
++struct mhi_pci_dev_info {
++      const struct mhi_controller_config *config;
++      const char *name;
++      const char *fw;
++      const char *edl;
++      unsigned int bar_num;
++      unsigned int dma_data_width;
++};
++
++#define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
++      {                                               \
++              .num = ch_num,                          \
++              .name = ch_name,                        \
++              .num_elements = el_count,               \
++              .event_ring = ev_ring,                  \
++              .dir = DMA_TO_DEVICE,                   \
++              .ee_mask = BIT(MHI_EE_AMSS),            \
++              .pollcfg = 0,                           \
++              .doorbell = MHI_DB_BRST_DISABLE,        \
++              .lpm_notify = false,                    \
++              .offload_channel = false,               \
++              .doorbell_mode_switch = false,          \
++      }                                               \
++
++#define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
++      {                                               \
++              .num = ch_num,                          \
++              .name = ch_name,                        \
++              .num_elements = el_count,               \
++              .event_ring = ev_ring,                  \
++              .dir = DMA_FROM_DEVICE,                 \
++              .ee_mask = BIT(MHI_EE_AMSS),            \
++              .pollcfg = 0,                           \
++              .doorbell = MHI_DB_BRST_DISABLE,        \
++              .lpm_notify = false,                    \
++              .offload_channel = false,               \
++              .doorbell_mode_switch = false,          \
++      }
++
++#define MHI_EVENT_CONFIG_CTRL(ev_ring)                \
++      {                                       \
++              .num_elements = 64,             \
++              .irq_moderation_ms = 0,         \
++              .irq = (ev_ring) + 1,           \
++              .priority = 1,                  \
++              .mode = MHI_DB_BRST_DISABLE,    \
++              .data_type = MHI_ER_CTRL,       \
++              .hardware_event = false,        \
++              .client_managed = false,        \
++              .offload_channel = false,       \
++      }
++
++#define MHI_EVENT_CONFIG_DATA(ev_ring)                \
++      {                                       \
++              .num_elements = 128,            \
++              .irq_moderation_ms = 5,         \
++              .irq = (ev_ring) + 1,           \
++              .priority = 1,                  \
++              .mode = MHI_DB_BRST_DISABLE,    \
++              .data_type = MHI_ER_DATA,       \
++              .hardware_event = false,        \
++              .client_managed = false,        \
++              .offload_channel = false,       \
++      }
++
++#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \
++      {                                       \
++              .num_elements = 128,            \
++              .irq_moderation_ms = 5,         \
++              .irq = (ev_ring) + 1,           \
++              .priority = 1,                  \
++              .mode = MHI_DB_BRST_DISABLE,    \
++              .data_type = MHI_ER_DATA,       \
++              .hardware_event = true,         \
++              .client_managed = false,        \
++              .offload_channel = false,       \
++              .channel = ch_num,              \
++      }
++
++static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
++      MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
++      MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
++      MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
++      MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
++      MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
++      MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0),
++      MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1),
++      MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2),
++};
++
++static const struct mhi_event_config modem_qcom_v1_mhi_events[] = {
++      /* first ring is control+data ring */
++      MHI_EVENT_CONFIG_CTRL(0),
++      /* Hardware channels request dedicated hardware event rings */
++      MHI_EVENT_CONFIG_HW_DATA(1, 100),
++      MHI_EVENT_CONFIG_HW_DATA(2, 101)
++};
++
++static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
++      .max_channels = 128,
++      .timeout_ms = 5000,
++      .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
++      .ch_cfg = modem_qcom_v1_mhi_channels,
++      .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
++      .event_cfg = modem_qcom_v1_mhi_events,
++};
++
++static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
++      .name = "qcom-sdx55m",
++      .fw = "qcom/sdx55m/sbl1.mbn",
++      .edl = "qcom/sdx55m/edl.mbn",
++      .config = &modem_qcom_v1_mhiv_config,
++      .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
++      .dma_data_width = 32
++};
++
++static const struct pci_device_id mhi_pci_id_table[] = {
++      { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
++              .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
++      {  }
++};
++MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
++
++static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
++                          void __iomem *addr, u32 *out)
++{
++      *out = readl(addr);
++      return 0;
++}
++
++static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
++                            void __iomem *addr, u32 val)
++{
++      writel(val, addr);
++}
++
++static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
++                            enum mhi_callback cb)
++{
++      /* Nothing to do for now */
++}
++
++static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
++                       unsigned int bar_num, u64 dma_mask)
++{
++      struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
++      int err;
++
++      err = pci_assign_resource(pdev, bar_num);
++      if (err)
++              return err;
++
++      err = pcim_enable_device(pdev);
++      if (err) {
++              dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
++              return err;
++      }
++
++      err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
++      if (err) {
++              dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
++              return err;
++      }
++      mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
++
++      err = pci_set_dma_mask(pdev, dma_mask);
++      if (err) {
++              dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
++              return err;
++      }
++
++      err = pci_set_consistent_dma_mask(pdev, dma_mask);
++      if (err) {
++              dev_err(&pdev->dev, "set consistent dma mask failed\n");
++              return err;
++      }
++
++      pci_set_master(pdev);
++
++      return 0;
++}
++
++static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
++                          const struct mhi_controller_config *mhi_cntrl_config)
++{
++      struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
++      int nr_vectors, i;
++      int *irq;
++
++      /*
++       * Alloc one MSI vector for BHI + one vector per event ring, ideally...
++       * No explicit pci_free_irq_vectors required, done by pcim_release.
++       */
++      mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
++
++      nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
++      if (nr_vectors < 0) {
++              dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
++                      nr_vectors);
++              return nr_vectors;
++      }
++
++      if (nr_vectors < mhi_cntrl->nr_irqs) {
++              dev_warn(&pdev->dev, "Not enough MSI vectors (%d/%d), use shared MSI\n",
++                       nr_vectors, mhi_cntrl_config->num_events);
++      }
++
++      irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
++      if (!irq)
++              return -ENOMEM;
++
++      for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
++              int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
++
++              irq[i] = pci_irq_vector(pdev, vector);
++      }
++
++      mhi_cntrl->irq = irq;
++
++      return 0;
++}
++
++static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
++{
++      /* no PM for now */
++      return 0;
++}
++
++static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
++{
++      /* no PM for now */
++}
++
++static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
++{
++      const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
++      const struct mhi_controller_config *mhi_cntrl_config;
++      struct mhi_controller *mhi_cntrl;
++      int err;
++
++      dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name);
++
++      mhi_cntrl = mhi_alloc_controller();
++      if (!mhi_cntrl)
++              return -ENOMEM;
++
++      mhi_cntrl_config = info->config;
++      mhi_cntrl->cntrl_dev = &pdev->dev;
++      mhi_cntrl->iova_start = 0;
++      mhi_cntrl->iova_stop = DMA_BIT_MASK(info->dma_data_width);
++      mhi_cntrl->fw_image = info->fw;
++      mhi_cntrl->edl_image = info->edl;
++
++      mhi_cntrl->read_reg = mhi_pci_read_reg;
++      mhi_cntrl->write_reg = mhi_pci_write_reg;
++      mhi_cntrl->status_cb = mhi_pci_status_cb;
++      mhi_cntrl->runtime_get = mhi_pci_runtime_get;
++      mhi_cntrl->runtime_put = mhi_pci_runtime_put;
++
++      err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
++      if (err)
++              goto err_release;
++
++      err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
++      if (err)
++              goto err_release;
++
++      pci_set_drvdata(pdev, mhi_cntrl);
++
++      err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
++      if (err)
++              goto err_release;
++
++      /* MHI bus does not power up the controller by default */
++      err = mhi_prepare_for_power_up(mhi_cntrl);
++      if (err) {
++              dev_err(&pdev->dev, "failed to prepare MHI controller\n");
++              goto err_unregister;
++      }
++
++      err = mhi_sync_power_up(mhi_cntrl);
++      if (err) {
++              dev_err(&pdev->dev, "failed to power up MHI controller\n");
++              goto err_unprepare;
++      }
++
++      return 0;
++
++err_unprepare:
++      mhi_unprepare_after_power_down(mhi_cntrl);
++err_unregister:
++      mhi_unregister_controller(mhi_cntrl);
++err_release:
++      mhi_free_controller(mhi_cntrl);
++
++      return err;
++}
++
++static void mhi_pci_remove(struct pci_dev *pdev)
++{
++      struct mhi_controller *mhi_cntrl = pci_get_drvdata(pdev);
++
++      mhi_power_down(mhi_cntrl, true);
++      mhi_unprepare_after_power_down(mhi_cntrl);
++      mhi_unregister_controller(mhi_cntrl);
++      mhi_free_controller(mhi_cntrl);
++}
++
++static struct pci_driver mhi_pci_driver = {
++      .name           = "mhi-pci-generic",
++      .id_table       = mhi_pci_id_table,
++      .probe          = mhi_pci_probe,
++      .remove         = mhi_pci_remove
++};
++module_pci_driver(mhi_pci_driver);
++
++MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
++MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
++MODULE_LICENSE("GPL");
+-- 
+2.40.1
+

diff --git a/queue-5.10/bus-mhi-add-mmio-region-length-to-controller-structu.patch b/queue-5.10/bus-mhi-add-mmio-region-length-to-controller-structu.patch
new file mode 100644 (file)
index 0000000..1a56833
--- /dev/null
+++ b/queue-5.10/bus-mhi-add-mmio-region-length-to-controller-structu.patch
@@ -0,0 +1,51 @@
+From 8c551509b6578b4052e85b65eb397567801c233a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 2 Aug 2021 10:42:50 +0530
+Subject: bus: mhi: Add MMIO region length to controller structure
+
+From: Bhaumik Bhatt <bbhatt@codeaurora.org>
+
+[ Upstream commit baa7a08569358d9d16e71ce36f287c39a665d776 ]
+
+Make controller driver specify the MMIO register region length
+for range checking of BHI or BHIe space. This can help validate
+that offsets are in acceptable memory region or not and avoid any
+boot-up issues due to BHI or BHIe memory accesses.
+
+Link: https://lore.kernel.org/r/1620330705-40192-4-git-send-email-bbhatt@codeaurora.org
+Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
+Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/20210802051255.5771-6-manivannan.sadhasivam@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: 6a0c637bfee6 ("bus: mhi: host: Range check CHDBOFF and ERDBOFF")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/mhi.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/mhi.h b/include/linux/mhi.h
+index d4841e5a5f458..5d9f8c6f3d40f 100644
+--- a/include/linux/mhi.h
++++ b/include/linux/mhi.h
+@@ -303,6 +303,7 @@ struct mhi_controller_config {
+  * @rddm_size: RAM dump size that host should allocate for debugging purpose
+  * @sbl_size: SBL image size downloaded through BHIe (optional)
+  * @seg_len: BHIe vector size (optional)
++ * @reg_len: Length of the MHI MMIO region (required)
+  * @fbc_image: Points to firmware image buffer
+  * @rddm_image: Points to RAM dump buffer
+  * @mhi_chan: Points to the channel configuration table
+@@ -383,6 +384,7 @@ struct mhi_controller {
+       size_t rddm_size;
+       size_t sbl_size;
+       size_t seg_len;
++      size_t reg_len;
+       struct image_info *fbc_image;
+       struct image_info *rddm_image;
+       struct mhi_chan *mhi_chan;
+-- 
+2.40.1
+

diff --git a/queue-5.10/bus-mhi-host-range-check-chdboff-and-erdboff.patch b/queue-5.10/bus-mhi-host-range-check-chdboff-and-erdboff.patch
new file mode 100644 (file)
index 0000000..ef12bfc
--- /dev/null
+++ b/queue-5.10/bus-mhi-host-range-check-chdboff-and-erdboff.patch
@@ -0,0 +1,59 @@
+From 2675990b4bea3d985bd09d02d9e3a0f2d17fab21 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 24 Mar 2023 10:13:04 -0600
+Subject: bus: mhi: host: Range check CHDBOFF and ERDBOFF
+
+From: Jeffrey Hugo <quic_jhugo@quicinc.com>
+
+[ Upstream commit 6a0c637bfee69a74c104468544d9f2a6579626d0 ]
+
+If the value read from the CHDBOFF and ERDBOFF registers is outside the
+range of the MHI register space then an invalid address might be computed
+which later causes a kernel panic.  Range check the read value to prevent
+a crash due to bad data from the device.
+
+Fixes: 6cd330ae76ff ("bus: mhi: core: Add support for ringing channel/event ring doorbells")
+Cc: stable@vger.kernel.org
+Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
+Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Link: https://lore.kernel.org/r/1679674384-27209-1-git-send-email-quic_jhugo@quicinc.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bus/mhi/host/init.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c
+index 0d0386f67ffe2..2cc48f96afdbc 100644
+--- a/drivers/bus/mhi/host/init.c
++++ b/drivers/bus/mhi/host/init.c
+@@ -498,6 +498,12 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
+               return -EIO;
+       }
+ 
++      if (val >= mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)) {
++              dev_err(dev, "CHDB offset: 0x%x is out of range: 0x%zx\n",
++                      val, mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB));
++              return -ERANGE;
++      }
++
+       /* Setup wake db */
+       mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
+       mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);
+@@ -517,6 +523,12 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
+               return -EIO;
+       }
+ 
++      if (val >= mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)) {
++              dev_err(dev, "ERDB offset: 0x%x is out of range: 0x%zx\n",
++                      val, mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings));
++              return -ERANGE;
++      }
++
+       /* Setup event db address for each ev_ring */
+       mhi_event = mhi_cntrl->mhi_event;
+       for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
+-- 
+2.40.1
+

diff --git a/queue-5.10/bus-mhi-move-host-mhi-code-to-host-directory.patch b/queue-5.10/bus-mhi-move-host-mhi-code-to-host-directory.patch
new file mode 100644 (file)
index 0000000..cc1b44a
--- /dev/null
+++ b/queue-5.10/bus-mhi-move-host-mhi-code-to-host-directory.patch
@@ -0,0 +1,189 @@
+From 5a306081b9f2013e958e7c1ab44800d65ab3b266 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Mar 2022 21:33:02 +0530
+Subject: bus: mhi: Move host MHI code to "host" directory
+
+From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+[ Upstream commit a0f5a630668cb8b2ebf5204f08e957875e991780 ]
+
+In preparation of the endpoint MHI support, let's move the host MHI code
+to its own "host" directory and adjust the toplevel MHI Kconfig & Makefile.
+
+While at it, let's also move the "pci_generic" driver to "host" directory
+as it is a host MHI controller driver.
+
+Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
+Reviewed-by: Alex Elder <elder@linaro.org>
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/20220301160308.107452-5-manivannan.sadhasivam@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: 6a0c637bfee6 ("bus: mhi: host: Range check CHDBOFF and ERDBOFF")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/bus/Makefile                      |  2 +-
+ drivers/bus/mhi/Kconfig                   | 27 ++------------------
+ drivers/bus/mhi/Makefile                  |  8 ++----
+ drivers/bus/mhi/host/Kconfig              | 31 +++++++++++++++++++++++
+ drivers/bus/mhi/{core => host}/Makefile   |  4 ++-
+ drivers/bus/mhi/{core => host}/boot.c     |  0
+ drivers/bus/mhi/{core => host}/debugfs.c  |  0
+ drivers/bus/mhi/{core => host}/init.c     |  0
+ drivers/bus/mhi/{core => host}/internal.h |  0
+ drivers/bus/mhi/{core => host}/main.c     |  0
+ drivers/bus/mhi/{ => host}/pci_generic.c  |  0
+ drivers/bus/mhi/{core => host}/pm.c       |  0
+ 12 files changed, 39 insertions(+), 33 deletions(-)
+ create mode 100644 drivers/bus/mhi/host/Kconfig
+ rename drivers/bus/mhi/{core => host}/Makefile (54%)
+ rename drivers/bus/mhi/{core => host}/boot.c (100%)
+ rename drivers/bus/mhi/{core => host}/debugfs.c (100%)
+ rename drivers/bus/mhi/{core => host}/init.c (100%)
+ rename drivers/bus/mhi/{core => host}/internal.h (100%)
+ rename drivers/bus/mhi/{core => host}/main.c (100%)
+ rename drivers/bus/mhi/{ => host}/pci_generic.c (100%)
+ rename drivers/bus/mhi/{core => host}/pm.c (100%)
+
+diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
+index 397e35392bff8..16c47a0616ae4 100644
+--- a/drivers/bus/Makefile
++++ b/drivers/bus/Makefile
+@@ -38,4 +38,4 @@ obj-$(CONFIG_VEXPRESS_CONFIG)        += vexpress-config.o
+ obj-$(CONFIG_DA8XX_MSTPRI)    += da8xx-mstpri.o
+ 
+ # MHI
+-obj-$(CONFIG_MHI_BUS)         += mhi/
++obj-y                         += mhi/
+diff --git a/drivers/bus/mhi/Kconfig b/drivers/bus/mhi/Kconfig
+index da5cd0c9fc620..4748df7f9cd58 100644
+--- a/drivers/bus/mhi/Kconfig
++++ b/drivers/bus/mhi/Kconfig
+@@ -2,30 +2,7 @@
+ #
+ # MHI bus
+ #
+-# Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
++# Copyright (c) 2021, Linaro Ltd.
+ #
+ 
+-config MHI_BUS
+-      tristate "Modem Host Interface (MHI) bus"
+-      help
+-        Bus driver for MHI protocol. Modem Host Interface (MHI) is a
+-        communication protocol used by the host processors to control
+-        and communicate with modem devices over a high speed peripheral
+-        bus or shared memory.
+-
+-config MHI_BUS_DEBUG
+-      bool "Debugfs support for the MHI bus"
+-      depends on MHI_BUS && DEBUG_FS
+-      help
+-        Enable debugfs support for use with the MHI transport. Allows
+-        reading and/or modifying some values within the MHI controller
+-        for debug and test purposes.
+-
+-config MHI_BUS_PCI_GENERIC
+-      tristate "MHI PCI controller driver"
+-      depends on MHI_BUS
+-      depends on PCI
+-      help
+-        This driver provides MHI PCI controller driver for devices such as
+-        Qualcomm SDX55 based PCIe modems.
+-
++source "drivers/bus/mhi/host/Kconfig"
+diff --git a/drivers/bus/mhi/Makefile b/drivers/bus/mhi/Makefile
+index 0a2d778d6fb42..5f5708a249f54 100644
+--- a/drivers/bus/mhi/Makefile
++++ b/drivers/bus/mhi/Makefile
+@@ -1,6 +1,2 @@
+-# core layer
+-obj-y += core/
+-
+-obj-$(CONFIG_MHI_BUS_PCI_GENERIC) += mhi_pci_generic.o
+-mhi_pci_generic-y += pci_generic.o
+-
++# Host MHI stack
++obj-y += host/
+diff --git a/drivers/bus/mhi/host/Kconfig b/drivers/bus/mhi/host/Kconfig
+new file mode 100644
+index 0000000000000..da5cd0c9fc620
+--- /dev/null
++++ b/drivers/bus/mhi/host/Kconfig
+@@ -0,0 +1,31 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# MHI bus
++#
++# Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
++#
++
++config MHI_BUS
++      tristate "Modem Host Interface (MHI) bus"
++      help
++        Bus driver for MHI protocol. Modem Host Interface (MHI) is a
++        communication protocol used by the host processors to control
++        and communicate with modem devices over a high speed peripheral
++        bus or shared memory.
++
++config MHI_BUS_DEBUG
++      bool "Debugfs support for the MHI bus"
++      depends on MHI_BUS && DEBUG_FS
++      help
++        Enable debugfs support for use with the MHI transport. Allows
++        reading and/or modifying some values within the MHI controller
++        for debug and test purposes.
++
++config MHI_BUS_PCI_GENERIC
++      tristate "MHI PCI controller driver"
++      depends on MHI_BUS
++      depends on PCI
++      help
++        This driver provides MHI PCI controller driver for devices such as
++        Qualcomm SDX55 based PCIe modems.
++
+diff --git a/drivers/bus/mhi/core/Makefile b/drivers/bus/mhi/host/Makefile
+similarity index 54%
+rename from drivers/bus/mhi/core/Makefile
+rename to drivers/bus/mhi/host/Makefile
+index c3feb4130aa37..859c2f38451c6 100644
+--- a/drivers/bus/mhi/core/Makefile
++++ b/drivers/bus/mhi/host/Makefile
+@@ -1,4 +1,6 @@
+ obj-$(CONFIG_MHI_BUS) += mhi.o
+-
+ mhi-y := init.o main.o pm.o boot.o
+ mhi-$(CONFIG_MHI_BUS_DEBUG) += debugfs.o
++
++obj-$(CONFIG_MHI_BUS_PCI_GENERIC) += mhi_pci_generic.o
++mhi_pci_generic-y += pci_generic.o
+diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/host/boot.c
+similarity index 100%
+rename from drivers/bus/mhi/core/boot.c
+rename to drivers/bus/mhi/host/boot.c
+diff --git a/drivers/bus/mhi/core/debugfs.c b/drivers/bus/mhi/host/debugfs.c
+similarity index 100%
+rename from drivers/bus/mhi/core/debugfs.c
+rename to drivers/bus/mhi/host/debugfs.c
+diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/host/init.c
+similarity index 100%
+rename from drivers/bus/mhi/core/init.c
+rename to drivers/bus/mhi/host/init.c
+diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/host/internal.h
+similarity index 100%
+rename from drivers/bus/mhi/core/internal.h
+rename to drivers/bus/mhi/host/internal.h
+diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/host/main.c
+similarity index 100%
+rename from drivers/bus/mhi/core/main.c
+rename to drivers/bus/mhi/host/main.c
+diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
+similarity index 100%
+rename from drivers/bus/mhi/pci_generic.c
+rename to drivers/bus/mhi/host/pci_generic.c
+diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/host/pm.c
+similarity index 100%
+rename from drivers/bus/mhi/core/pm.c
+rename to drivers/bus/mhi/host/pm.c
+-- 
+2.40.1
+

diff --git a/queue-5.10/dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch b/queue-5.10/dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch
new file mode 100644 (file)
index 0000000..ed7e131
--- /dev/null
+++ b/queue-5.10/dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch
@@ -0,0 +1,63 @@
+From bb6ba1cc5b0326881187a7cdc02d9968d5ba97bf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Jun 2023 12:47:37 +0000
+Subject: dma-remap: use kvmalloc_array/kvfree for larger dma memory remap
+
+From: gaoxu <gaoxu2@hihonor.com>
+
+[ Upstream commit 51ff97d54f02b4444dfc42e380ac4c058e12d5dd ]
+
+If dma_direct_alloc() alloc memory in size of 64MB, the inner function
+dma_common_contiguous_remap() will allocate 128KB memory by invoking
+the function kmalloc_array(). and the kmalloc_array seems to fail to try to
+allocate 128KB mem.
+
+Call trace:
+[14977.928623] qcrosvm: page allocation failure: order:5, mode:0x40cc0
+[14977.928638] dump_backtrace.cfi_jt+0x0/0x8
+[14977.928647] dump_stack_lvl+0x80/0xb8
+[14977.928652] warn_alloc+0x164/0x200
+[14977.928657] __alloc_pages_slowpath+0x9f0/0xb4c
+[14977.928660] __alloc_pages+0x21c/0x39c
+[14977.928662] kmalloc_order+0x48/0x108
+[14977.928666] kmalloc_order_trace+0x34/0x154
+[14977.928668] __kmalloc+0x548/0x7e4
+[14977.928673] dma_direct_alloc+0x11c/0x4f8
+[14977.928678] dma_alloc_attrs+0xf4/0x138
+[14977.928680] gh_vm_ioctl_set_fw_name+0x3c4/0x610 [gunyah]
+[14977.928698] gh_vm_ioctl+0x90/0x14c [gunyah]
+[14977.928705] __arm64_sys_ioctl+0x184/0x210
+
+work around by doing kvmalloc_array instead.
+
+Signed-off-by: Gao Xu <gaoxu2@hihonor.com>
+Reviewed-by: Suren Baghdasaryan <surenb@google.com>
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/dma/remap.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/dma/remap.c b/kernel/dma/remap.c
+index 905c3fa005f10..5bff061993102 100644
+--- a/kernel/dma/remap.c
++++ b/kernel/dma/remap.c
+@@ -43,13 +43,13 @@ void *dma_common_contiguous_remap(struct page *page, size_t size,
+       void *vaddr;
+       int i;
+ 
+-      pages = kmalloc_array(count, sizeof(struct page *), GFP_KERNEL);
++      pages = kvmalloc_array(count, sizeof(struct page *), GFP_KERNEL);
+       if (!pages)
+               return NULL;
+       for (i = 0; i < count; i++)
+               pages[i] = nth_page(page, i);
+       vaddr = vmap(pages, count, VM_DMA_COHERENT, prot);
+-      kfree(pages);
++      kvfree(pages);
+ 
+       return vaddr;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.10/drm-amdgpu-fix-potential-fence-use-after-free-v2.patch b/queue-5.10/drm-amdgpu-fix-potential-fence-use-after-free-v2.patch
new file mode 100644 (file)
index 0000000..c4532da
--- /dev/null
+++ b/queue-5.10/drm-amdgpu-fix-potential-fence-use-after-free-v2.patch
@@ -0,0 +1,52 @@
+From bb8e22738ce2287da2ea712b4a32483abf2214f0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Jun 2023 18:10:47 -0700
+Subject: drm/amdgpu: Fix potential fence use-after-free v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: shanzhulig <shanzhulig@gmail.com>
+
+[ Upstream commit 2e54154b9f27262efd0cb4f903cc7d5ad1fe9628 ]
+
+fence Decrements the reference count before exiting.
+Avoid Race Vulnerabilities for fence use-after-free.
+
+v2 (chk): actually fix the use after free and not just move it.
+
+Signed-off-by: shanzhulig <shanzhulig@gmail.com>
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index ffd8f5601e28a..e25c3387bcf87 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -1517,15 +1517,15 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
+                       continue;
+ 
+               r = dma_fence_wait_timeout(fence, true, timeout);
++              if (r > 0 && fence->error)
++                      r = fence->error;
++
+               dma_fence_put(fence);
+               if (r < 0)
+                       return r;
+ 
+               if (r == 0)
+                       break;
+-
+-              if (fence->error)
+-                      return fence->error;
+       }
+ 
+       memset(wait, 0, sizeof(*wait));
+-- 
+2.40.1
+

diff --git a/queue-5.10/drm-amdgpu-install-stub-fence-into-potential-unused-.patch b/queue-5.10/drm-amdgpu-install-stub-fence-into-potential-unused-.patch
new file mode 100644 (file)
index 0000000..eb86fff
--- /dev/null
+++ b/queue-5.10/drm-amdgpu-install-stub-fence-into-potential-unused-.patch
@@ -0,0 +1,59 @@
+From a709958b37c121bf10e0dd0250cdbd647e2db7a1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 5 May 2023 20:14:15 +0800
+Subject: drm/amdgpu: install stub fence into potential unused fence pointers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Lang Yu <Lang.Yu@amd.com>
+
+[ Upstream commit 187916e6ed9d0c3b3abc27429f7a5f8c936bd1f0 ]
+
+When using cpu to update page tables, vm update fences are unused.
+Install stub fence into these fence pointers instead of NULL
+to avoid NULL dereference when calling dma_fence_wait() on them.
+
+Suggested-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Lang Yu <Lang.Yu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 8445bb7ae06ab..3b4724d60868f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2155,6 +2155,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
+       amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
+ 
+       bo_va->ref_count = 1;
++      bo_va->last_pt_update = dma_fence_get_stub();
+       INIT_LIST_HEAD(&bo_va->valids);
+       INIT_LIST_HEAD(&bo_va->invalids);
+ 
+@@ -2867,7 +2868,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+               vm->update_funcs = &amdgpu_vm_cpu_funcs;
+       else
+               vm->update_funcs = &amdgpu_vm_sdma_funcs;
+-      vm->last_update = NULL;
++
++      vm->last_update = dma_fence_get_stub();
+       vm->last_unlocked = dma_fence_get_stub();
+ 
+       mutex_init(&vm->eviction_lock);
+@@ -3042,7 +3044,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+               vm->update_funcs = &amdgpu_vm_sdma_funcs;
+       }
+       dma_fence_put(vm->last_update);
+-      vm->last_update = NULL;
++      vm->last_update = dma_fence_get_stub();
+       vm->is_compute_context = true;
+ 
+       if (vm->pasid) {
+-- 
+2.40.1
+

diff --git a/queue-5.10/drm-radeon-fix-integer-overflow-in-radeon_cs_parser_.patch b/queue-5.10/drm-radeon-fix-integer-overflow-in-radeon_cs_parser_.patch
new file mode 100644 (file)
index 0000000..d2bc153
--- /dev/null
+++ b/queue-5.10/drm-radeon-fix-integer-overflow-in-radeon_cs_parser_.patch
@@ -0,0 +1,41 @@
+From 16444173800e7361dffdb11f003e0f7d14489af2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 19 Apr 2023 20:20:58 +0800
+Subject: drm/radeon: Fix integer overflow in radeon_cs_parser_init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: hackyzh002 <hackyzh002@gmail.com>
+
+[ Upstream commit f828b681d0cd566f86351c0b913e6cb6ed8c7b9c ]
+
+The type of size is unsigned, if size is 0x40000000, there will be an
+integer overflow, size will be zero after size *= sizeof(uint32_t),
+will cause uninitialized memory to be referenced later
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: hackyzh002 <hackyzh002@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/radeon/radeon_cs.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
+index a78b60b62caf2..87a57e5588a28 100644
+--- a/drivers/gpu/drm/radeon/radeon_cs.c
++++ b/drivers/gpu/drm/radeon/radeon_cs.c
+@@ -271,7 +271,8 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
+ {
+       struct drm_radeon_cs *cs = data;
+       uint64_t *chunk_array_ptr;
+-      unsigned size, i;
++      u64 size;
++      unsigned i;
+       u32 ring = RADEON_CS_RING_GFX;
+       s32 priority = 0;
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/dt-bindings-iio-add-ad74413r.patch b/queue-5.10/dt-bindings-iio-add-ad74413r.patch
new file mode 100644 (file)
index 0000000..7348921
--- /dev/null
+++ b/queue-5.10/dt-bindings-iio-add-ad74413r.patch
@@ -0,0 +1,231 @@
+From 1bfea8242f4b96a8807c48dd26a2afb22cde256e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 5 Dec 2021 13:40:44 +0200
+Subject: dt-bindings: iio: add AD74413R
+
+From: Cosmin Tanislav <demonsingur@gmail.com>
+
+[ Upstream commit 3cf3cdea6fe3fdb7a1e4ac1372b80408e4f56b73 ]
+
+The AD74412R and AD74413R are quad-channel, software configurable,
+input/output solutions for building and process control applications.
+
+They contain functionality for analog output, analog input, digital input,
+resistance temperature detector, and thermocouple measurements integrated
+into a single chip solution with an SPI interface.
+
+The devices feature a 16-bit ADC and four configurable 13-bit DACs to
+provide four configurable input/output channels and a suite of diagnostic
+functions.
+
+The AD74413R differentiates itself from the AD74412R by being
+HART-compatible.
+
+Signed-off-by: Cosmin Tanislav <cosmin.tanislav@analog.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20211205114045.173612-3-cosmin.tanislav@analog.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../bindings/iio/addac/adi,ad74413r.yaml      | 158 ++++++++++++++++++
+ include/dt-bindings/iio/addac/adi,ad74413r.h  |  21 +++
+ 2 files changed, 179 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml
+ create mode 100644 include/dt-bindings/iio/addac/adi,ad74413r.h
+
+diff --git a/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml b/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml
+new file mode 100644
+index 0000000000000..baa65a521bad5
+--- /dev/null
++++ b/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml
+@@ -0,0 +1,158 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/iio/addac/adi,ad74413r.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Analog Devices AD74412R/AD74413R device
++
++maintainers:
++  - Cosmin Tanislav <cosmin.tanislav@analog.com>
++
++description: |
++  The AD74412R and AD74413R are quad-channel software configurable input/output
++  solutions for building and process control applications. They contain
++  functionality for analog output, analog input, digital input, resistance
++  temperature detector, and thermocouple measurements integrated
++  into a single chip solution with an SPI interface.
++  The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
++  four configurable input/output channels and a suite of diagnostic functions.
++  The AD74413R differentiates itself from the AD74412R by being HART-compatible.
++    https://www.analog.com/en/products/ad74412r.html
++    https://www.analog.com/en/products/ad74413r.html
++
++properties:
++  compatible:
++    enum:
++      - adi,ad74412r
++      - adi,ad74413r
++
++  reg:
++    maxItems: 1
++
++  '#address-cells':
++    const: 1
++
++  '#size-cells':
++    const: 0
++
++  spi-max-frequency:
++    maximum: 1000000
++
++  spi-cpol: true
++
++  interrupts:
++    maxItems: 1
++
++  refin-supply: true
++
++  shunt-resistor-micro-ohms:
++    description:
++      Shunt (sense) resistor value in micro-Ohms.
++    default: 100000000
++
++required:
++  - compatible
++  - reg
++  - spi-max-frequency
++  - spi-cpol
++  - refin-supply
++
++additionalProperties: false
++
++patternProperties:
++  "^channel@[0-3]$":
++    type: object
++    description: Represents the external channels which are connected to the device.
++
++    properties:
++      reg:
++        description: |
++          The channel number. It can have up to 4 channels numbered from 0 to 3.
++        minimum: 0
++        maximum: 3
++
++      adi,ch-func:
++        $ref: /schemas/types.yaml#/definitions/uint32
++        description: |
++          Channel function.
++          HART functions are not supported on AD74412R.
++          0 - CH_FUNC_HIGH_IMPEDANCE
++          1 - CH_FUNC_VOLTAGE_OUTPUT
++          2 - CH_FUNC_CURRENT_OUTPUT
++          3 - CH_FUNC_VOLTAGE_INPUT
++          4 - CH_FUNC_CURRENT_INPUT_EXT_POWER
++          5 - CH_FUNC_CURRENT_INPUT_LOOP_POWER
++          6 - CH_FUNC_RESISTANCE_INPUT
++          7 - CH_FUNC_DIGITAL_INPUT_LOGIC
++          8 - CH_FUNC_DIGITAL_INPUT_LOOP_POWER
++          9 - CH_FUNC_CURRENT_INPUT_EXT_POWER_HART
++          10 - CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART
++        minimum: 0
++        maximum: 10
++        default: 0
++
++      adi,gpo-comparator:
++        type: boolean
++        description: |
++          Whether to configure GPO as a comparator or not.
++          When not configured as a comparator, the GPO will be treated as an
++          output-only GPIO.
++
++    required:
++      - reg
++
++examples:
++  - |
++    #include <dt-bindings/gpio/gpio.h>
++    #include <dt-bindings/interrupt-controller/irq.h>
++    #include <dt-bindings/iio/addac/adi,ad74413r.h>
++
++    spi {
++      #address-cells = <1>;
++      #size-cells = <0>;
++
++      cs-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
++      status = "okay";
++
++      ad74413r@0 {
++        compatible = "adi,ad74413r";
++        reg = <0>;
++        spi-max-frequency = <1000000>;
++        spi-cpol;
++
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        interrupt-parent = <&gpio>;
++        interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
++
++        refin-supply = <&ad74413r_refin>;
++
++        channel@0 {
++          reg = <0>;
++
++          adi,ch-func = <CH_FUNC_VOLTAGE_OUTPUT>;
++        };
++
++        channel@1 {
++          reg = <1>;
++
++          adi,ch-func = <CH_FUNC_CURRENT_OUTPUT>;
++        };
++
++        channel@2 {
++          reg = <2>;
++
++          adi,ch-func = <CH_FUNC_DIGITAL_INPUT_LOGIC>;
++          adi,gpo-comparator;
++        };
++
++        channel@3 {
++          reg = <3>;
++
++          adi,ch-func = <CH_FUNC_CURRENT_INPUT_EXT_POWER>;
++        };
++      };
++    };
++...
+diff --git a/include/dt-bindings/iio/addac/adi,ad74413r.h b/include/dt-bindings/iio/addac/adi,ad74413r.h
+new file mode 100644
+index 0000000000000..204f92bbd79f2
+--- /dev/null
++++ b/include/dt-bindings/iio/addac/adi,ad74413r.h
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _DT_BINDINGS_ADI_AD74413R_H
++#define _DT_BINDINGS_ADI_AD74413R_H
++
++#define CH_FUNC_HIGH_IMPEDANCE                        0x0
++#define CH_FUNC_VOLTAGE_OUTPUT                        0x1
++#define CH_FUNC_CURRENT_OUTPUT                        0x2
++#define CH_FUNC_VOLTAGE_INPUT                 0x3
++#define CH_FUNC_CURRENT_INPUT_EXT_POWER               0x4
++#define CH_FUNC_CURRENT_INPUT_LOOP_POWER      0x5
++#define CH_FUNC_RESISTANCE_INPUT              0x6
++#define CH_FUNC_DIGITAL_INPUT_LOGIC           0x7
++#define CH_FUNC_DIGITAL_INPUT_LOOP_POWER      0x8
++#define CH_FUNC_CURRENT_INPUT_EXT_POWER_HART  0x9
++#define CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART 0xA
++
++#define CH_FUNC_MIN   CH_FUNC_HIGH_IMPEDANCE
++#define CH_FUNC_MAX   CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART
++
++#endif /* _DT_BINDINGS_ADI_AD74413R_H */
+-- 
+2.40.1
+

diff --git a/queue-5.10/fs-jfs-check-for-read-only-mounted-filesystem-in-txb.patch b/queue-5.10/fs-jfs-check-for-read-only-mounted-filesystem-in-txb.patch
new file mode 100644 (file)
index 0000000..abcd1b6
--- /dev/null
+++ b/queue-5.10/fs-jfs-check-for-read-only-mounted-filesystem-in-txb.patch
@@ -0,0 +1,39 @@
+From 4e807240df403ae65aac97a7493d924457df6d82 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 23 Jun 2023 19:17:08 +0530
+Subject: FS: JFS: Check for read-only mounted filesystem in txBegin
+
+From: Immad Mir <mirimmad17@gmail.com>
+
+[ Upstream commit 95e2b352c03b0a86c5717ba1d24ea20969abcacc ]
+
+ This patch adds a check for read-only mounted filesystem
+ in txBegin before starting a transaction potentially saving
+ from NULL pointer deref.
+
+Signed-off-by: Immad Mir <mirimmad17@gmail.com>
+Signed-off-by: Dave Kleikamp <dave.kleikamp@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/jfs/jfs_txnmgr.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/fs/jfs/jfs_txnmgr.c b/fs/jfs/jfs_txnmgr.c
+index c8ce7f1bc5942..6f6a5b9203d3f 100644
+--- a/fs/jfs/jfs_txnmgr.c
++++ b/fs/jfs/jfs_txnmgr.c
+@@ -354,6 +354,11 @@ tid_t txBegin(struct super_block *sb, int flag)
+       jfs_info("txBegin: flag = 0x%x", flag);
+       log = JFS_SBI(sb)->log;
+ 
++      if (!log) {
++              jfs_error(sb, "read-only filesystem\n");
++              return 0;
++      }
++
+       TXN_LOCK();
+ 
+       INCREMENT(TxStat.txBegin);
+-- 
+2.40.1
+

diff --git a/queue-5.10/fs-jfs-fix-null-ptr-deref-read-in-txbegin.patch b/queue-5.10/fs-jfs-fix-null-ptr-deref-read-in-txbegin.patch
new file mode 100644 (file)
index 0000000..c6cfcf9
--- /dev/null
+++ b/queue-5.10/fs-jfs-fix-null-ptr-deref-read-in-txbegin.patch
@@ -0,0 +1,44 @@
+From d076e91b9eb29fde5f976e34a4741dc1ef68087c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 23 Jun 2023 19:14:01 +0530
+Subject: FS: JFS: Fix null-ptr-deref Read in txBegin
+
+From: Immad Mir <mirimmad17@gmail.com>
+
+[ Upstream commit 47cfdc338d674d38f4b2f22b7612cc6a2763ba27 ]
+
+ Syzkaller reported an issue where txBegin may be called
+ on a superblock in a read-only mounted filesystem which leads
+ to NULL pointer deref. This could be solved by checking if
+ the filesystem is read-only before calling txBegin, and returning
+ with appropiate error code.
+
+Reported-By: syzbot+f1faa20eec55e0c8644c@syzkaller.appspotmail.com
+Link: https://syzkaller.appspot.com/bug?id=be7e52c50c5182cc09a09ea6fc456446b2039de3
+
+Signed-off-by: Immad Mir <mirimmad17@gmail.com>
+Signed-off-by: Dave Kleikamp <dave.kleikamp@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/jfs/namei.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/fs/jfs/namei.c b/fs/jfs/namei.c
+index 7a55d14cc1af0..f155ad6650bd4 100644
+--- a/fs/jfs/namei.c
++++ b/fs/jfs/namei.c
+@@ -798,6 +798,11 @@ static int jfs_link(struct dentry *old_dentry,
+       if (rc)
+               goto out;
+ 
++      if (isReadOnly(ip)) {
++              jfs_error(ip->i_sb, "read-only filesystem\n");
++              return -EROFS;
++      }
++
+       tid = txBegin(ip->i_sb, 0);
+ 
+       mutex_lock_nested(&JFS_IP(dir)->commit_mutex, COMMIT_MUTEX_PARENT);
+-- 
+2.40.1
+

diff --git a/queue-5.10/fs-jfs-fix-ubsan-array-index-out-of-bounds-in-dballo.patch b/queue-5.10/fs-jfs-fix-ubsan-array-index-out-of-bounds-in-dballo.patch
new file mode 100644 (file)
index 0000000..578fae2
--- /dev/null
+++ b/queue-5.10/fs-jfs-fix-ubsan-array-index-out-of-bounds-in-dballo.patch
@@ -0,0 +1,86 @@
+From cf34508388f6571ac3f249608f177e571dc42da3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Jun 2023 00:07:03 +0530
+Subject: fs: jfs: Fix UBSAN: array-index-out-of-bounds in dbAllocDmapLev
+
+From: Yogesh <yogi.kernel@gmail.com>
+
+[ Upstream commit 4e302336d5ca1767a06beee7596a72d3bdc8d983 ]
+
+Syzkaller reported the following issue:
+
+UBSAN: array-index-out-of-bounds in fs/jfs/jfs_dmap.c:1965:6
+index -84 is out of range for type 's8[341]' (aka 'signed char[341]')
+CPU: 1 PID: 4995 Comm: syz-executor146 Not tainted 6.4.0-rc6-syzkaller-00037-gb6dad5178cea #0
+Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 05/27/2023
+Call Trace:
+ <TASK>
+ __dump_stack lib/dump_stack.c:88 [inline]
+ dump_stack_lvl+0x1e7/0x2d0 lib/dump_stack.c:106
+ ubsan_epilogue lib/ubsan.c:217 [inline]
+ __ubsan_handle_out_of_bounds+0x11c/0x150 lib/ubsan.c:348
+ dbAllocDmapLev+0x3e5/0x430 fs/jfs/jfs_dmap.c:1965
+ dbAllocCtl+0x113/0x920 fs/jfs/jfs_dmap.c:1809
+ dbAllocAG+0x28f/0x10b0 fs/jfs/jfs_dmap.c:1350
+ dbAlloc+0x658/0xca0 fs/jfs/jfs_dmap.c:874
+ dtSplitUp fs/jfs/jfs_dtree.c:974 [inline]
+ dtInsert+0xda7/0x6b00 fs/jfs/jfs_dtree.c:863
+ jfs_create+0x7b6/0xbb0 fs/jfs/namei.c:137
+ lookup_open fs/namei.c:3492 [inline]
+ open_last_lookups fs/namei.c:3560 [inline]
+ path_openat+0x13df/0x3170 fs/namei.c:3788
+ do_filp_open+0x234/0x490 fs/namei.c:3818
+ do_sys_openat2+0x13f/0x500 fs/open.c:1356
+ do_sys_open fs/open.c:1372 [inline]
+ __do_sys_openat fs/open.c:1388 [inline]
+ __se_sys_openat fs/open.c:1383 [inline]
+ __x64_sys_openat+0x247/0x290 fs/open.c:1383
+ do_syscall_x64 arch/x86/entry/common.c:50 [inline]
+ do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
+ entry_SYSCALL_64_after_hwframe+0x63/0xcd
+RIP: 0033:0x7f1f4e33f7e9
+Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 51 14 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 c0 ff ff ff f7 d8 64 89 01 48
+RSP: 002b:00007ffc21129578 EFLAGS: 00000246 ORIG_RAX: 0000000000000101
+RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f1f4e33f7e9
+RDX: 000000000000275a RSI: 0000000020000040 RDI: 00000000ffffff9c
+RBP: 00007f1f4e2ff080 R08: 0000000000000000 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000246 R12: 00007f1f4e2ff110
+R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000
+ </TASK>
+
+The bug occurs when the dbAllocDmapLev()function attempts to access
+dp->tree.stree[leafidx + LEAFIND] while the leafidx value is negative.
+
+To rectify this, the patch introduces a safeguard within the
+dbAllocDmapLev() function. A check has been added to verify if leafidx is
+negative. If it is, the function immediately returns an I/O error, preventing
+any further execution that could potentially cause harm.
+
+Tested via syzbot.
+
+Reported-by: syzbot+853a6f4dfa3cf37d3aea@syzkaller.appspotmail.com
+Link: https://syzkaller.appspot.com/bug?extid=ae2f5a27a07ae44b0f17
+Signed-off-by: Yogesh <yogi.kernel@gmail.com>
+Signed-off-by: Dave Kleikamp <dave.kleikamp@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/jfs/jfs_dmap.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c
+index bd9af2be352fc..cef3303d94995 100644
+--- a/fs/jfs/jfs_dmap.c
++++ b/fs/jfs/jfs_dmap.c
+@@ -2027,6 +2027,9 @@ dbAllocDmapLev(struct bmap * bmp,
+       if (dbFindLeaf((dmtree_t *) & dp->tree, l2nb, &leafidx))
+               return -ENOSPC;
+ 
++      if (leafidx < 0)
++              return -EIO;
++
+       /* determine the block number within the file system corresponding
+        * to the leaf at which free space was found.
+        */
+-- 
+2.40.1
+

diff --git a/queue-5.10/gfs2-fix-possible-data-races-in-gfs2_show_options.patch b/queue-5.10/gfs2-fix-possible-data-races-in-gfs2_show_options.patch
new file mode 100644 (file)
index 0000000..768ebc2
--- /dev/null
+++ b/queue-5.10/gfs2-fix-possible-data-races-in-gfs2_show_options.patch
@@ -0,0 +1,86 @@
+From ef11a950fc485d0ef408f91e078339d9ef329167 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Jun 2023 11:06:37 +0800
+Subject: gfs2: Fix possible data races in gfs2_show_options()
+
+From: Tuo Li <islituo@gmail.com>
+
+[ Upstream commit 6fa0a72cbbe45db4ed967a51f9e6f4e3afe61d20 ]
+
+Some fields such as gt_logd_secs of the struct gfs2_tune are accessed
+without holding the lock gt_spin in gfs2_show_options():
+
+  val = sdp->sd_tune.gt_logd_secs;
+  if (val != 30)
+    seq_printf(s, ",commit=%d", val);
+
+And thus can cause data races when gfs2_show_options() and other functions
+such as gfs2_reconfigure() are concurrently executed:
+
+  spin_lock(&gt->gt_spin);
+  gt->gt_logd_secs = newargs->ar_commit;
+
+To fix these possible data races, the lock sdp->sd_tune.gt_spin is
+acquired before accessing the fields of gfs2_tune and released after these
+accesses.
+
+Further changes by Andreas:
+
+- Don't hold the spin lock over the seq_printf operations.
+
+Reported-by: BassCheck <bass@buaa.edu.cn>
+Signed-off-by: Tuo Li <islituo@gmail.com>
+Signed-off-by: Andreas Gruenbacher <agruenba@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/gfs2/super.c | 26 +++++++++++++++-----------
+ 1 file changed, 15 insertions(+), 11 deletions(-)
+
+diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c
+index e01b6a2d12d30..b61de8dab51a0 100644
+--- a/fs/gfs2/super.c
++++ b/fs/gfs2/super.c
+@@ -1017,7 +1017,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root)
+ {
+       struct gfs2_sbd *sdp = root->d_sb->s_fs_info;
+       struct gfs2_args *args = &sdp->sd_args;
+-      int val;
++      unsigned int logd_secs, statfs_slow, statfs_quantum, quota_quantum;
++
++      spin_lock(&sdp->sd_tune.gt_spin);
++      logd_secs = sdp->sd_tune.gt_logd_secs;
++      quota_quantum = sdp->sd_tune.gt_quota_quantum;
++      statfs_quantum = sdp->sd_tune.gt_statfs_quantum;
++      statfs_slow = sdp->sd_tune.gt_statfs_slow;
++      spin_unlock(&sdp->sd_tune.gt_spin);
+ 
+       if (is_ancestor(root, sdp->sd_master_dir))
+               seq_puts(s, ",meta");
+@@ -1072,17 +1079,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root)
+       }
+       if (args->ar_discard)
+               seq_puts(s, ",discard");
+-      val = sdp->sd_tune.gt_logd_secs;
+-      if (val != 30)
+-              seq_printf(s, ",commit=%d", val);
+-      val = sdp->sd_tune.gt_statfs_quantum;
+-      if (val != 30)
+-              seq_printf(s, ",statfs_quantum=%d", val);
+-      else if (sdp->sd_tune.gt_statfs_slow)
++      if (logd_secs != 30)
++              seq_printf(s, ",commit=%d", logd_secs);
++      if (statfs_quantum != 30)
++              seq_printf(s, ",statfs_quantum=%d", statfs_quantum);
++      else if (statfs_slow)
+               seq_puts(s, ",statfs_quantum=0");
+-      val = sdp->sd_tune.gt_quota_quantum;
+-      if (val != 60)
+-              seq_printf(s, ",quota_quantum=%d", val);
++      if (quota_quantum != 60)
++              seq_printf(s, ",quota_quantum=%d", quota_quantum);
+       if (args->ar_statfs_percent)
+               seq_printf(s, ",statfs_percent=%d", args->ar_statfs_percent);
+       if (args->ar_errors != GFS2_ERRORS_DEFAULT) {
+-- 
+2.40.1
+

diff --git a/queue-5.10/hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch b/queue-5.10/hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch
new file mode 100644 (file)
index 0000000..3ec7763
--- /dev/null
+++ b/queue-5.10/hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch
@@ -0,0 +1,54 @@
+From 8cbdac005d3c61f033065d6d65844947739377a6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 May 2023 15:40:08 +0200
+Subject: HID: add quirk for 03f0:464a HP Elite Presenter Mouse
+
+From: Marco Morandini <marco.morandini@polimi.it>
+
+[ Upstream commit 0db117359e47750d8bd310d19f13e1c4ef7fc26a ]
+
+HP Elite Presenter Mouse HID Record Descriptor shows
+two mouses (Repord ID 0x1 and 0x2), one keypad (Report ID 0x5),
+two Consumer Controls (Report IDs 0x6 and 0x3).
+Previous to this commit it registers one mouse, one keypad
+and one Consumer Control, and it was usable only as a
+digitl laser pointer (one of the two mouses). This patch defines
+the 464a USB device ID and enables the HID_QUIRK_MULTI_INPUT
+quirk for it, allowing to use the device both as a mouse
+and a digital laser pointer.
+
+Signed-off-by: Marco Morandini <marco.morandini@polimi.it>
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hid/hid-ids.h    | 1 +
+ drivers/hid/hid-quirks.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
+index 2b658d820b800..6712d99ad80da 100644
+--- a/drivers/hid/hid-ids.h
++++ b/drivers/hid/hid-ids.h
+@@ -582,6 +582,7 @@
+ #define USB_DEVICE_ID_UGCI_FIGHTING   0x0030
+ 
+ #define USB_VENDOR_ID_HP              0x03f0
++#define USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A          0x464a
+ #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A 0x0a4a
+ #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A 0x0b4a
+ #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE                0x134a
+diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c
+index 9f1fcbea19eb7..4229e5de06745 100644
+--- a/drivers/hid/hid-quirks.c
++++ b/drivers/hid/hid-quirks.c
+@@ -96,6 +96,7 @@ static const struct hid_device_id hid_quirks[] = {
+       { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A096), HID_QUIRK_NO_INIT_REPORTS },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A293), HID_QUIRK_ALWAYS_POLL },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A), HID_QUIRK_ALWAYS_POLL },
++      { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A), HID_QUIRK_MULTI_INPUT },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A), HID_QUIRK_ALWAYS_POLL },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL },
+       { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A), HID_QUIRK_ALWAYS_POLL },
+-- 
+2.40.1
+

diff --git a/queue-5.10/iio-adc-stx104-implement-and-utilize-register-struct.patch b/queue-5.10/iio-adc-stx104-implement-and-utilize-register-struct.patch
new file mode 100644 (file)
index 0000000..0483ad0
--- /dev/null
+++ b/queue-5.10/iio-adc-stx104-implement-and-utilize-register-struct.patch
@@ -0,0 +1,213 @@
+From 3c0f1937fcd04b78f44458d766cf28675fa9082b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Jul 2022 13:21:24 -0400
+Subject: iio: adc: stx104: Implement and utilize register structures
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 6cfd14c54b1f42f29097244c1b6208f8268d7d5b ]
+
+Reduce magic numbers and improve code readability by implementing and
+utilizing named register data structures.
+
+Tested-by: Fred Eckert <Frede@cmslaser.com>
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Link: https://lore.kernel.org/r/8cb91d5b53e57b066120e42ea07000d6c7ef5543.1657213745.git.william.gray@linaro.org
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/stx104.c | 74 +++++++++++++++++++++++++++-------------
+ 1 file changed, 50 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c
+index 7552351bfed9e..48a91a95e597b 100644
+--- a/drivers/iio/adc/stx104.c
++++ b/drivers/iio/adc/stx104.c
+@@ -16,6 +16,7 @@
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
+ #include <linux/spinlock.h>
++#include <linux/types.h>
+ 
+ #define STX104_OUT_CHAN(chan) {                               \
+       .type = IIO_VOLTAGE,                            \
+@@ -44,14 +45,36 @@ static unsigned int num_stx104;
+ module_param_hw_array(base, uint, ioport, &num_stx104, 0);
+ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
+ 
++/**
++ * struct stx104_reg - device register structure
++ * @ssr_ad:   Software Strobe Register and ADC Data
++ * @achan:    ADC Channel
++ * @dio:      Digital I/O
++ * @dac:      DAC Channels
++ * @cir_asr:  Clear Interrupts and ADC Status
++ * @acr:      ADC Control
++ * @pccr_fsh: Pacer Clock Control and FIFO Status MSB
++ * @acfg:     ADC Configuration
++ */
++struct stx104_reg {
++      u16 ssr_ad;
++      u8 achan;
++      u8 dio;
++      u16 dac[2];
++      u8 cir_asr;
++      u8 acr;
++      u8 pccr_fsh;
++      u8 acfg;
++};
++
+ /**
+  * struct stx104_iio - IIO device private data structure
+  * @chan_out_states:  channels' output states
+- * @base:             base port address of the IIO device
++ * @reg:              I/O address offset for the device registers
+  */
+ struct stx104_iio {
+       unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
+-      void __iomem *base;
++      struct stx104_reg __iomem *reg;
+ };
+ 
+ /**
+@@ -64,7 +87,7 @@ struct stx104_iio {
+ struct stx104_gpio {
+       struct gpio_chip chip;
+       spinlock_t lock;
+-      void __iomem *base;
++      u8 __iomem *base;
+       unsigned int out_state;
+ };
+ 
+@@ -72,6 +95,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+       struct iio_chan_spec const *chan, int *val, int *val2, long mask)
+ {
+       struct stx104_iio *const priv = iio_priv(indio_dev);
++      struct stx104_reg __iomem *const reg = priv->reg;
+       unsigned int adc_config;
+       int adbu;
+       int gain;
+@@ -79,7 +103,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+       switch (mask) {
+       case IIO_CHAN_INFO_HARDWAREGAIN:
+               /* get gain configuration */
+-              adc_config = ioread8(priv->base + 11);
++              adc_config = ioread8(&reg->acfg);
+               gain = adc_config & 0x3;
+ 
+               *val = 1 << gain;
+@@ -91,24 +115,26 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+               }
+ 
+               /* select ADC channel */
+-              iowrite8(chan->channel | (chan->channel << 4), priv->base + 2);
++              iowrite8(chan->channel | (chan->channel << 4), &reg->achan);
+ 
+-              /* trigger ADC sample capture and wait for completion */
+-              iowrite8(0, priv->base);
+-              while (ioread8(priv->base + 8) & BIT(7));
++              /* trigger ADC sample capture by writing to the 8-bit
++               * Software Strobe Register and wait for completion
++               */
++              iowrite8(0, &reg->ssr_ad);
++              while (ioread8(&reg->cir_asr) & BIT(7));
+ 
+-              *val = ioread16(priv->base);
++              *val = ioread16(&reg->ssr_ad);
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_OFFSET:
+               /* get ADC bipolar/unipolar configuration */
+-              adc_config = ioread8(priv->base + 11);
++              adc_config = ioread8(&reg->acfg);
+               adbu = !(adc_config & BIT(2));
+ 
+               *val = -32768 * adbu;
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_SCALE:
+               /* get ADC bipolar/unipolar and gain configuration */
+-              adc_config = ioread8(priv->base + 11);
++              adc_config = ioread8(&reg->acfg);
+               adbu = !(adc_config & BIT(2));
+               gain = adc_config & 0x3;
+ 
+@@ -130,16 +156,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+               /* Only four gain states (x1, x2, x4, x8) */
+               switch (val) {
+               case 1:
+-                      iowrite8(0, priv->base + 11);
++                      iowrite8(0, &priv->reg->acfg);
+                       break;
+               case 2:
+-                      iowrite8(1, priv->base + 11);
++                      iowrite8(1, &priv->reg->acfg);
+                       break;
+               case 4:
+-                      iowrite8(2, priv->base + 11);
++                      iowrite8(2, &priv->reg->acfg);
+                       break;
+               case 8:
+-                      iowrite8(3, priv->base + 11);
++                      iowrite8(3, &priv->reg->acfg);
+                       break;
+               default:
+                       return -EINVAL;
+@@ -153,7 +179,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+                               return -EINVAL;
+ 
+                       priv->chan_out_states[chan->channel] = val;
+-                      iowrite16(val, priv->base + 4 + 2 * chan->channel);
++                      iowrite16(val, &priv->reg->dac[chan->channel]);
+ 
+                       return 0;
+               }
+@@ -307,15 +333,15 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       }
+ 
+       priv = iio_priv(indio_dev);
+-      priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT);
+-      if (!priv->base)
++      priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT);
++      if (!priv->reg)
+               return -ENOMEM;
+ 
+       indio_dev->info = &stx104_info;
+       indio_dev->modes = INDIO_DIRECT_MODE;
+ 
+       /* determine if differential inputs */
+-      if (ioread8(priv->base + 8) & BIT(5)) {
++      if (ioread8(&priv->reg->cir_asr) & BIT(5)) {
+               indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
+               indio_dev->channels = stx104_channels_diff;
+       } else {
+@@ -326,14 +352,14 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       indio_dev->name = dev_name(dev);
+ 
+       /* configure device for software trigger operation */
+-      iowrite8(0, priv->base + 9);
++      iowrite8(0, &priv->reg->acr);
+ 
+       /* initialize gain setting to x1 */
+-      iowrite8(0, priv->base + 11);
++      iowrite8(0, &priv->reg->acfg);
+ 
+       /* initialize DAC output to 0V */
+-      iowrite16(0, priv->base + 4);
+-      iowrite16(0, priv->base + 6);
++      iowrite16(0, &priv->reg->dac[0]);
++      iowrite16(0, &priv->reg->dac[1]);
+ 
+       stx104gpio->chip.label = dev_name(dev);
+       stx104gpio->chip.parent = dev;
+@@ -348,7 +374,7 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
+       stx104gpio->chip.set = stx104_gpio_set;
+       stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
+-      stx104gpio->base = priv->base + 3;
++      stx104gpio->base = &priv->reg->dio;
+       stx104gpio->out_state = 0x0;
+ 
+       spin_lock_init(&stx104gpio->lock);
+-- 
+2.40.1
+

diff --git a/queue-5.10/iio-adc-stx104-utilize-iomap-interface.patch b/queue-5.10/iio-adc-stx104-utilize-iomap-interface.patch
new file mode 100644 (file)
index 0000000..864d986
--- /dev/null
+++ b/queue-5.10/iio-adc-stx104-utilize-iomap-interface.patch
@@ -0,0 +1,206 @@
+From bca246c1c5b4ce057f13072a54fb3ebf93e88e87 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 10 May 2022 13:30:59 -0400
+Subject: iio: adc: stx104: Utilize iomap interface
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 73b8390cc27e096ab157be261ccc4eaaa6db87af ]
+
+This driver doesn't need to access I/O ports directly via inb()/outb()
+and friends. This patch abstracts such access by calling ioport_map()
+to enable the use of more typical ioread8()/iowrite8() I/O memory
+accessor calls.
+
+Suggested-by: David Laight <David.Laight@ACULAB.COM>
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/64673797df382c52fc32fce24348b25a0b05e73a.1652201921.git.william.gray@linaro.org
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/stx104.c | 56 +++++++++++++++++++++-------------------
+ 1 file changed, 29 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c
+index 55bd2dc514e93..7552351bfed9e 100644
+--- a/drivers/iio/adc/stx104.c
++++ b/drivers/iio/adc/stx104.c
+@@ -51,7 +51,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
+  */
+ struct stx104_iio {
+       unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
+-      unsigned int base;
++      void __iomem *base;
+ };
+ 
+ /**
+@@ -64,7 +64,7 @@ struct stx104_iio {
+ struct stx104_gpio {
+       struct gpio_chip chip;
+       spinlock_t lock;
+-      unsigned int base;
++      void __iomem *base;
+       unsigned int out_state;
+ };
+ 
+@@ -79,7 +79,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+       switch (mask) {
+       case IIO_CHAN_INFO_HARDWAREGAIN:
+               /* get gain configuration */
+-              adc_config = inb(priv->base + 11);
++              adc_config = ioread8(priv->base + 11);
+               gain = adc_config & 0x3;
+ 
+               *val = 1 << gain;
+@@ -91,24 +91,24 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+               }
+ 
+               /* select ADC channel */
+-              outb(chan->channel | (chan->channel << 4), priv->base + 2);
++              iowrite8(chan->channel | (chan->channel << 4), priv->base + 2);
+ 
+               /* trigger ADC sample capture and wait for completion */
+-              outb(0, priv->base);
+-              while (inb(priv->base + 8) & BIT(7));
++              iowrite8(0, priv->base);
++              while (ioread8(priv->base + 8) & BIT(7));
+ 
+-              *val = inw(priv->base);
++              *val = ioread16(priv->base);
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_OFFSET:
+               /* get ADC bipolar/unipolar configuration */
+-              adc_config = inb(priv->base + 11);
++              adc_config = ioread8(priv->base + 11);
+               adbu = !(adc_config & BIT(2));
+ 
+               *val = -32768 * adbu;
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_SCALE:
+               /* get ADC bipolar/unipolar and gain configuration */
+-              adc_config = inb(priv->base + 11);
++              adc_config = ioread8(priv->base + 11);
+               adbu = !(adc_config & BIT(2));
+               gain = adc_config & 0x3;
+ 
+@@ -130,16 +130,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+               /* Only four gain states (x1, x2, x4, x8) */
+               switch (val) {
+               case 1:
+-                      outb(0, priv->base + 11);
++                      iowrite8(0, priv->base + 11);
+                       break;
+               case 2:
+-                      outb(1, priv->base + 11);
++                      iowrite8(1, priv->base + 11);
+                       break;
+               case 4:
+-                      outb(2, priv->base + 11);
++                      iowrite8(2, priv->base + 11);
+                       break;
+               case 8:
+-                      outb(3, priv->base + 11);
++                      iowrite8(3, priv->base + 11);
+                       break;
+               default:
+                       return -EINVAL;
+@@ -153,7 +153,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+                               return -EINVAL;
+ 
+                       priv->chan_out_states[chan->channel] = val;
+-                      outw(val, priv->base + 4 + 2 * chan->channel);
++                      iowrite16(val, priv->base + 4 + 2 * chan->channel);
+ 
+                       return 0;
+               }
+@@ -222,7 +222,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset)
+       if (offset >= 4)
+               return -EINVAL;
+ 
+-      return !!(inb(stx104gpio->base) & BIT(offset));
++      return !!(ioread8(stx104gpio->base) & BIT(offset));
+ }
+ 
+ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
+@@ -230,7 +230,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
+ {
+       struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
+ 
+-      *bits = inb(stx104gpio->base);
++      *bits = ioread8(stx104gpio->base);
+ 
+       return 0;
+ }
+@@ -252,7 +252,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset,
+       else
+               stx104gpio->out_state &= ~mask;
+ 
+-      outb(stx104gpio->out_state, stx104gpio->base);
++      iowrite8(stx104gpio->out_state, stx104gpio->base);
+ 
+       spin_unlock_irqrestore(&stx104gpio->lock, flags);
+ }
+@@ -279,7 +279,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *chip,
+ 
+       stx104gpio->out_state &= ~*mask;
+       stx104gpio->out_state |= *mask & *bits;
+-      outb(stx104gpio->out_state, stx104gpio->base);
++      iowrite8(stx104gpio->out_state, stx104gpio->base);
+ 
+       spin_unlock_irqrestore(&stx104gpio->lock, flags);
+ }
+@@ -306,11 +306,16 @@ static int stx104_probe(struct device *dev, unsigned int id)
+               return -EBUSY;
+       }
+ 
++      priv = iio_priv(indio_dev);
++      priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT);
++      if (!priv->base)
++              return -ENOMEM;
++
+       indio_dev->info = &stx104_info;
+       indio_dev->modes = INDIO_DIRECT_MODE;
+ 
+       /* determine if differential inputs */
+-      if (inb(base[id] + 8) & BIT(5)) {
++      if (ioread8(priv->base + 8) & BIT(5)) {
+               indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
+               indio_dev->channels = stx104_channels_diff;
+       } else {
+@@ -320,18 +325,15 @@ static int stx104_probe(struct device *dev, unsigned int id)
+ 
+       indio_dev->name = dev_name(dev);
+ 
+-      priv = iio_priv(indio_dev);
+-      priv->base = base[id];
+-
+       /* configure device for software trigger operation */
+-      outb(0, base[id] + 9);
++      iowrite8(0, priv->base + 9);
+ 
+       /* initialize gain setting to x1 */
+-      outb(0, base[id] + 11);
++      iowrite8(0, priv->base + 11);
+ 
+       /* initialize DAC output to 0V */
+-      outw(0, base[id] + 4);
+-      outw(0, base[id] + 6);
++      iowrite16(0, priv->base + 4);
++      iowrite16(0, priv->base + 6);
+ 
+       stx104gpio->chip.label = dev_name(dev);
+       stx104gpio->chip.parent = dev;
+@@ -346,7 +348,7 @@ static int stx104_probe(struct device *dev, unsigned int id)
+       stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
+       stx104gpio->chip.set = stx104_gpio_set;
+       stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
+-      stx104gpio->base = base[id] + 3;
++      stx104gpio->base = priv->base + 3;
+       stx104gpio->out_state = 0x0;
+ 
+       spin_lock_init(&stx104gpio->lock);
+-- 
+2.40.1
+

diff --git a/queue-5.10/iio-add-addac-subdirectory.patch b/queue-5.10/iio-add-addac-subdirectory.patch
new file mode 100644 (file)
index 0000000..1f41f2a
--- /dev/null
+++ b/queue-5.10/iio-add-addac-subdirectory.patch
@@ -0,0 +1,78 @@
+From 13eab8bd312e78f05a00031e85233b0d5fdbe405 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 5 Dec 2021 13:40:43 +0200
+Subject: iio: add addac subdirectory
+
+From: Cosmin Tanislav <demonsingur@gmail.com>
+
+[ Upstream commit b62e2e1763cda3a6c494ed754317f19be1249297 ]
+
+For IIO devices that expose both ADC and DAC functionality.
+
+Signed-off-by: Cosmin Tanislav <cosmin.tanislav@analog.com>
+Link: https://lore.kernel.org/r/20211205114045.173612-2-cosmin.tanislav@analog.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/Kconfig        | 1 +
+ drivers/iio/Makefile       | 1 +
+ drivers/iio/addac/Kconfig  | 8 ++++++++
+ drivers/iio/addac/Makefile | 6 ++++++
+ 4 files changed, 16 insertions(+)
+ create mode 100644 drivers/iio/addac/Kconfig
+ create mode 100644 drivers/iio/addac/Makefile
+
+diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
+index 267553386c710..2ed303aa7de3c 100644
+--- a/drivers/iio/Kconfig
++++ b/drivers/iio/Kconfig
+@@ -70,6 +70,7 @@ config IIO_TRIGGERED_EVENT
+ 
+ source "drivers/iio/accel/Kconfig"
+ source "drivers/iio/adc/Kconfig"
++source "drivers/iio/addac/Kconfig"
+ source "drivers/iio/afe/Kconfig"
+ source "drivers/iio/amplifiers/Kconfig"
+ source "drivers/iio/chemical/Kconfig"
+diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
+index 1712011c0f4a1..d6690e449ccec 100644
+--- a/drivers/iio/Makefile
++++ b/drivers/iio/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_IIO_TRIGGERED_EVENT) += industrialio-triggered-event.o
+ 
+ obj-y += accel/
+ obj-y += adc/
++obj-y += addac/
+ obj-y += afe/
+ obj-y += amplifiers/
+ obj-y += buffer/
+diff --git a/drivers/iio/addac/Kconfig b/drivers/iio/addac/Kconfig
+new file mode 100644
+index 0000000000000..2e64d7755d5ea
+--- /dev/null
++++ b/drivers/iio/addac/Kconfig
+@@ -0,0 +1,8 @@
++#
++# ADC DAC drivers
++#
++# When adding new entries keep the list in alphabetical order
++
++menu "Analog to digital and digital to analog converters"
++
++endmenu
+diff --git a/drivers/iio/addac/Makefile b/drivers/iio/addac/Makefile
+new file mode 100644
+index 0000000000000..b888b9ee12da0
+--- /dev/null
++++ b/drivers/iio/addac/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# Makefile for industrial I/O ADDAC drivers
++#
++
++# When adding new entries keep the list in alphabetical order
+-- 
+2.40.1
+

diff --git a/queue-5.10/iio-addac-stx104-fix-race-condition-for-stx104_write.patch b/queue-5.10/iio-addac-stx104-fix-race-condition-for-stx104_write.patch
new file mode 100644 (file)
index 0000000..d2a654b
--- /dev/null
+++ b/queue-5.10/iio-addac-stx104-fix-race-condition-for-stx104_write.patch
@@ -0,0 +1,74 @@
+From ac52cac8fb5b1e1c5cd478c96398f71c2d8df53d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Apr 2023 10:40:10 -0400
+Subject: iio: addac: stx104: Fix race condition for stx104_write_raw()
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 9740827468cea80c42db29e7171a50e99acf7328 ]
+
+The priv->chan_out_states array and actual DAC value can become
+mismatched if stx104_write_raw() is called concurrently. Prevent such a
+race condition by utilizing a mutex.
+
+Fixes: 97a445dad37a ("iio: Add IIO support for the DAC on the Apex Embedded Systems STX104")
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Link: https://lore.kernel.org/r/c95c9a77fcef36b2a052282146950f23bbc1ebdc.1680790580.git.william.gray@linaro.org
+Cc: <Stable@vger.kernel.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/stx104.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c
+index 48a91a95e597b..e110a910235ff 100644
+--- a/drivers/iio/adc/stx104.c
++++ b/drivers/iio/adc/stx104.c
+@@ -15,6 +15,7 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
++#include <linux/mutex.h>
+ #include <linux/spinlock.h>
+ #include <linux/types.h>
+ 
+@@ -69,10 +70,12 @@ struct stx104_reg {
+ 
+ /**
+  * struct stx104_iio - IIO device private data structure
++ * @lock: synchronization lock to prevent I/O race conditions
+  * @chan_out_states:  channels' output states
+  * @reg:              I/O address offset for the device registers
+  */
+ struct stx104_iio {
++      struct mutex lock;
+       unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
+       struct stx104_reg __iomem *reg;
+ };
+@@ -178,9 +181,12 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
+                       if ((unsigned int)val > 65535)
+                               return -EINVAL;
+ 
++                      mutex_lock(&priv->lock);
++
+                       priv->chan_out_states[chan->channel] = val;
+                       iowrite16(val, &priv->reg->dac[chan->channel]);
+ 
++                      mutex_unlock(&priv->lock);
+                       return 0;
+               }
+               return -EINVAL;
+@@ -351,6 +357,8 @@ static int stx104_probe(struct device *dev, unsigned int id)
+ 
+       indio_dev->name = dev_name(dev);
+ 
++      mutex_init(&priv->lock);
++
+       /* configure device for software trigger operation */
+       iowrite8(0, &priv->reg->acr);
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/iio-addac-stx104-fix-race-condition-when-converting-.patch b/queue-5.10/iio-addac-stx104-fix-race-condition-when-converting-.patch
new file mode 100644 (file)
index 0000000..d740ffa
--- /dev/null
+++ b/queue-5.10/iio-addac-stx104-fix-race-condition-when-converting-.patch
@@ -0,0 +1,50 @@
+From 026ba2fd0ed8ecf992b77ab9abfdd0d47f6e805a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Apr 2023 10:40:11 -0400
+Subject: iio: addac: stx104: Fix race condition when converting
+ analog-to-digital
+
+From: William Breathitt Gray <william.gray@linaro.org>
+
+[ Upstream commit 4f9b80aefb9e2f542a49d9ec087cf5919730e1dd ]
+
+The ADC conversion procedure requires several device I/O operations
+performed in a particular sequence. If stx104_read_raw() is called
+concurrently, the ADC conversion procedure could be clobbered. Prevent
+such a race condition by utilizing a mutex.
+
+Fixes: 4075a283ae83 ("iio: stx104: Add IIO support for the ADC channels")
+Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
+Link: https://lore.kernel.org/r/2ae5e40eed5006ca735e4c12181a9ff5ced65547.1680790580.git.william.gray@linaro.org
+Cc: <Stable@vger.kernel.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/stx104.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c
+index e110a910235ff..b658a75d4e3a8 100644
+--- a/drivers/iio/adc/stx104.c
++++ b/drivers/iio/adc/stx104.c
+@@ -117,6 +117,8 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+                       return IIO_VAL_INT;
+               }
+ 
++              mutex_lock(&priv->lock);
++
+               /* select ADC channel */
+               iowrite8(chan->channel | (chan->channel << 4), &reg->achan);
+ 
+@@ -127,6 +129,8 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
+               while (ioread8(&reg->cir_asr) & BIT(7));
+ 
+               *val = ioread16(&reg->ssr_ad);
++
++              mutex_unlock(&priv->lock);
+               return IIO_VAL_INT;
+       case IIO_CHAN_INFO_OFFSET:
+               /* get ADC bipolar/unipolar configuration */
+-- 
+2.40.1
+

diff --git a/queue-5.10/ima-allow-fix-uml-builds.patch b/queue-5.10/ima-allow-fix-uml-builds.patch
new file mode 100644 (file)
index 0000000..f2959b9
--- /dev/null
+++ b/queue-5.10/ima-allow-fix-uml-builds.patch
@@ -0,0 +1,56 @@
+From c459c9aca115ec9e44080447ae50c184ca251e20 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 23 Feb 2023 19:27:03 -0800
+Subject: IMA: allow/fix UML builds
+
+From: Randy Dunlap <rdunlap@infradead.org>
+
+[ Upstream commit 644f17412f5acf01a19af9d04a921937a2bc86c6 ]
+
+UML supports HAS_IOMEM since 0bbadafdc49d (um: allow disabling
+NO_IOMEM).
+
+Current IMA build on UML fails on allmodconfig (with TCG_TPM=m):
+
+ld: security/integrity/ima/ima_queue.o: in function `ima_add_template_entry':
+ima_queue.c:(.text+0x2d9): undefined reference to `tpm_pcr_extend'
+ld: security/integrity/ima/ima_init.o: in function `ima_init':
+ima_init.c:(.init.text+0x43f): undefined reference to `tpm_default_chip'
+ld: security/integrity/ima/ima_crypto.o: in function `ima_calc_boot_aggregate_tfm':
+ima_crypto.c:(.text+0x1044): undefined reference to `tpm_pcr_read'
+ld: ima_crypto.c:(.text+0x10d8): undefined reference to `tpm_pcr_read'
+
+Modify the IMA Kconfig entry so that it selects TCG_TPM if HAS_IOMEM
+is set, regardless of the UML Kconfig setting.
+This updates TCG_TPM from =m to =y and fixes the linker errors.
+
+Fixes: f4a0391dfa91 ("ima: fix Kconfig dependencies")
+Cc: Stable <stable@vger.kernel.org> # v5.14+
+Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
+Cc: Fabio Estevam <festevam@gmail.com>
+Cc: Richard Weinberger <richard@nod.at>
+Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com>
+Cc: Johannes Berg <johannes@sipsolutions.net>
+Cc: linux-um@lists.infradead.org
+Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ security/integrity/ima/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/security/integrity/ima/Kconfig b/security/integrity/ima/Kconfig
+index 755af0b29e755..0a5ae1e8da47a 100644
+--- a/security/integrity/ima/Kconfig
++++ b/security/integrity/ima/Kconfig
+@@ -8,7 +8,7 @@ config IMA
+       select CRYPTO_HMAC
+       select CRYPTO_SHA1
+       select CRYPTO_HASH_INFO
+-      select TCG_TPM if HAS_IOMEM && !UML
++      select TCG_TPM if HAS_IOMEM
+       select TCG_TIS if TCG_TPM && X86
+       select TCG_CRB if TCG_TPM && ACPI
+       select TCG_IBMVTPM if TCG_TPM && PPC_PSERIES
+-- 
+2.40.1
+

diff --git a/queue-5.10/iopoll-call-cpu_relax-in-busy-loops.patch b/queue-5.10/iopoll-call-cpu_relax-in-busy-loops.patch
new file mode 100644 (file)
index 0000000..e94f2bf
--- /dev/null
+++ b/queue-5.10/iopoll-call-cpu_relax-in-busy-loops.patch
@@ -0,0 +1,77 @@
+From d62a5b83cdb21ae174b8acb9751c48004b7bf318 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 2 Jun 2023 10:50:36 +0200
+Subject: iopoll: Call cpu_relax() in busy loops
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+[ Upstream commit b407460ee99033503993ac7437d593451fcdfe44 ]
+
+It is considered good practice to call cpu_relax() in busy loops, see
+Documentation/process/volatile-considered-harmful.rst.  This can not
+only lower CPU power consumption or yield to a hyperthreaded twin
+processor, but also allows an architecture to mitigate hardware issues
+(e.g. ARM Erratum 754327 for Cortex-A9 prior to r2p0) in the
+architecture-specific cpu_relax() implementation.
+
+In addition, cpu_relax() is also a compiler barrier.  It is not
+immediately obvious that the @op argument "function" will result in an
+actual function call (e.g. in case of inlining).
+
+Where a function call is a C sequence point, this is lost on inlining.
+Therefore, with agressive enough optimization it might be possible for
+the compiler to hoist the:
+
+        (val) = op(args);
+
+"load" out of the loop because it doesn't see the value changing. The
+addition of cpu_relax() would inhibit this.
+
+As the iopoll helpers lack calls to cpu_relax(), people are sometimes
+reluctant to use them, and may fall back to open-coded polling loops
+(including cpu_relax() calls) instead.
+
+Fix this by adding calls to cpu_relax() to the iopoll helpers:
+  - For the non-atomic case, it is sufficient to call cpu_relax() in
+    case of a zero sleep-between-reads value, as a call to
+    usleep_range() is a safe barrier otherwise.  However, it doesn't
+    hurt to add the call regardless, for simplicity, and for similarity
+    with the atomic case below.
+  - For the atomic case, cpu_relax() must be called regardless of the
+    sleep-between-reads value, as there is no guarantee all
+    architecture-specific implementations of udelay() handle this.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Link: https://lore.kernel.org/r/45c87bec3397fdd704376807f0eec5cc71be440f.1685692810.git.geert+renesas@glider.be
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/iopoll.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
+index 2c8860e406bd8..0417360a6db9b 100644
+--- a/include/linux/iopoll.h
++++ b/include/linux/iopoll.h
+@@ -53,6 +53,7 @@
+               } \
+               if (__sleep_us) \
+                       usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
++              cpu_relax(); \
+       } \
+       (cond) ? 0 : -ETIMEDOUT; \
+ })
+@@ -95,6 +96,7 @@
+               } \
+               if (__delay_us) \
+                       udelay(__delay_us); \
++              cpu_relax(); \
+       } \
+       (cond) ? 0 : -ETIMEDOUT; \
+ })
+-- 
+2.40.1
+

diff --git a/queue-5.10/irqchip-mips-gic-get-rid-of-the-reliance-on-irq_cpu_.patch b/queue-5.10/irqchip-mips-gic-get-rid-of-the-reliance-on-irq_cpu_.patch
new file mode 100644 (file)
index 0000000..a4fbfa1
--- /dev/null
+++ b/queue-5.10/irqchip-mips-gic-get-rid-of-the-reliance-on-irq_cpu_.patch
@@ -0,0 +1,102 @@
+From 2b6824a4899495e4602e0d7f6a474479462aa8f0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 21 Oct 2021 18:04:13 +0100
+Subject: irqchip/mips-gic: Get rid of the reliance on irq_cpu_online()
+
+From: Marc Zyngier <maz@kernel.org>
+
+[ Upstream commit dd098a0e031928cf88c89f7577d31821e1f0e6de ]
+
+The MIPS GIC driver uses irq_cpu_online() to go and program the
+per-CPU interrupts. However, this method iterates over all IRQs
+in the system, despite only 3 per-CPU interrupts being of interest.
+
+Let's be terribly bold and do the iteration ourselves. To ensure
+mutual exclusion, hold the gic_lock spinlock that is otherwise
+taken while dealing with these interrupts.
+
+Signed-off-by: Marc Zyngier <maz@kernel.org>
+Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Tested-by: Serge Semin <fancer.lancer@gmail.com>
+Link: https://lore.kernel.org/r/20211021170414.3341522-3-maz@kernel.org
+Stable-dep-of: 3d6a0e4197c0 ("irqchip/mips-gic: Use raw spinlock for gic_lock")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/irqchip/irq-mips-gic.c | 37 ++++++++++++++++++++++++----------
+ 1 file changed, 26 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
+index 8ada91bdbe4d0..7e4a9e75b49be 100644
+--- a/drivers/irqchip/irq-mips-gic.c
++++ b/drivers/irqchip/irq-mips-gic.c
+@@ -382,24 +382,35 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
+       spin_unlock_irqrestore(&gic_lock, flags);
+ }
+ 
+-static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
++static void gic_all_vpes_irq_cpu_online(void)
+ {
+-      struct gic_all_vpes_chip_data *cd;
+-      unsigned int intr;
++      static const unsigned int local_intrs[] = {
++              GIC_LOCAL_INT_TIMER,
++              GIC_LOCAL_INT_PERFCTR,
++              GIC_LOCAL_INT_FDC,
++      };
++      unsigned long flags;
++      int i;
+ 
+-      intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
+-      cd = irq_data_get_irq_chip_data(d);
++      spin_lock_irqsave(&gic_lock, flags);
+ 
+-      write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
+-      if (cd->mask)
+-              write_gic_vl_smask(BIT(intr));
++      for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
++              unsigned int intr = local_intrs[i];
++              struct gic_all_vpes_chip_data *cd;
++
++              cd = &gic_all_vpes_chip_data[intr];
++              write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
++              if (cd->mask)
++                      write_gic_vl_smask(BIT(intr));
++      }
++
++      spin_unlock_irqrestore(&gic_lock, flags);
+ }
+ 
+ static struct irq_chip gic_all_vpes_local_irq_controller = {
+       .name                   = "MIPS GIC Local",
+       .irq_mask               = gic_mask_local_irq_all_vpes,
+       .irq_unmask             = gic_unmask_local_irq_all_vpes,
+-      .irq_cpu_online         = gic_all_vpes_irq_cpu_online,
+ };
+ 
+ static void __gic_irq_dispatch(void)
+@@ -480,6 +491,10 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
+       intr = GIC_HWIRQ_TO_LOCAL(hwirq);
+       map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
+ 
++      /*
++       * If adding support for more per-cpu interrupts, keep the the
++       * array in gic_all_vpes_irq_cpu_online() in sync.
++       */
+       switch (intr) {
+       case GIC_LOCAL_INT_TIMER:
+               /* CONFIG_MIPS_CMP workaround (see __gic_init) */
+@@ -710,8 +725,8 @@ static int gic_cpu_startup(unsigned int cpu)
+       /* Clear all local IRQ masks (ie. disable all local interrupts) */
+       write_gic_vl_rmask(~0);
+ 
+-      /* Invoke irq_cpu_online callbacks to enable desired interrupts */
+-      irq_cpu_online();
++      /* Enable desired interrupts */
++      gic_all_vpes_irq_cpu_online();
+ 
+       return 0;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.10/irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch b/queue-5.10/irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch
new file mode 100644 (file)
index 0000000..90eb469
--- /dev/null
+++ b/queue-5.10/irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch
@@ -0,0 +1,163 @@
+From 5f4e30944de03926099dfd6c950860675133b634 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 24 Apr 2023 11:31:56 +0100
+Subject: irqchip/mips-gic: Use raw spinlock for gic_lock
+
+From: Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+[ Upstream commit 3d6a0e4197c04599d75d85a608c8bb16a630a38c ]
+
+Since we may hold gic_lock in hardirq context, use raw spinlock
+makes more sense given that it is for low-level interrupt handling
+routine and the critical section is small.
+
+Fixes BUG:
+
+[    0.426106] =============================
+[    0.426257] [ BUG: Invalid wait context ]
+[    0.426422] 6.3.0-rc7-next-20230421-dirty #54 Not tainted
+[    0.426638] -----------------------------
+[    0.426766] swapper/0/1 is trying to lock:
+[    0.426954] ffffffff8104e7b8 (gic_lock){....}-{3:3}, at: gic_set_type+0x30/08
+
+Fixes: 95150ae8b330 ("irqchip: mips-gic: Implement irq_set_type callback")
+Cc: stable@vger.kernel.org
+Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
+Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
+Tested-by: Serge Semin <fancer.lancer@gmail.com>
+Signed-off-by: Marc Zyngier <maz@kernel.org>
+Link: https://lore.kernel.org/r/20230424103156.66753-3-jiaxun.yang@flygoat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/irqchip/irq-mips-gic.c | 30 +++++++++++++++---------------
+ 1 file changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
+index 7e4a9e75b49be..fc25b900cef71 100644
+--- a/drivers/irqchip/irq-mips-gic.c
++++ b/drivers/irqchip/irq-mips-gic.c
+@@ -48,7 +48,7 @@ void __iomem *mips_gic_base;
+ 
+ static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
+ 
+-static DEFINE_SPINLOCK(gic_lock);
++static DEFINE_RAW_SPINLOCK(gic_lock);
+ static struct irq_domain *gic_irq_domain;
+ static int gic_shared_intrs;
+ static unsigned int gic_cpu_pin;
+@@ -209,7 +209,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
+ 
+       irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
+ 
+-      spin_lock_irqsave(&gic_lock, flags);
++      raw_spin_lock_irqsave(&gic_lock, flags);
+       switch (type & IRQ_TYPE_SENSE_MASK) {
+       case IRQ_TYPE_EDGE_FALLING:
+               pol = GIC_POL_FALLING_EDGE;
+@@ -249,7 +249,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
+       else
+               irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
+                                                handle_level_irq, NULL);
+-      spin_unlock_irqrestore(&gic_lock, flags);
++      raw_spin_unlock_irqrestore(&gic_lock, flags);
+ 
+       return 0;
+ }
+@@ -267,7 +267,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
+               return -EINVAL;
+ 
+       /* Assumption : cpumask refers to a single CPU */
+-      spin_lock_irqsave(&gic_lock, flags);
++      raw_spin_lock_irqsave(&gic_lock, flags);
+ 
+       /* Re-route this IRQ */
+       write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
+@@ -278,7 +278,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
+               set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
+ 
+       irq_data_update_effective_affinity(d, cpumask_of(cpu));
+-      spin_unlock_irqrestore(&gic_lock, flags);
++      raw_spin_unlock_irqrestore(&gic_lock, flags);
+ 
+       return IRQ_SET_MASK_OK;
+ }
+@@ -356,12 +356,12 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
+       cd = irq_data_get_irq_chip_data(d);
+       cd->mask = false;
+ 
+-      spin_lock_irqsave(&gic_lock, flags);
++      raw_spin_lock_irqsave(&gic_lock, flags);
+       for_each_online_cpu(cpu) {
+               write_gic_vl_other(mips_cm_vp_id(cpu));
+               write_gic_vo_rmask(BIT(intr));
+       }
+-      spin_unlock_irqrestore(&gic_lock, flags);
++      raw_spin_unlock_irqrestore(&gic_lock, flags);
+ }
+ 
+ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
+@@ -374,12 +374,12 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
+       cd = irq_data_get_irq_chip_data(d);
+       cd->mask = true;
+ 
+-      spin_lock_irqsave(&gic_lock, flags);
++      raw_spin_lock_irqsave(&gic_lock, flags);
+       for_each_online_cpu(cpu) {
+               write_gic_vl_other(mips_cm_vp_id(cpu));
+               write_gic_vo_smask(BIT(intr));
+       }
+-      spin_unlock_irqrestore(&gic_lock, flags);
++      raw_spin_unlock_irqrestore(&gic_lock, flags);
+ }
+ 
+ static void gic_all_vpes_irq_cpu_online(void)
+@@ -392,7 +392,7 @@ static void gic_all_vpes_irq_cpu_online(void)
+       unsigned long flags;
+       int i;
+ 
+-      spin_lock_irqsave(&gic_lock, flags);
++      raw_spin_lock_irqsave(&gic_lock, flags);
+ 
+       for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
+               unsigned int intr = local_intrs[i];
+@@ -404,7 +404,7 @@ static void gic_all_vpes_irq_cpu_online(void)
+                       write_gic_vl_smask(BIT(intr));
+       }
+ 
+-      spin_unlock_irqrestore(&gic_lock, flags);
++      raw_spin_unlock_irqrestore(&gic_lock, flags);
+ }
+ 
+ static struct irq_chip gic_all_vpes_local_irq_controller = {
+@@ -434,11 +434,11 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
+ 
+       data = irq_get_irq_data(virq);
+ 
+-      spin_lock_irqsave(&gic_lock, flags);
++      raw_spin_lock_irqsave(&gic_lock, flags);
+       write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
+       write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
+       irq_data_update_effective_affinity(data, cpumask_of(cpu));
+-      spin_unlock_irqrestore(&gic_lock, flags);
++      raw_spin_unlock_irqrestore(&gic_lock, flags);
+ 
+       return 0;
+ }
+@@ -533,12 +533,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
+       if (!gic_local_irq_is_routable(intr))
+               return -EPERM;
+ 
+-      spin_lock_irqsave(&gic_lock, flags);
++      raw_spin_lock_irqsave(&gic_lock, flags);
+       for_each_online_cpu(cpu) {
+               write_gic_vl_other(mips_cm_vp_id(cpu));
+               write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
+       }
+-      spin_unlock_irqrestore(&gic_lock, flags);
++      raw_spin_unlock_irqrestore(&gic_lock, flags);
+ 
+       return 0;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.10/macsec-fix-traffic-counters-statistics.patch b/queue-5.10/macsec-fix-traffic-counters-statistics.patch
new file mode 100644 (file)
index 0000000..20c9740
--- /dev/null
+++ b/queue-5.10/macsec-fix-traffic-counters-statistics.patch
@@ -0,0 +1,250 @@
+From 4ac458fd0cfcac45a36c5cbe05c5cb05adce5dde Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 8 Aug 2022 15:38:23 -0700
+Subject: macsec: Fix traffic counters/statistics
+
+From: Clayton Yager <Clayton_Yager@selinc.com>
+
+[ Upstream commit 91ec9bd57f3524ff3d86bfb7c9ee5a315019733c ]
+
+OutOctetsProtected, OutOctetsEncrypted, InOctetsValidated, and
+InOctetsDecrypted were incrementing by the total number of octets in frames
+instead of by the number of octets of User Data in frames.
+
+The Controlled Port statistics ifOutOctets and ifInOctets were incrementing
+by the total number of octets instead of the number of octets of the MSDUs
+plus octets of the destination and source MAC addresses.
+
+The Controlled Port statistics ifInDiscards and ifInErrors were not
+incrementing each time the counters they aggregate were.
+
+The Controlled Port statistic ifInErrors was not included in the output of
+macsec_get_stats64 so the value was not present in ip commands output.
+
+The ReceiveSA counters InPktsNotValid, InPktsNotUsingSA, and InPktsUnusedSA
+were not incrementing.
+
+Signed-off-by: Clayton Yager <Clayton_Yager@selinc.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Stable-dep-of: 32d0a49d36a2 ("macsec: use DEV_STATS_INC()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/macsec.c | 58 +++++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 49 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c
+index 4fdb970e34823..6691c941f8bb8 100644
+--- a/drivers/net/macsec.c
++++ b/drivers/net/macsec.c
+@@ -159,6 +159,19 @@ static struct macsec_rx_sa *macsec_rxsa_get(struct macsec_rx_sa __rcu *ptr)
+       return sa;
+ }
+ 
++static struct macsec_rx_sa *macsec_active_rxsa_get(struct macsec_rx_sc *rx_sc)
++{
++      struct macsec_rx_sa *sa = NULL;
++      int an;
++
++      for (an = 0; an < MACSEC_NUM_AN; an++)  {
++              sa = macsec_rxsa_get(rx_sc->sa[an]);
++              if (sa)
++                      break;
++      }
++      return sa;
++}
++
+ static void free_rx_sc_rcu(struct rcu_head *head)
+ {
+       struct macsec_rx_sc *rx_sc = container_of(head, struct macsec_rx_sc, rcu_head);
+@@ -497,18 +510,28 @@ static void macsec_encrypt_finish(struct sk_buff *skb, struct net_device *dev)
+       skb->protocol = eth_hdr(skb)->h_proto;
+ }
+ 
++static unsigned int macsec_msdu_len(struct sk_buff *skb)
++{
++      struct macsec_dev *macsec = macsec_priv(skb->dev);
++      struct macsec_secy *secy = &macsec->secy;
++      bool sci_present = macsec_skb_cb(skb)->has_sci;
++
++      return skb->len - macsec_hdr_len(sci_present) - secy->icv_len;
++}
++
+ static void macsec_count_tx(struct sk_buff *skb, struct macsec_tx_sc *tx_sc,
+                           struct macsec_tx_sa *tx_sa)
+ {
++      unsigned int msdu_len = macsec_msdu_len(skb);
+       struct pcpu_tx_sc_stats *txsc_stats = this_cpu_ptr(tx_sc->stats);
+ 
+       u64_stats_update_begin(&txsc_stats->syncp);
+       if (tx_sc->encrypt) {
+-              txsc_stats->stats.OutOctetsEncrypted += skb->len;
++              txsc_stats->stats.OutOctetsEncrypted += msdu_len;
+               txsc_stats->stats.OutPktsEncrypted++;
+               this_cpu_inc(tx_sa->stats->OutPktsEncrypted);
+       } else {
+-              txsc_stats->stats.OutOctetsProtected += skb->len;
++              txsc_stats->stats.OutOctetsProtected += msdu_len;
+               txsc_stats->stats.OutPktsProtected++;
+               this_cpu_inc(tx_sa->stats->OutPktsProtected);
+       }
+@@ -538,9 +561,10 @@ static void macsec_encrypt_done(struct crypto_async_request *base, int err)
+       aead_request_free(macsec_skb_cb(skb)->req);
+ 
+       rcu_read_lock_bh();
+-      macsec_encrypt_finish(skb, dev);
+       macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa);
+-      len = skb->len;
++      /* packet is encrypted/protected so tx_bytes must be calculated */
++      len = macsec_msdu_len(skb) + 2 * ETH_ALEN;
++      macsec_encrypt_finish(skb, dev);
+       ret = dev_queue_xmit(skb);
+       count_tx(dev, ret, len);
+       rcu_read_unlock_bh();
+@@ -699,6 +723,7 @@ static struct sk_buff *macsec_encrypt(struct sk_buff *skb,
+ 
+       macsec_skb_cb(skb)->req = req;
+       macsec_skb_cb(skb)->tx_sa = tx_sa;
++      macsec_skb_cb(skb)->has_sci = sci_present;
+       aead_request_set_callback(req, 0, macsec_encrypt_done, skb);
+ 
+       dev_hold(skb->dev);
+@@ -740,15 +765,17 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               rxsc_stats->stats.InPktsLate++;
+               u64_stats_update_end(&rxsc_stats->syncp);
++              secy->netdev->stats.rx_dropped++;
+               return false;
+       }
+ 
+       if (secy->validate_frames != MACSEC_VALIDATE_DISABLED) {
++              unsigned int msdu_len = macsec_msdu_len(skb);
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               if (hdr->tci_an & MACSEC_TCI_E)
+-                      rxsc_stats->stats.InOctetsDecrypted += skb->len;
++                      rxsc_stats->stats.InOctetsDecrypted += msdu_len;
+               else
+-                      rxsc_stats->stats.InOctetsValidated += skb->len;
++                      rxsc_stats->stats.InOctetsValidated += msdu_len;
+               u64_stats_update_end(&rxsc_stats->syncp);
+       }
+ 
+@@ -761,6 +788,8 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsNotValid++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
++                      this_cpu_inc(rx_sa->stats->InPktsNotValid);
++                      secy->netdev->stats.rx_errors++;
+                       return false;
+               }
+ 
+@@ -853,9 +882,9 @@ static void macsec_decrypt_done(struct crypto_async_request *base, int err)
+ 
+       macsec_finalize_skb(skb, macsec->secy.icv_len,
+                           macsec_extra_len(macsec_skb_cb(skb)->has_sci));
++      len = skb->len;
+       macsec_reset_skb(skb, macsec->secy.netdev);
+ 
+-      len = skb->len;
+       if (gro_cells_receive(&macsec->gro_cells, skb) == NET_RX_SUCCESS)
+               count_rx(dev, len);
+ 
+@@ -1046,6 +1075,7 @@ static enum rx_handler_result handle_not_macsec(struct sk_buff *skb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoTag++;
+                       u64_stats_update_end(&secy_stats->syncp);
++                      macsec->secy.netdev->stats.rx_dropped++;
+                       continue;
+               }
+ 
+@@ -1155,6 +1185,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               u64_stats_update_begin(&secy_stats->syncp);
+               secy_stats->stats.InPktsBadTag++;
+               u64_stats_update_end(&secy_stats->syncp);
++              secy->netdev->stats.rx_errors++;
+               goto drop_nosa;
+       }
+ 
+@@ -1165,11 +1196,15 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               /* If validateFrames is Strict or the C bit in the
+                * SecTAG is set, discard
+                */
++              struct macsec_rx_sa *active_rx_sa = macsec_active_rxsa_get(rx_sc);
+               if (hdr->tci_an & MACSEC_TCI_C ||
+                   secy->validate_frames == MACSEC_VALIDATE_STRICT) {
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsNotUsingSA++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
++                      secy->netdev->stats.rx_errors++;
++                      if (active_rx_sa)
++                              this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA);
+                       goto drop_nosa;
+               }
+ 
+@@ -1179,6 +1214,8 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               rxsc_stats->stats.InPktsUnusedSA++;
+               u64_stats_update_end(&rxsc_stats->syncp);
++              if (active_rx_sa)
++                      this_cpu_inc(active_rx_sa->stats->InPktsUnusedSA);
+               goto deliver;
+       }
+ 
+@@ -1199,6 +1236,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsLate++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
++                      macsec->secy.netdev->stats.rx_dropped++;
+                       goto drop;
+               }
+       }
+@@ -1227,6 +1265,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+ deliver:
+       macsec_finalize_skb(skb, secy->icv_len,
+                           macsec_extra_len(macsec_skb_cb(skb)->has_sci));
++      len = skb->len;
+       macsec_reset_skb(skb, secy->netdev);
+ 
+       if (rx_sa)
+@@ -1234,7 +1273,6 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+       macsec_rxsc_put(rx_sc);
+ 
+       skb_orphan(skb);
+-      len = skb->len;
+       ret = gro_cells_receive(&macsec->gro_cells, skb);
+       if (ret == NET_RX_SUCCESS)
+               count_rx(dev, len);
+@@ -1276,6 +1314,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoSCI++;
+                       u64_stats_update_end(&secy_stats->syncp);
++                      macsec->secy.netdev->stats.rx_errors++;
+                       continue;
+               }
+ 
+@@ -3407,6 +3446,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+               return NETDEV_TX_OK;
+       }
+ 
++      len = skb->len;
+       skb = macsec_encrypt(skb, dev);
+       if (IS_ERR(skb)) {
+               if (PTR_ERR(skb) != -EINPROGRESS)
+@@ -3417,7 +3457,6 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+       macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa);
+ 
+       macsec_encrypt_finish(skb, dev);
+-      len = skb->len;
+       ret = dev_queue_xmit(skb);
+       count_tx(dev, ret, len);
+       return ret;
+@@ -3648,6 +3687,7 @@ static void macsec_get_stats64(struct net_device *dev,
+ 
+       s->rx_dropped = dev->stats.rx_dropped;
+       s->tx_dropped = dev->stats.tx_dropped;
++      s->rx_errors = dev->stats.rx_errors;
+ }
+ 
+ static int macsec_get_iflink(const struct net_device *dev)
+-- 
+2.40.1
+

diff --git a/queue-5.10/macsec-use-dev_stats_inc.patch b/queue-5.10/macsec-use-dev_stats_inc.patch
new file mode 100644 (file)
index 0000000..90e1602
--- /dev/null
+++ b/queue-5.10/macsec-use-dev_stats_inc.patch
@@ -0,0 +1,145 @@
+From 9762aa9c0808ee5709d08569808a48026aa9f7d3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 4 Aug 2023 17:26:52 +0000
+Subject: macsec: use DEV_STATS_INC()
+
+From: Eric Dumazet <edumazet@google.com>
+
+[ Upstream commit 32d0a49d36a2a306c2e47fe5659361e424f0ed3f ]
+
+syzbot/KCSAN reported data-races in macsec whenever dev->stats fields
+are updated.
+
+It appears all of these updates can happen from multiple cpus.
+
+Adopt SMP safe DEV_STATS_INC() to update dev->stats fields.
+
+Fixes: c09440f7dcb3 ("macsec: introduce IEEE 802.1AE driver")
+Reported-by: syzbot <syzkaller@googlegroups.com>
+Signed-off-by: Eric Dumazet <edumazet@google.com>
+Cc: Sabrina Dubroca <sd@queasysnail.net>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/macsec.c | 28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c
+index 6691c941f8bb8..2ad15b1d7ffd7 100644
+--- a/drivers/net/macsec.c
++++ b/drivers/net/macsec.c
+@@ -765,7 +765,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+               u64_stats_update_begin(&rxsc_stats->syncp);
+               rxsc_stats->stats.InPktsLate++;
+               u64_stats_update_end(&rxsc_stats->syncp);
+-              secy->netdev->stats.rx_dropped++;
++              DEV_STATS_INC(secy->netdev, rx_dropped);
+               return false;
+       }
+ 
+@@ -789,7 +789,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u
+                       rxsc_stats->stats.InPktsNotValid++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
+                       this_cpu_inc(rx_sa->stats->InPktsNotValid);
+-                      secy->netdev->stats.rx_errors++;
++                      DEV_STATS_INC(secy->netdev, rx_errors);
+                       return false;
+               }
+ 
+@@ -1075,7 +1075,7 @@ static enum rx_handler_result handle_not_macsec(struct sk_buff *skb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoTag++;
+                       u64_stats_update_end(&secy_stats->syncp);
+-                      macsec->secy.netdev->stats.rx_dropped++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+                       continue;
+               }
+ 
+@@ -1185,7 +1185,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+               u64_stats_update_begin(&secy_stats->syncp);
+               secy_stats->stats.InPktsBadTag++;
+               u64_stats_update_end(&secy_stats->syncp);
+-              secy->netdev->stats.rx_errors++;
++              DEV_STATS_INC(secy->netdev, rx_errors);
+               goto drop_nosa;
+       }
+ 
+@@ -1202,7 +1202,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsNotUsingSA++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
+-                      secy->netdev->stats.rx_errors++;
++                      DEV_STATS_INC(secy->netdev, rx_errors);
+                       if (active_rx_sa)
+                               this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA);
+                       goto drop_nosa;
+@@ -1236,7 +1236,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&rxsc_stats->syncp);
+                       rxsc_stats->stats.InPktsLate++;
+                       u64_stats_update_end(&rxsc_stats->syncp);
+-                      macsec->secy.netdev->stats.rx_dropped++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+                       goto drop;
+               }
+       }
+@@ -1277,7 +1277,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+       if (ret == NET_RX_SUCCESS)
+               count_rx(dev, len);
+       else
+-              macsec->secy.netdev->stats.rx_dropped++;
++              DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+ 
+       rcu_read_unlock();
+ 
+@@ -1314,7 +1314,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       u64_stats_update_begin(&secy_stats->syncp);
+                       secy_stats->stats.InPktsNoSCI++;
+                       u64_stats_update_end(&secy_stats->syncp);
+-                      macsec->secy.netdev->stats.rx_errors++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_errors);
+                       continue;
+               }
+ 
+@@ -1333,7 +1333,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb)
+                       secy_stats->stats.InPktsUnknownSCI++;
+                       u64_stats_update_end(&secy_stats->syncp);
+               } else {
+-                      macsec->secy.netdev->stats.rx_dropped++;
++                      DEV_STATS_INC(macsec->secy.netdev, rx_dropped);
+               }
+       }
+ 
+@@ -3442,7 +3442,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+ 
+       if (!secy->operational) {
+               kfree_skb(skb);
+-              dev->stats.tx_dropped++;
++              DEV_STATS_INC(dev, tx_dropped);
+               return NETDEV_TX_OK;
+       }
+ 
+@@ -3450,7 +3450,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,
+       skb = macsec_encrypt(skb, dev);
+       if (IS_ERR(skb)) {
+               if (PTR_ERR(skb) != -EINPROGRESS)
+-                      dev->stats.tx_dropped++;
++                      DEV_STATS_INC(dev, tx_dropped);
+               return NETDEV_TX_OK;
+       }
+ 
+@@ -3685,9 +3685,9 @@ static void macsec_get_stats64(struct net_device *dev,
+ 
+       dev_fetch_sw_netstats(s, dev->tstats);
+ 
+-      s->rx_dropped = dev->stats.rx_dropped;
+-      s->tx_dropped = dev->stats.tx_dropped;
+-      s->rx_errors = dev->stats.rx_errors;
++      s->rx_dropped = atomic_long_read(&dev->stats.__rx_dropped);
++      s->tx_dropped = atomic_long_read(&dev->stats.__tx_dropped);
++      s->rx_errors = atomic_long_read(&dev->stats.__rx_errors);
+ }
+ 
+ static int macsec_get_iflink(const struct net_device *dev)
+-- 
+2.40.1
+

diff --git a/queue-5.10/media-platform-mediatek-vpu-fix-null-ptr-dereference.patch b/queue-5.10/media-platform-mediatek-vpu-fix-null-ptr-dereference.patch
new file mode 100644 (file)
index 0000000..4e084a0
--- /dev/null
+++ b/queue-5.10/media-platform-mediatek-vpu-fix-null-ptr-dereference.patch
@@ -0,0 +1,50 @@
+From d8cfd60cf39641522287bf868e4de884f33994c7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 24 May 2023 13:11:47 +0100
+Subject: media: platform: mediatek: vpu: fix NULL ptr dereference
+
+From: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+
+[ Upstream commit 3df55cd773e8603b623425cc97b05e542854ad27 ]
+
+If pdev is NULL, then it is still dereferenced.
+
+This fixes this smatch warning:
+
+drivers/media/platform/mediatek/vpu/mtk_vpu.c:570 vpu_load_firmware() warn: address of NULL pointer 'pdev'
+
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Cc: Yunfei Dong <yunfei.dong@mediatek.com>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/platform/mtk-vpu/mtk_vpu.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/platform/mtk-vpu/mtk_vpu.c b/drivers/media/platform/mtk-vpu/mtk_vpu.c
+index c62eb212cca92..e7c4b0dd588a9 100644
+--- a/drivers/media/platform/mtk-vpu/mtk_vpu.c
++++ b/drivers/media/platform/mtk-vpu/mtk_vpu.c
+@@ -539,15 +539,17 @@ static int load_requested_vpu(struct mtk_vpu *vpu,
+ int vpu_load_firmware(struct platform_device *pdev)
+ {
+       struct mtk_vpu *vpu;
+-      struct device *dev = &pdev->dev;
++      struct device *dev;
+       struct vpu_run *run;
+       int ret;
+ 
+       if (!pdev) {
+-              dev_err(dev, "VPU platform device is invalid\n");
++              pr_err("VPU platform device is invalid\n");
+               return -EINVAL;
+       }
+ 
++      dev = &pdev->dev;
++
+       vpu = platform_get_drvdata(pdev);
+       run = &vpu->run;
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch b/queue-5.10/media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch
new file mode 100644 (file)
index 0000000..20b88ea
--- /dev/null
+++ b/queue-5.10/media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch
@@ -0,0 +1,69 @@
+From bfe70c55fe47b2bb4281b14e90fcd88a21199ce0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Apr 2023 16:17:40 +0800
+Subject: media: v4l2-mem2mem: add lock to protect parameter num_rdy
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Yunfei Dong <yunfei.dong@mediatek.com>
+
+[ Upstream commit 56b5c3e67b0f9af3f45cf393be048ee8d8a92694 ]
+
+Getting below error when using KCSAN to check the driver. Adding lock to
+protect parameter num_rdy when getting the value with function:
+v4l2_m2m_num_src_bufs_ready/v4l2_m2m_num_dst_bufs_ready.
+
+kworker/u16:3: [name:report&]BUG: KCSAN: data-race in v4l2_m2m_buf_queue
+kworker/u16:3: [name:report&]
+
+kworker/u16:3: [name:report&]read-write to 0xffffff8105f35b94 of 1 bytes by task 20865 on cpu 7:
+kworker/u16:3:  v4l2_m2m_buf_queue+0xd8/0x10c
+
+Signed-off-by: Pina Chen <pina.chen@mediatek.com>
+Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
+Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/media/v4l2-mem2mem.h | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h
+index 5a91b548ecc0c..8d52c4506762d 100644
+--- a/include/media/v4l2-mem2mem.h
++++ b/include/media/v4l2-mem2mem.h
+@@ -588,7 +588,14 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx,
+ static inline
+ unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx)
+ {
+-      return m2m_ctx->out_q_ctx.num_rdy;
++      unsigned int num_buf_rdy;
++      unsigned long flags;
++
++      spin_lock_irqsave(&m2m_ctx->out_q_ctx.rdy_spinlock, flags);
++      num_buf_rdy = m2m_ctx->out_q_ctx.num_rdy;
++      spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags);
++
++      return num_buf_rdy;
+ }
+ 
+ /**
+@@ -600,7 +607,14 @@ unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx)
+ static inline
+ unsigned int v4l2_m2m_num_dst_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx)
+ {
+-      return m2m_ctx->cap_q_ctx.num_rdy;
++      unsigned int num_buf_rdy;
++      unsigned long flags;
++
++      spin_lock_irqsave(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags);
++      num_buf_rdy = m2m_ctx->cap_q_ctx.num_rdy;
++      spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags);
++
++      return num_buf_rdy;
+ }
+ 
+ /**
+-- 
+2.40.1
+

diff --git a/queue-5.10/mips-dec-prom-address-warray-bounds-warning.patch b/queue-5.10/mips-dec-prom-address-warray-bounds-warning.patch
new file mode 100644 (file)
index 0000000..e5da0fe
--- /dev/null
+++ b/queue-5.10/mips-dec-prom-address-warray-bounds-warning.patch
@@ -0,0 +1,54 @@
+From 4296ff036a93b98b5a5b84ab512edbe56f37b5a6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Jun 2023 17:43:57 -0600
+Subject: MIPS: dec: prom: Address -Warray-bounds warning
+
+From: Gustavo A. R. Silva <gustavoars@kernel.org>
+
+[ Upstream commit 7b191b9b55df2a844bd32d1d380f47a7df1c2896 ]
+
+Zero-length arrays are deprecated, and we are replacing them with flexible
+array members instead. So, replace zero-length array with flexible-array
+member in struct memmap.
+
+Address the following warning found after building (with GCC-13) mips64
+with decstation_64_defconfig:
+In function 'rex_setup_memory_region',
+    inlined from 'prom_meminit' at arch/mips/dec/prom/memory.c:91:3:
+arch/mips/dec/prom/memory.c:72:31: error: array subscript i is outside array bounds of 'unsigned char[0]' [-Werror=array-bounds=]
+   72 |                 if (bm->bitmap[i] == 0xff)
+      |                     ~~~~~~~~~~^~~
+In file included from arch/mips/dec/prom/memory.c:16:
+./arch/mips/include/asm/dec/prom.h: In function 'prom_meminit':
+./arch/mips/include/asm/dec/prom.h:73:23: note: while referencing 'bitmap'
+   73 |         unsigned char bitmap[0];
+
+This helps with the ongoing efforts to globally enable -Warray-bounds.
+
+This results in no differences in binary output.
+
+Link: https://github.com/KSPP/linux/issues/79
+Link: https://github.com/KSPP/linux/issues/323
+Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/mips/include/asm/dec/prom.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
+index 1e1247add1cf8..908e96e3a3117 100644
+--- a/arch/mips/include/asm/dec/prom.h
++++ b/arch/mips/include/asm/dec/prom.h
+@@ -70,7 +70,7 @@ static inline bool prom_is_rex(u32 magic)
+  */
+ typedef struct {
+       int pagesize;
+-      unsigned char bitmap[0];
++      unsigned char bitmap[];
+ } memmap;
+ 
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/mmc-bcm2835-fix-deferred-probing.patch b/queue-5.10/mmc-bcm2835-fix-deferred-probing.patch
new file mode 100644 (file)
index 0000000..6c46906
--- /dev/null
+++ b/queue-5.10/mmc-bcm2835-fix-deferred-probing.patch
@@ -0,0 +1,44 @@
+From 784d0744ff678725e2d892c7421b10c15bbaad74 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Jun 2023 23:36:11 +0300
+Subject: mmc: bcm2835: fix deferred probing
+
+From: Sergey Shtylyov <s.shtylyov@omp.ru>
+
+[ Upstream commit 71150ac12558bcd9d75e6e24cf7c872c2efd80f3 ]
+
+The driver overrides the error codes and IRQ0 returned by platform_get_irq()
+to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe
+permanently instead of the deferred probing. Switch to propagating the error
+codes upstream.  Since commit ce753ad1549c ("platform: finally disallow IRQ0
+in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs,
+so we now can safely ignore it...
+
+Fixes: 660fc733bd74 ("mmc: bcm2835: Add new driver for the sdhost controller.")
+Cc: stable@vger.kernel.org # v5.19+
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
+Link: https://lore.kernel.org/r/20230617203622.6812-2-s.shtylyov@omp.ru
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/bcm2835.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c
+index 8c2361e662774..985079943be76 100644
+--- a/drivers/mmc/host/bcm2835.c
++++ b/drivers/mmc/host/bcm2835.c
+@@ -1413,8 +1413,8 @@ static int bcm2835_probe(struct platform_device *pdev)
+       host->max_clk = clk_get_rate(clk);
+ 
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0) {
+-              ret = -EINVAL;
++      if (host->irq < 0) {
++              ret = host->irq;
+               goto err;
+       }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/mmc-core-add-devm_mmc_alloc_host.patch b/queue-5.10/mmc-core-add-devm_mmc_alloc_host.patch
new file mode 100644 (file)
index 0000000..c2e3ff8
--- /dev/null
+++ b/queue-5.10/mmc-core-add-devm_mmc_alloc_host.patch
@@ -0,0 +1,76 @@
+From 4b907536db023207f3f397f4d0c519fe8a630dcb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 4 Feb 2023 00:53:35 +0100
+Subject: mmc: core: add devm_mmc_alloc_host
+
+From: Heiner Kallweit <hkallweit1@gmail.com>
+
+[ Upstream commit 80df83c2c57e75cb482ccf0c639ce84703ab41a2 ]
+
+Add a device-managed version of mmc_alloc_host().
+
+The argument order is reversed compared to mmc_alloc_host() because
+device-managed functions typically have the device argument first.
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Link: https://lore.kernel.org/r/6d8f9fdc-7c9e-8e4f-e6ef-5470b971c74e@gmail.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Stable-dep-of: b8ada54fa1b8 ("mmc: meson-gx: fix deferred probing")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/core/host.c  | 26 ++++++++++++++++++++++++++
+ include/linux/mmc/host.h |  1 +
+ 2 files changed, 27 insertions(+)
+
+diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
+index 03e2f965a96a8..1f46694b2e531 100644
+--- a/drivers/mmc/core/host.c
++++ b/drivers/mmc/core/host.c
+@@ -513,6 +513,32 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
+ 
+ EXPORT_SYMBOL(mmc_alloc_host);
+ 
++static void devm_mmc_host_release(struct device *dev, void *res)
++{
++      mmc_free_host(*(struct mmc_host **)res);
++}
++
++struct mmc_host *devm_mmc_alloc_host(struct device *dev, int extra)
++{
++      struct mmc_host **dr, *host;
++
++      dr = devres_alloc(devm_mmc_host_release, sizeof(*dr), GFP_KERNEL);
++      if (!dr)
++              return ERR_PTR(-ENOMEM);
++
++      host = mmc_alloc_host(extra, dev);
++      if (IS_ERR(host)) {
++              devres_free(dr);
++              return host;
++      }
++
++      *dr = host;
++      devres_add(dev, dr);
++
++      return host;
++}
++EXPORT_SYMBOL(devm_mmc_alloc_host);
++
+ static int mmc_validate_host_caps(struct mmc_host *host)
+ {
+       if (host->caps & MMC_CAP_SDIO_IRQ && !host->ops->enable_sdio_irq) {
+diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
+index 40d7e98fc9902..fb294cbb9081d 100644
+--- a/include/linux/mmc/host.h
++++ b/include/linux/mmc/host.h
+@@ -477,6 +477,7 @@ struct mmc_host {
+ struct device_node;
+ 
+ struct mmc_host *mmc_alloc_host(int extra, struct device *);
++struct mmc_host *devm_mmc_alloc_host(struct device *dev, int extra);
+ int mmc_add_host(struct mmc_host *);
+ void mmc_remove_host(struct mmc_host *);
+ void mmc_free_host(struct mmc_host *);
+-- 
+2.40.1
+

diff --git a/queue-5.10/mmc-meson-gx-fix-deferred-probing.patch b/queue-5.10/mmc-meson-gx-fix-deferred-probing.patch
new file mode 100644 (file)
index 0000000..44c01d7
--- /dev/null
+++ b/queue-5.10/mmc-meson-gx-fix-deferred-probing.patch
@@ -0,0 +1,45 @@
+From 50ab8ad92a0e39790264ef9e9123e2314d2a0f15 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Jun 2023 23:36:12 +0300
+Subject: mmc: meson-gx: fix deferred probing
+
+From: Sergey Shtylyov <s.shtylyov@omp.ru>
+
+[ Upstream commit b8ada54fa1b83f3b6480d4cced71354301750153 ]
+
+The driver overrides the error codes and IRQ0 returned by platform_get_irq()
+to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe
+permanently instead of the deferred probing. Switch to propagating the error
+codes upstream.  Since commit ce753ad1549c ("platform: finally disallow IRQ0
+in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs,
+so we now can safely ignore it...
+
+Fixes: cbcaac6d7dd2 ("mmc: meson-gx-mmc: Fix platform_get_irq's error checking")
+Cc: stable@vger.kernel.org # v5.19+
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://lore.kernel.org/r/20230617203622.6812-3-s.shtylyov@omp.ru
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/meson-gx-mmc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
+index 8a345ee2e6cf5..1992eea8b777e 100644
+--- a/drivers/mmc/host/meson-gx-mmc.c
++++ b/drivers/mmc/host/meson-gx-mmc.c
+@@ -1159,8 +1159,8 @@ static int meson_mmc_probe(struct platform_device *pdev)
+               return PTR_ERR(host->regs);
+ 
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0)
+-              return -EINVAL;
++      if (host->irq < 0)
++              return host->irq;
+ 
+       host->pinctrl = devm_pinctrl_get(&pdev->dev);
+       if (IS_ERR(host->pinctrl))
+-- 
+2.40.1
+

diff --git a/queue-5.10/mmc-meson-gx-use-devm_mmc_alloc_host.patch b/queue-5.10/mmc-meson-gx-use-devm_mmc_alloc_host.patch
new file mode 100644 (file)
index 0000000..7bf3d54
--- /dev/null
+++ b/queue-5.10/mmc-meson-gx-use-devm_mmc_alloc_host.patch
@@ -0,0 +1,131 @@
+From 9896479e57c022f519f097a73a0f8e61537ad401 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 4 Feb 2023 00:54:48 +0100
+Subject: mmc: meson-gx: use devm_mmc_alloc_host
+
+From: Heiner Kallweit <hkallweit1@gmail.com>
+
+[ Upstream commit 418f7c2de1334b70fbee790911a1b46503230137 ]
+
+Use new function devm_mmc_alloc_host() to simplify the code.
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Link: https://lore.kernel.org/r/728f159b-885f-c78a-1a3d-f55c245250e1@gmail.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Stable-dep-of: b8ada54fa1b8 ("mmc: meson-gx: fix deferred probing")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/meson-gx-mmc.c | 52 +++++++++++----------------------
+ 1 file changed, 17 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
+index e89bd6f4b317c..8a345ee2e6cf5 100644
+--- a/drivers/mmc/host/meson-gx-mmc.c
++++ b/drivers/mmc/host/meson-gx-mmc.c
+@@ -1122,7 +1122,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
+       struct mmc_host *mmc;
+       int ret;
+ 
+-      mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
++      mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct meson_host));
+       if (!mmc)
+               return -ENOMEM;
+       host = mmc_priv(mmc);
+@@ -1138,46 +1138,33 @@ static int meson_mmc_probe(struct platform_device *pdev)
+       host->vqmmc_enabled = false;
+       ret = mmc_regulator_get_supply(mmc);
+       if (ret)
+-              goto free_host;
++              return ret;
+ 
+       ret = mmc_of_parse(mmc);
+-      if (ret) {
+-              if (ret != -EPROBE_DEFER)
+-                      dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
+-              goto free_host;
+-      }
++      if (ret)
++              return dev_err_probe(&pdev->dev, ret, "error parsing DT\n");
+ 
+       host->data = (struct meson_mmc_data *)
+               of_device_get_match_data(&pdev->dev);
+-      if (!host->data) {
+-              ret = -EINVAL;
+-              goto free_host;
+-      }
++      if (!host->data)
++              return -EINVAL;
+ 
+       ret = device_reset_optional(&pdev->dev);
+-      if (ret) {
+-              dev_err_probe(&pdev->dev, ret, "device reset failed\n");
+-              goto free_host;
+-      }
++      if (ret)
++              return dev_err_probe(&pdev->dev, ret, "device reset failed\n");
+ 
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       host->regs = devm_ioremap_resource(&pdev->dev, res);
+-      if (IS_ERR(host->regs)) {
+-              ret = PTR_ERR(host->regs);
+-              goto free_host;
+-      }
++      if (IS_ERR(host->regs))
++              return PTR_ERR(host->regs);
+ 
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0) {
+-              ret = -EINVAL;
+-              goto free_host;
+-      }
++      if (host->irq <= 0)
++              return -EINVAL;
+ 
+       host->pinctrl = devm_pinctrl_get(&pdev->dev);
+-      if (IS_ERR(host->pinctrl)) {
+-              ret = PTR_ERR(host->pinctrl);
+-              goto free_host;
+-      }
++      if (IS_ERR(host->pinctrl))
++              return PTR_ERR(host->pinctrl);
+ 
+       host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
+                                                  "clk-gate");
+@@ -1188,14 +1175,12 @@ static int meson_mmc_probe(struct platform_device *pdev)
+       }
+ 
+       host->core_clk = devm_clk_get(&pdev->dev, "core");
+-      if (IS_ERR(host->core_clk)) {
+-              ret = PTR_ERR(host->core_clk);
+-              goto free_host;
+-      }
++      if (IS_ERR(host->core_clk))
++              return PTR_ERR(host->core_clk);
+ 
+       ret = clk_prepare_enable(host->core_clk);
+       if (ret)
+-              goto free_host;
++              return ret;
+ 
+       ret = meson_mmc_clk_init(host);
+       if (ret)
+@@ -1290,8 +1275,6 @@ static int meson_mmc_probe(struct platform_device *pdev)
+       clk_disable_unprepare(host->mmc_clk);
+ err_core_clk:
+       clk_disable_unprepare(host->core_clk);
+-free_host:
+-      mmc_free_host(mmc);
+       return ret;
+ }
+ 
+@@ -1315,7 +1298,6 @@ static int meson_mmc_remove(struct platform_device *pdev)
+       clk_disable_unprepare(host->mmc_clk);
+       clk_disable_unprepare(host->core_clk);
+ 
+-      mmc_free_host(host->mmc);
+       return 0;
+ }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch b/queue-5.10/mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch
new file mode 100644 (file)
index 0000000..674fc65
--- /dev/null
+++ b/queue-5.10/mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch
@@ -0,0 +1,155 @@
+From 190ad413be7d625a592278ab25ad5649e575b920 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Jun 2023 09:45:33 +0900
+Subject: mmc: sdhci-f-sdh30: Replace with sdhci_pltfm
+
+From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+[ Upstream commit 5def5c1c15bf22934ee227af85c1716762f3829f ]
+
+Even if sdhci_pltfm_pmops is specified for PM, this driver doesn't apply
+sdhci_pltfm, so the structure is not correctly referenced in PM functions.
+This applies sdhci_pltfm to this driver to fix this issue.
+
+- Call sdhci_pltfm_init() instead of sdhci_alloc_host() and
+  other functions that covered by sdhci_pltfm.
+- Move ops and quirks to sdhci_pltfm_data
+- Replace sdhci_priv() with own private function sdhci_f_sdh30_priv().
+
+Fixes: 87a507459f49 ("mmc: sdhci: host: add new f_sdh30")
+Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20230630004533.26644-1-hayashi.kunihiko@socionext.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci_f_sdh30.c | 60 ++++++++++++++------------------
+ 1 file changed, 27 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci_f_sdh30.c b/drivers/mmc/host/sdhci_f_sdh30.c
+index 6c4f43e112826..8876fd1c7eee0 100644
+--- a/drivers/mmc/host/sdhci_f_sdh30.c
++++ b/drivers/mmc/host/sdhci_f_sdh30.c
+@@ -26,9 +26,16 @@ struct f_sdhost_priv {
+       bool enable_cmd_dat_delay;
+ };
+ 
++static void *sdhci_f_sdhost_priv(struct sdhci_host *host)
++{
++      struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++
++      return sdhci_pltfm_priv(pltfm_host);
++}
++
+ static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
+ {
+-      struct f_sdhost_priv *priv = sdhci_priv(host);
++      struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
+       u32 ctrl = 0;
+ 
+       usleep_range(2500, 3000);
+@@ -61,7 +68,7 @@ static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
+ 
+ static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
+ {
+-      struct f_sdhost_priv *priv = sdhci_priv(host);
++      struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
+       u32 ctl;
+ 
+       if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
+@@ -85,30 +92,32 @@ static const struct sdhci_ops sdhci_f_sdh30_ops = {
+       .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+ 
++static const struct sdhci_pltfm_data sdhci_f_sdh30_pltfm_data = {
++      .ops = &sdhci_f_sdh30_ops,
++      .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
++              | SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
++      .quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE
++              |  SDHCI_QUIRK2_TUNING_WORK_AROUND,
++};
++
+ static int sdhci_f_sdh30_probe(struct platform_device *pdev)
+ {
+       struct sdhci_host *host;
+       struct device *dev = &pdev->dev;
+-      int irq, ctrl = 0, ret = 0;
++      int ctrl = 0, ret = 0;
+       struct f_sdhost_priv *priv;
++      struct sdhci_pltfm_host *pltfm_host;
+       u32 reg = 0;
+ 
+-      irq = platform_get_irq(pdev, 0);
+-      if (irq < 0)
+-              return irq;
+-
+-      host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
++      host = sdhci_pltfm_init(pdev, &sdhci_f_sdh30_pltfm_data,
++                              sizeof(struct f_sdhost_priv));
+       if (IS_ERR(host))
+               return PTR_ERR(host);
+ 
+-      priv = sdhci_priv(host);
++      pltfm_host = sdhci_priv(host);
++      priv = sdhci_pltfm_priv(pltfm_host);
+       priv->dev = dev;
+ 
+-      host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+-                     SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+-      host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
+-                      SDHCI_QUIRK2_TUNING_WORK_AROUND;
+-
+       priv->enable_cmd_dat_delay = device_property_read_bool(dev,
+                                               "fujitsu,cmd-dat-delay-select");
+ 
+@@ -116,18 +125,6 @@ static int sdhci_f_sdh30_probe(struct platform_device *pdev)
+       if (ret)
+               goto err;
+ 
+-      platform_set_drvdata(pdev, host);
+-
+-      host->hw_name = "f_sdh30";
+-      host->ops = &sdhci_f_sdh30_ops;
+-      host->irq = irq;
+-
+-      host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
+-      if (IS_ERR(host->ioaddr)) {
+-              ret = PTR_ERR(host->ioaddr);
+-              goto err;
+-      }
+-
+       if (dev_of_node(dev)) {
+               sdhci_get_of_property(pdev);
+ 
+@@ -182,23 +179,20 @@ static int sdhci_f_sdh30_probe(struct platform_device *pdev)
+ err_clk:
+       clk_disable_unprepare(priv->clk_iface);
+ err:
+-      sdhci_free_host(host);
++      sdhci_pltfm_free(pdev);
++
+       return ret;
+ }
+ 
+ static int sdhci_f_sdh30_remove(struct platform_device *pdev)
+ {
+       struct sdhci_host *host = platform_get_drvdata(pdev);
+-      struct f_sdhost_priv *priv = sdhci_priv(host);
+-
+-      sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
+-                        0xffffffff);
++      struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
+ 
+       clk_disable_unprepare(priv->clk_iface);
+       clk_disable_unprepare(priv->clk);
+ 
+-      sdhci_free_host(host);
+-      platform_set_drvdata(pdev, NULL);
++      sdhci_pltfm_unregister(pdev);
+ 
+       return 0;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.10/mmc-sdhci-spear-fix-deferred-probing.patch b/queue-5.10/mmc-sdhci-spear-fix-deferred-probing.patch
new file mode 100644 (file)
index 0000000..2864851
--- /dev/null
+++ b/queue-5.10/mmc-sdhci-spear-fix-deferred-probing.patch
@@ -0,0 +1,46 @@
+From 2fbe19a7beef7514ea9bdafdb10fbd77f66ea4b3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Jun 2023 23:36:19 +0300
+Subject: mmc: sdhci-spear: fix deferred probing
+
+From: Sergey Shtylyov <s.shtylyov@omp.ru>
+
+[ Upstream commit 8d0caeedcd05a721f3cc2537b0ea212ec4027307 ]
+
+The driver overrides the error codes and IRQ0 returned by platform_get_irq()
+to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe
+permanently instead of the deferred probing. Switch to propagating the error
+codes upstream.  Since commit ce753ad1549c ("platform: finally disallow IRQ0
+in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs,
+so we now can safely ignore it...
+
+Fixes: 682798a596a6 ("mmc: sdhci-spear: Handle return value of platform_get_irq")
+Cc: stable@vger.kernel.org # v5.19+
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/20230617203622.6812-10-s.shtylyov@omp.ru
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci-spear.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci-spear.c b/drivers/mmc/host/sdhci-spear.c
+index d463e2fd5b1a8..c79035727b20b 100644
+--- a/drivers/mmc/host/sdhci-spear.c
++++ b/drivers/mmc/host/sdhci-spear.c
+@@ -65,8 +65,8 @@ static int sdhci_probe(struct platform_device *pdev)
+       host->hw_name = "sdhci";
+       host->ops = &sdhci_pltfm_ops;
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0) {
+-              ret = -EINVAL;
++      if (host->irq < 0) {
++              ret = host->irq;
+               goto err_host;
+       }
+       host->quirks = SDHCI_QUIRK_BROKEN_ADMA;
+-- 
+2.40.1
+

diff --git a/queue-5.10/mmc-sunxi-fix-deferred-probing.patch b/queue-5.10/mmc-sunxi-fix-deferred-probing.patch
new file mode 100644 (file)
index 0000000..49d8835
--- /dev/null
+++ b/queue-5.10/mmc-sunxi-fix-deferred-probing.patch
@@ -0,0 +1,45 @@
+From 58b2855b1f4c56cca8f407edcdac8da73fdd5c15 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 17 Jun 2023 23:36:21 +0300
+Subject: mmc: sunxi: fix deferred probing
+
+From: Sergey Shtylyov <s.shtylyov@omp.ru>
+
+[ Upstream commit c2df53c5806cfd746dae08e07bc8c4ad247c3b70 ]
+
+The driver overrides the error codes and IRQ0 returned by platform_get_irq()
+to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe
+permanently instead of the deferred probing. Switch to propagating the error
+codes upstream.  Since commit ce753ad1549c ("platform: finally disallow IRQ0
+in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs,
+so we now can safely ignore it...
+
+Fixes: 2408a08583d2 ("mmc: sunxi-mmc: Handle return value of platform_get_irq")
+Cc: stable@vger.kernel.org # v5.19+
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Link: https://lore.kernel.org/r/20230617203622.6812-12-s.shtylyov@omp.ru
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sunxi-mmc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 9215069c61560..b834fde3f9eda 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1317,8 +1317,8 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
+               return ret;
+ 
+       host->irq = platform_get_irq(pdev, 0);
+-      if (host->irq <= 0) {
+-              ret = -EINVAL;
++      if (host->irq < 0) {
++              ret = host->irq;
+               goto error_disable_mmc;
+       }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/net-mlx5-move-all-internal-timer-metadata-into-a-ded.patch b/queue-5.10/net-mlx5-move-all-internal-timer-metadata-into-a-ded.patch
new file mode 100644 (file)
index 0000000..350c4e6
--- /dev/null
+++ b/queue-5.10/net-mlx5-move-all-internal-timer-metadata-into-a-ded.patch
@@ -0,0 +1,367 @@
+From 3c0d76995a8c3f26ad43dea1c411c626aa169880 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 12 Feb 2021 14:30:40 -0800
+Subject: net/mlx5: Move all internal timer metadata into a dedicated struct
+
+From: Eran Ben Elisha <eranbe@mellanox.com>
+
+[ Upstream commit d6f3dc8f509ce6288e2537eb4b0614ef444fd84a ]
+
+Internal timer mode (SW clock) requires some PTP clock related metadata
+structs. Real time mode (HW clock) will not need these metadata structs.
+This separation emphasize the different interfaces for HW clock and SW
+clock.
+
+Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
+Signed-off-by: Aya Levin <ayal@nvidia.com>
+Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
+Stable-dep-of: d00620762565 ("net/mlx5: Skip clock update work when device is in error state")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../ethernet/mellanox/mlx5/core/lib/clock.c   | 107 ++++++++++--------
+ .../ethernet/mellanox/mlx5/core/lib/clock.h   |   3 +-
+ include/linux/mlx5/driver.h                   |  12 +-
+ 3 files changed, 71 insertions(+), 51 deletions(-)
+
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+index 3fbceb4af54e4..01b8a9648b16f 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+@@ -89,7 +89,8 @@ static u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
+ 
+ static u64 read_internal_timer(const struct cyclecounter *cc)
+ {
+-      struct mlx5_clock *clock = container_of(cc, struct mlx5_clock, cycles);
++      struct mlx5_timer *timer = container_of(cc, struct mlx5_timer, cycles);
++      struct mlx5_clock *clock = container_of(timer, struct mlx5_clock, timer);
+       struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev,
+                                                 clock);
+ 
+@@ -100,6 +101,7 @@ static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev)
+ {
+       struct mlx5_ib_clock_info *clock_info = mdev->clock_info;
+       struct mlx5_clock *clock = &mdev->clock;
++      struct mlx5_timer *timer;
+       u32 sign;
+ 
+       if (!clock_info)
+@@ -109,10 +111,11 @@ static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev)
+       smp_store_mb(clock_info->sign,
+                    sign | MLX5_IB_CLOCK_INFO_KERNEL_UPDATING);
+ 
+-      clock_info->cycles = clock->tc.cycle_last;
+-      clock_info->mult   = clock->cycles.mult;
+-      clock_info->nsec   = clock->tc.nsec;
+-      clock_info->frac   = clock->tc.frac;
++      timer = &clock->timer;
++      clock_info->cycles = timer->tc.cycle_last;
++      clock_info->mult   = timer->cycles.mult;
++      clock_info->nsec   = timer->tc.nsec;
++      clock_info->frac   = timer->tc.frac;
+ 
+       smp_store_release(&clock_info->sign,
+                         sign + MLX5_IB_CLOCK_INFO_KERNEL_UPDATING * 2);
+@@ -151,28 +154,32 @@ static void mlx5_timestamp_overflow(struct work_struct *work)
+ {
+       struct delayed_work *dwork = to_delayed_work(work);
+       struct mlx5_core_dev *mdev;
++      struct mlx5_timer *timer;
+       struct mlx5_clock *clock;
+       unsigned long flags;
+ 
+-      clock = container_of(dwork, struct mlx5_clock, overflow_work);
++      timer = container_of(dwork, struct mlx5_timer, overflow_work);
++      clock = container_of(timer, struct mlx5_clock, timer);
+       mdev = container_of(clock, struct mlx5_core_dev, clock);
++
+       write_seqlock_irqsave(&clock->lock, flags);
+-      timecounter_read(&clock->tc);
++      timecounter_read(&timer->tc);
+       mlx5_update_clock_info_page(mdev);
+       write_sequnlock_irqrestore(&clock->lock, flags);
+-      schedule_delayed_work(&clock->overflow_work, clock->overflow_period);
++      schedule_delayed_work(&timer->overflow_work, timer->overflow_period);
+ }
+ 
+ static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts)
+ {
+       struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
++      struct mlx5_timer *timer = &clock->timer;
+       u64 ns = timespec64_to_ns(ts);
+       struct mlx5_core_dev *mdev;
+       unsigned long flags;
+ 
+       mdev = container_of(clock, struct mlx5_core_dev, clock);
+       write_seqlock_irqsave(&clock->lock, flags);
+-      timecounter_init(&clock->tc, &clock->cycles, ns);
++      timecounter_init(&timer->tc, &timer->cycles, ns);
+       mlx5_update_clock_info_page(mdev);
+       write_sequnlock_irqrestore(&clock->lock, flags);
+ 
+@@ -183,6 +190,7 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
+                            struct ptp_system_timestamp *sts)
+ {
+       struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
++      struct mlx5_timer *timer = &clock->timer;
+       struct mlx5_core_dev *mdev;
+       unsigned long flags;
+       u64 cycles, ns;
+@@ -190,7 +198,7 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
+       mdev = container_of(clock, struct mlx5_core_dev, clock);
+       write_seqlock_irqsave(&clock->lock, flags);
+       cycles = mlx5_read_internal_timer(mdev, sts);
+-      ns = timecounter_cyc2time(&clock->tc, cycles);
++      ns = timecounter_cyc2time(&timer->tc, cycles);
+       write_sequnlock_irqrestore(&clock->lock, flags);
+ 
+       *ts = ns_to_timespec64(ns);
+@@ -201,12 +209,13 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
+ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+ {
+       struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
++      struct mlx5_timer *timer = &clock->timer;
+       struct mlx5_core_dev *mdev;
+       unsigned long flags;
+ 
+       mdev = container_of(clock, struct mlx5_core_dev, clock);
+       write_seqlock_irqsave(&clock->lock, flags);
+-      timecounter_adjtime(&clock->tc, delta);
++      timecounter_adjtime(&timer->tc, delta);
+       mlx5_update_clock_info_page(mdev);
+       write_sequnlock_irqrestore(&clock->lock, flags);
+ 
+@@ -216,27 +225,27 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+ static int mlx5_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
+ {
+       struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
++      struct mlx5_timer *timer = &clock->timer;
+       struct mlx5_core_dev *mdev;
+       unsigned long flags;
+       int neg_adj = 0;
+       u32 diff;
+       u64 adj;
+ 
+-
+       if (delta < 0) {
+               neg_adj = 1;
+               delta = -delta;
+       }
+ 
+-      adj = clock->nominal_c_mult;
++      adj = timer->nominal_c_mult;
+       adj *= delta;
+       diff = div_u64(adj, 1000000000ULL);
+ 
+       mdev = container_of(clock, struct mlx5_core_dev, clock);
+       write_seqlock_irqsave(&clock->lock, flags);
+-      timecounter_read(&clock->tc);
+-      clock->cycles.mult = neg_adj ? clock->nominal_c_mult - diff :
+-                                     clock->nominal_c_mult + diff;
++      timecounter_read(&timer->tc);
++      timer->cycles.mult = neg_adj ? timer->nominal_c_mult - diff :
++                                     timer->nominal_c_mult + diff;
+       mlx5_update_clock_info_page(mdev);
+       write_sequnlock_irqrestore(&clock->lock, flags);
+ 
+@@ -313,6 +322,7 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp,
+                       container_of(ptp, struct mlx5_clock, ptp_info);
+       struct mlx5_core_dev *mdev =
+                       container_of(clock, struct mlx5_core_dev, clock);
++      struct mlx5_timer *timer = &clock->timer;
+       u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
+       u64 nsec_now, nsec_delta, time_stamp = 0;
+       u64 cycles_now, cycles_delta;
+@@ -355,10 +365,10 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp,
+               ns = timespec64_to_ns(&ts);
+               cycles_now = mlx5_read_internal_timer(mdev, NULL);
+               write_seqlock_irqsave(&clock->lock, flags);
+-              nsec_now = timecounter_cyc2time(&clock->tc, cycles_now);
++              nsec_now = timecounter_cyc2time(&timer->tc, cycles_now);
+               nsec_delta = ns - nsec_now;
+-              cycles_delta = div64_u64(nsec_delta << clock->cycles.shift,
+-                                       clock->cycles.mult);
++              cycles_delta = div64_u64(nsec_delta << timer->cycles.shift,
++                                       timer->cycles.mult);
+               write_sequnlock_irqrestore(&clock->lock, flags);
+               time_stamp = cycles_now + cycles_delta;
+               field_select = MLX5_MTPPS_FS_PIN_MODE |
+@@ -541,6 +551,7 @@ static int mlx5_pps_event(struct notifier_block *nb,
+                         unsigned long type, void *data)
+ {
+       struct mlx5_clock *clock = mlx5_nb_cof(nb, struct mlx5_clock, pps_nb);
++      struct mlx5_timer *timer = &clock->timer;
+       struct ptp_clock_event ptp_event;
+       u64 cycles_now, cycles_delta;
+       u64 nsec_now, nsec_delta, ns;
+@@ -575,10 +586,10 @@ static int mlx5_pps_event(struct notifier_block *nb,
+               ts.tv_nsec = 0;
+               ns = timespec64_to_ns(&ts);
+               write_seqlock_irqsave(&clock->lock, flags);
+-              nsec_now = timecounter_cyc2time(&clock->tc, cycles_now);
++              nsec_now = timecounter_cyc2time(&timer->tc, cycles_now);
+               nsec_delta = ns - nsec_now;
+-              cycles_delta = div64_u64(nsec_delta << clock->cycles.shift,
+-                                       clock->cycles.mult);
++              cycles_delta = div64_u64(nsec_delta << timer->cycles.shift,
++                                       timer->cycles.mult);
+               clock->pps_info.start[pin] = cycles_now + cycles_delta;
+               write_sequnlock_irqrestore(&clock->lock, flags);
+               schedule_work(&clock->pps_info.out_work);
+@@ -594,17 +605,18 @@ static int mlx5_pps_event(struct notifier_block *nb,
+ static void mlx5_timecounter_init(struct mlx5_core_dev *mdev)
+ {
+       struct mlx5_clock *clock = &mdev->clock;
++      struct mlx5_timer *timer = &clock->timer;
+       u32 dev_freq;
+ 
+       dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz);
+-      clock->cycles.read = read_internal_timer;
+-      clock->cycles.shift = MLX5_CYCLES_SHIFT;
+-      clock->cycles.mult = clocksource_khz2mult(dev_freq,
+-                                                clock->cycles.shift);
+-      clock->nominal_c_mult = clock->cycles.mult;
+-      clock->cycles.mask = CLOCKSOURCE_MASK(41);
+-
+-      timecounter_init(&clock->tc, &clock->cycles,
++      timer->cycles.read = read_internal_timer;
++      timer->cycles.shift = MLX5_CYCLES_SHIFT;
++      timer->cycles.mult = clocksource_khz2mult(dev_freq,
++                                                timer->cycles.shift);
++      timer->nominal_c_mult = timer->cycles.mult;
++      timer->cycles.mask = CLOCKSOURCE_MASK(41);
++
++      timecounter_init(&timer->tc, &timer->cycles,
+                        ktime_to_ns(ktime_get_real()));
+ }
+ 
+@@ -612,6 +624,7 @@ static void mlx5_init_overflow_period(struct mlx5_clock *clock)
+ {
+       struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock);
+       struct mlx5_ib_clock_info *clock_info = mdev->clock_info;
++      struct mlx5_timer *timer = &clock->timer;
+       u64 overflow_cycles;
+       u64 frac = 0;
+       u64 ns;
+@@ -623,29 +636,30 @@ static void mlx5_init_overflow_period(struct mlx5_clock *clock)
+        * multiplied by clock multiplier where the result doesn't exceed
+        * 64bits.
+        */
+-      overflow_cycles = div64_u64(~0ULL >> 1, clock->cycles.mult);
+-      overflow_cycles = min(overflow_cycles, div_u64(clock->cycles.mask, 3));
++      overflow_cycles = div64_u64(~0ULL >> 1, timer->cycles.mult);
++      overflow_cycles = min(overflow_cycles, div_u64(timer->cycles.mask, 3));
+ 
+-      ns = cyclecounter_cyc2ns(&clock->cycles, overflow_cycles,
++      ns = cyclecounter_cyc2ns(&timer->cycles, overflow_cycles,
+                                frac, &frac);
+       do_div(ns, NSEC_PER_SEC / HZ);
+-      clock->overflow_period = ns;
++      timer->overflow_period = ns;
+ 
+-      INIT_DELAYED_WORK(&clock->overflow_work, mlx5_timestamp_overflow);
+-      if (clock->overflow_period)
+-              schedule_delayed_work(&clock->overflow_work, 0);
++      INIT_DELAYED_WORK(&timer->overflow_work, mlx5_timestamp_overflow);
++      if (timer->overflow_period)
++              schedule_delayed_work(&timer->overflow_work, 0);
+       else
+               mlx5_core_warn(mdev,
+                              "invalid overflow period, overflow_work is not scheduled\n");
+ 
+       if (clock_info)
+-              clock_info->overflow_period = clock->overflow_period;
++              clock_info->overflow_period = timer->overflow_period;
+ }
+ 
+ static void mlx5_init_clock_info(struct mlx5_core_dev *mdev)
+ {
+       struct mlx5_clock *clock = &mdev->clock;
+       struct mlx5_ib_clock_info *info;
++      struct mlx5_timer *timer;
+ 
+       mdev->clock_info = (struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL);
+       if (!mdev->clock_info) {
+@@ -654,13 +668,14 @@ static void mlx5_init_clock_info(struct mlx5_core_dev *mdev)
+       }
+ 
+       info = mdev->clock_info;
+-
+-      info->nsec = clock->tc.nsec;
+-      info->cycles = clock->tc.cycle_last;
+-      info->mask = clock->cycles.mask;
+-      info->mult = clock->nominal_c_mult;
+-      info->shift = clock->cycles.shift;
+-      info->frac = clock->tc.frac;
++      timer = &clock->timer;
++
++      info->nsec = timer->tc.nsec;
++      info->cycles = timer->tc.cycle_last;
++      info->mask = timer->cycles.mask;
++      info->mult = timer->nominal_c_mult;
++      info->shift = timer->cycles.shift;
++      info->frac = timer->tc.frac;
+ }
+ 
+ void mlx5_init_clock(struct mlx5_core_dev *mdev)
+@@ -714,7 +729,7 @@ void mlx5_cleanup_clock(struct mlx5_core_dev *mdev)
+       }
+ 
+       cancel_work_sync(&clock->pps_info.out_work);
+-      cancel_delayed_work_sync(&clock->overflow_work);
++      cancel_delayed_work_sync(&clock->timer.overflow_work);
+ 
+       if (mdev->clock_info) {
+               free_page((unsigned long)mdev->clock_info);
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h
+index 31600924bdc36..6e8804ebc773b 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h
++++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h
+@@ -45,12 +45,13 @@ static inline int mlx5_clock_get_ptp_index(struct mlx5_core_dev *mdev)
+ static inline ktime_t mlx5_timecounter_cyc2time(struct mlx5_clock *clock,
+                                               u64 timestamp)
+ {
++      struct mlx5_timer *timer = &clock->timer;
+       unsigned int seq;
+       u64 nsec;
+ 
+       do {
+               seq = read_seqbegin(&clock->lock);
+-              nsec = timecounter_cyc2time(&clock->tc, timestamp);
++              nsec = timecounter_cyc2time(&timer->tc, timestamp);
+       } while (read_seqretry(&clock->lock, seq));
+ 
+       return ns_to_ktime(nsec);
+diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
+index ae88362216a4e..4f95b98215d81 100644
+--- a/include/linux/mlx5/driver.h
++++ b/include/linux/mlx5/driver.h
+@@ -644,18 +644,22 @@ struct mlx5_pps {
+       u8                         enabled;
+ };
+ 
+-struct mlx5_clock {
+-      struct mlx5_nb             pps_nb;
+-      seqlock_t                  lock;
++struct mlx5_timer {
+       struct cyclecounter        cycles;
+       struct timecounter         tc;
+-      struct hwtstamp_config     hwtstamp_config;
+       u32                        nominal_c_mult;
+       unsigned long              overflow_period;
+       struct delayed_work        overflow_work;
++};
++
++struct mlx5_clock {
++      struct mlx5_nb             pps_nb;
++      seqlock_t                  lock;
++      struct hwtstamp_config     hwtstamp_config;
+       struct ptp_clock          *ptp;
+       struct ptp_clock_info      ptp_info;
+       struct mlx5_pps            pps_info;
++      struct mlx5_timer          timer;
+ };
+ 
+ struct mlx5_dm;
+-- 
+2.40.1
+

diff --git a/queue-5.10/net-mlx5-refactor-init-clock-function.patch b/queue-5.10/net-mlx5-refactor-init-clock-function.patch
new file mode 100644 (file)
index 0000000..d3259b1
--- /dev/null
+++ b/queue-5.10/net-mlx5-refactor-init-clock-function.patch
@@ -0,0 +1,136 @@
+From 17f3150264b9608582bd273bdd6827d12ec8e11b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 12 Feb 2021 14:30:39 -0800
+Subject: net/mlx5: Refactor init clock function
+
+From: Eran Ben Elisha <eranbe@mellanox.com>
+
+[ Upstream commit 1436de0b991548fd859a00c889b8c4dcbbb5f463 ]
+
+Function mlx5_init_clock() is responsible for internal PTP related metadata
+initializations. Break mlx5_init_clock() to sub functions, each takes care
+of its own logic.
+
+Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
+Signed-off-by: Aya Levin <ayal@nvidia.com>
+Reviewed-by: Moshe Shemesh <moshe@mellanox.com>
+Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
+Stable-dep-of: d00620762565 ("net/mlx5: Skip clock update work when device is in error state")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../ethernet/mellanox/mlx5/core/lib/clock.c   | 76 +++++++++++++------
+ 1 file changed, 53 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+index 44a434b1178b5..3fbceb4af54e4 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+@@ -591,20 +591,12 @@ static int mlx5_pps_event(struct notifier_block *nb,
+       return NOTIFY_OK;
+ }
+ 
+-void mlx5_init_clock(struct mlx5_core_dev *mdev)
++static void mlx5_timecounter_init(struct mlx5_core_dev *mdev)
+ {
+       struct mlx5_clock *clock = &mdev->clock;
+-      u64 overflow_cycles;
+-      u64 ns;
+-      u64 frac = 0;
+       u32 dev_freq;
+ 
+       dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz);
+-      if (!dev_freq) {
+-              mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n");
+-              return;
+-      }
+-      seqlock_init(&clock->lock);
+       clock->cycles.read = read_internal_timer;
+       clock->cycles.shift = MLX5_CYCLES_SHIFT;
+       clock->cycles.mult = clocksource_khz2mult(dev_freq,
+@@ -614,6 +606,15 @@ void mlx5_init_clock(struct mlx5_core_dev *mdev)
+ 
+       timecounter_init(&clock->tc, &clock->cycles,
+                        ktime_to_ns(ktime_get_real()));
++}
++
++static void mlx5_init_overflow_period(struct mlx5_clock *clock)
++{
++      struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock);
++      struct mlx5_ib_clock_info *clock_info = mdev->clock_info;
++      u64 overflow_cycles;
++      u64 frac = 0;
++      u64 ns;
+ 
+       /* Calculate period in seconds to call the overflow watchdog - to make
+        * sure counter is checked at least twice every wrap around.
+@@ -630,24 +631,53 @@ void mlx5_init_clock(struct mlx5_core_dev *mdev)
+       do_div(ns, NSEC_PER_SEC / HZ);
+       clock->overflow_period = ns;
+ 
+-      mdev->clock_info =
+-              (struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL);
+-      if (mdev->clock_info) {
+-              mdev->clock_info->nsec = clock->tc.nsec;
+-              mdev->clock_info->cycles = clock->tc.cycle_last;
+-              mdev->clock_info->mask = clock->cycles.mask;
+-              mdev->clock_info->mult = clock->nominal_c_mult;
+-              mdev->clock_info->shift = clock->cycles.shift;
+-              mdev->clock_info->frac = clock->tc.frac;
+-              mdev->clock_info->overflow_period = clock->overflow_period;
+-      }
+-
+-      INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out);
+       INIT_DELAYED_WORK(&clock->overflow_work, mlx5_timestamp_overflow);
+       if (clock->overflow_period)
+               schedule_delayed_work(&clock->overflow_work, 0);
+       else
+-              mlx5_core_warn(mdev, "invalid overflow period, overflow_work is not scheduled\n");
++              mlx5_core_warn(mdev,
++                             "invalid overflow period, overflow_work is not scheduled\n");
++
++      if (clock_info)
++              clock_info->overflow_period = clock->overflow_period;
++}
++
++static void mlx5_init_clock_info(struct mlx5_core_dev *mdev)
++{
++      struct mlx5_clock *clock = &mdev->clock;
++      struct mlx5_ib_clock_info *info;
++
++      mdev->clock_info = (struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL);
++      if (!mdev->clock_info) {
++              mlx5_core_warn(mdev, "Failed to allocate IB clock info page\n");
++              return;
++      }
++
++      info = mdev->clock_info;
++
++      info->nsec = clock->tc.nsec;
++      info->cycles = clock->tc.cycle_last;
++      info->mask = clock->cycles.mask;
++      info->mult = clock->nominal_c_mult;
++      info->shift = clock->cycles.shift;
++      info->frac = clock->tc.frac;
++}
++
++void mlx5_init_clock(struct mlx5_core_dev *mdev)
++{
++      struct mlx5_clock *clock = &mdev->clock;
++
++      if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) {
++              mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n");
++              return;
++      }
++
++      seqlock_init(&clock->lock);
++
++      mlx5_timecounter_init(mdev);
++      mlx5_init_clock_info(mdev);
++      mlx5_init_overflow_period(clock);
++      INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out);
+ 
+       /* Configure the PHC */
+       clock->ptp_info = mlx5_ptp_clock_info;
+-- 
+2.40.1
+

diff --git a/queue-5.10/net-mlx5-skip-clock-update-work-when-device-is-in-er.patch b/queue-5.10/net-mlx5-skip-clock-update-work-when-device-is-in-er.patch
new file mode 100644 (file)
index 0000000..94ecf84
--- /dev/null
+++ b/queue-5.10/net-mlx5-skip-clock-update-work-when-device-is-in-er.patch
@@ -0,0 +1,49 @@
+From e51c259f9895290fa3627e13d3a941111857a211 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 19 Jul 2023 11:33:44 +0300
+Subject: net/mlx5: Skip clock update work when device is in error state
+
+From: Moshe Shemesh <moshe@nvidia.com>
+
+[ Upstream commit d006207625657322ba8251b6e7e829f9659755dc ]
+
+When device is in error state, marked by the flag
+MLX5_DEVICE_STATE_INTERNAL_ERROR, the HW and PCI may not be accessible
+and so clock update work should be skipped. Furthermore, such access
+through PCI in error state, after calling mlx5_pci_disable_device() can
+result in failing to recover from pci errors.
+
+Fixes: ef9814deafd0 ("net/mlx5e: Add HW timestamping (TS) support")
+Reported-and-tested-by: Ganesh G R <ganeshgr@linux.ibm.com>
+Closes: https://lore.kernel.org/netdev/9bdb9b9d-140a-7a28-f0de-2e64e873c068@nvidia.com
+Signed-off-by: Moshe Shemesh <moshe@nvidia.com>
+Reviewed-by: Aya Levin <ayal@nvidia.com>
+Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+index 01b8a9648b16f..80dee8c692495 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+@@ -162,10 +162,15 @@ static void mlx5_timestamp_overflow(struct work_struct *work)
+       clock = container_of(timer, struct mlx5_clock, timer);
+       mdev = container_of(clock, struct mlx5_core_dev, clock);
+ 
++      if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
++              goto out;
++
+       write_seqlock_irqsave(&clock->lock, flags);
+       timecounter_read(&timer->tc);
+       mlx5_update_clock_info_page(mdev);
+       write_sequnlock_irqrestore(&clock->lock, flags);
++
++out:
+       schedule_delayed_work(&timer->overflow_work, timer->overflow_period);
+ }
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch b/queue-5.10/net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch
new file mode 100644 (file)
index 0000000..33d0df4
--- /dev/null
+++ b/queue-5.10/net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch
@@ -0,0 +1,55 @@
+From b1a4c95a08e679b7e62bdc1e163b02453de7a0f0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Jun 2023 18:17:42 +0300
+Subject: net/ncsi: change from ndo_set_mac_address to dev_set_mac_address
+
+From: Ivan Mikhaylov <fr0st61te@gmail.com>
+
+[ Upstream commit 790071347a0a1a89e618eedcd51c687ea783aeb3 ]
+
+Change ndo_set_mac_address to dev_set_mac_address because
+dev_set_mac_address provides a way to notify network layer about MAC
+change. In other case, services may not aware about MAC change and keep
+using old one which set from network adapter driver.
+
+As example, DHCP client from systemd do not update MAC address without
+notification from net subsystem which leads to the problem with acquiring
+the right address from DHCP server.
+
+Fixes: cb10c7c0dfd9e ("net/ncsi: Add NCSI Broadcom OEM command")
+Cc: stable@vger.kernel.org # v6.0+ 2f38e84 net/ncsi: make one oem_gma function for all mfr id
+Signed-off-by: Paul Fertser <fercerpav@gmail.com>
+Signed-off-by: Ivan Mikhaylov <fr0st61te@gmail.com>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/ncsi/ncsi-rsp.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/net/ncsi/ncsi-rsp.c b/net/ncsi/ncsi-rsp.c
+index 888ccc2d4e34b..47ffb790ff99f 100644
+--- a/net/ncsi/ncsi-rsp.c
++++ b/net/ncsi/ncsi-rsp.c
+@@ -616,7 +616,6 @@ static int ncsi_rsp_handler_oem_mlx_gma(struct ncsi_request *nr)
+ {
+       struct ncsi_dev_priv *ndp = nr->ndp;
+       struct net_device *ndev = ndp->ndev.dev;
+-      const struct net_device_ops *ops = ndev->netdev_ops;
+       struct ncsi_rsp_oem_pkt *rsp;
+       struct sockaddr saddr;
+       int ret = 0;
+@@ -630,7 +629,9 @@ static int ncsi_rsp_handler_oem_mlx_gma(struct ncsi_request *nr)
+       /* Set the flag for GMA command which should only be called once */
+       ndp->gma_flag = 1;
+ 
+-      ret = ops->ndo_set_mac_address(ndev, &saddr);
++      rtnl_lock();
++      ret = dev_set_mac_address(ndev, &saddr, NULL);
++      rtnl_unlock();
+       if (ret < 0)
+               netdev_warn(ndev, "NCSI: 'Writing mac address to device failed\n");
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch b/queue-5.10/ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch
new file mode 100644 (file)
index 0000000..6f50679
--- /dev/null
+++ b/queue-5.10/ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch
@@ -0,0 +1,61 @@
+From 6e523f1a28186b6afd4f43cc2ad3d4fc22340854 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 13 Jun 2023 10:13:37 +0200
+Subject: ovl: check type and offset of struct vfsmount in ovl_entry
+
+From: Christian Brauner <brauner@kernel.org>
+
+[ Upstream commit f723edb8a532cd26e1ff0a2b271d73762d48f762 ]
+
+Porting overlayfs to the new amount api I started experiencing random
+crashes that couldn't be explained easily. So after much debugging and
+reasoning it became clear that struct ovl_entry requires the point to
+struct vfsmount to be the first member and of type struct vfsmount.
+
+During the port I added a new member at the beginning of struct
+ovl_entry which broke all over the place in the form of random crashes
+and cache corruptions. While there's a comment in ovl_free_fs() to the
+effect of "Hack! Reuse ofs->layers as a vfsmount array before freeing
+it" there's no such comment on struct ovl_entry which makes this easy to
+trip over.
+
+Add a comment and two static asserts for both the offset and the type of
+pointer in struct ovl_entry.
+
+Signed-off-by: Christian Brauner <brauner@kernel.org>
+Signed-off-by: Amir Goldstein <amir73il@gmail.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/overlayfs/ovl_entry.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/fs/overlayfs/ovl_entry.h b/fs/overlayfs/ovl_entry.h
+index b208eba5d0b64..b58a0140d78d5 100644
+--- a/fs/overlayfs/ovl_entry.h
++++ b/fs/overlayfs/ovl_entry.h
+@@ -30,6 +30,7 @@ struct ovl_sb {
+ };
+ 
+ struct ovl_layer {
++      /* ovl_free_fs() relies on @mnt being the first member! */
+       struct vfsmount *mnt;
+       /* Trap in ovl inode cache */
+       struct inode *trap;
+@@ -40,6 +41,14 @@ struct ovl_layer {
+       int fsid;
+ };
+ 
++/*
++ * ovl_free_fs() relies on @mnt being the first member when unmounting
++ * the private mounts created for each layer. Let's check both the
++ * offset and type.
++ */
++static_assert(offsetof(struct ovl_layer, mnt) == 0);
++static_assert(__same_type(typeof_member(struct ovl_layer, mnt), struct vfsmount *));
++
+ struct ovl_path {
+       const struct ovl_layer *layer;
+       struct dentry *dentry;
+-- 
+2.40.1
+

diff --git a/queue-5.10/pci-tegra194-fix-possible-array-out-of-bounds-access.patch b/queue-5.10/pci-tegra194-fix-possible-array-out-of-bounds-access.patch
new file mode 100644 (file)
index 0000000..623ae42
--- /dev/null
+++ b/queue-5.10/pci-tegra194-fix-possible-array-out-of-bounds-access.patch
@@ -0,0 +1,66 @@
+From 0c70b58a91b9cf5d788005fabb0eaec6b2fa3809 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 May 2023 23:02:09 +0530
+Subject: PCI: tegra194: Fix possible array out of bounds access
+
+From: Sumit Gupta <sumitg@nvidia.com>
+
+[ Upstream commit 205b3d02d57ce6dce96f6d2b9c230f56a9bf9817 ]
+
+Add check to fix the possible array out of bounds violation by
+making speed equal to GEN1_CORE_CLK_FREQ when its value is more
+than the size of "pcie_gen_freq" array. This array has size of
+four but possible speed (CLS) values are from "0 to 0xF". So,
+"speed - 1" values are "-1 to 0xE".
+
+Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
+Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
+Link: https://lore.kernel.org/lkml/72b9168b-d4d6-4312-32ea-69358df2f2d0@nvidia.com/
+Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
+index 1222f5749bc67..a215777df96c7 100644
+--- a/drivers/pci/controller/dwc/pcie-tegra194.c
++++ b/drivers/pci/controller/dwc/pcie-tegra194.c
+@@ -239,6 +239,7 @@
+ #define EP_STATE_ENABLED      1
+ 
+ static const unsigned int pcie_gen_freq[] = {
++      GEN1_CORE_CLK_FREQ,     /* PCI_EXP_LNKSTA_CLS == 0; undefined */
+       GEN1_CORE_CLK_FREQ,
+       GEN2_CORE_CLK_FREQ,
+       GEN3_CORE_CLK_FREQ,
+@@ -470,7 +471,11 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
+ 
+       speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
+               PCI_EXP_LNKSTA_CLS;
+-      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
++
++      if (speed >= ARRAY_SIZE(pcie_gen_freq))
++              speed = 0;
++
++      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
+ 
+       /* If EP doesn't advertise L1SS, just return */
+       val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
+@@ -973,7 +978,11 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
+ 
+       speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
+               PCI_EXP_LNKSTA_CLS;
+-      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
++
++      if (speed >= ARRAY_SIZE(pcie_gen_freq))
++              speed = 0;
++
++      clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
+ 
+       tegra_pcie_enable_interrupts(pp);
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch b/queue-5.10/pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch
new file mode 100644 (file)
index 0000000..4899f92
--- /dev/null
+++ b/queue-5.10/pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch
@@ -0,0 +1,66 @@
+From 5e9d177d9db6a1b388466c3b1adfb55f8566ffc2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 12 May 2023 20:45:29 +0200
+Subject: pcmcia: rsrc_nonstatic: Fix memory leak in
+ nonstatic_release_resource_db()
+
+From: Armin Wolf <W_Armin@gmx.de>
+
+[ Upstream commit c85fd9422fe0f5d667305efb27f56d09eab120b0 ]
+
+When nonstatic_release_resource_db() frees all resources associated
+with an PCMCIA socket, it forgets to free socket_data too, causing
+a memory leak observable with kmemleak:
+
+unreferenced object 0xc28d1000 (size 64):
+  comm "systemd-udevd", pid 297, jiffies 4294898478 (age 194.484s)
+  hex dump (first 32 bytes):
+    00 00 00 00 00 00 00 00 f0 85 0e c3 00 00 00 00  ................
+    00 00 00 00 0c 10 8d c2 00 00 00 00 00 00 00 00  ................
+  backtrace:
+    [<ffda4245>] __kmem_cache_alloc_node+0x2d7/0x4a0
+    [<7e51f0c8>] kmalloc_trace+0x31/0xa4
+    [<d52b4ca0>] nonstatic_init+0x24/0x1a4 [pcmcia_rsrc]
+    [<a2f13e08>] pcmcia_register_socket+0x200/0x35c [pcmcia_core]
+    [<a728be1b>] yenta_probe+0x4d8/0xa70 [yenta_socket]
+    [<c48fac39>] pci_device_probe+0x99/0x194
+    [<84b7c690>] really_probe+0x181/0x45c
+    [<8060fe6e>] __driver_probe_device+0x75/0x1f4
+    [<b9b76f43>] driver_probe_device+0x28/0xac
+    [<648b766f>] __driver_attach+0xeb/0x1e4
+    [<6e9659eb>] bus_for_each_dev+0x61/0xb4
+    [<25a669f3>] driver_attach+0x1e/0x28
+    [<d8671d6b>] bus_add_driver+0x102/0x20c
+    [<df0d323c>] driver_register+0x5b/0x120
+    [<942cd8a4>] __pci_register_driver+0x44/0x4c
+    [<e536027e>] __UNIQUE_ID___addressable_cleanup_module188+0x1c/0xfffff000 [iTCO_vendor_support]
+
+Fix this by freeing socket_data too.
+
+Tested on a Acer Travelmate 4002WLMi by manually binding/unbinding
+the yenta_cardbus driver (yenta_socket).
+
+Signed-off-by: Armin Wolf <W_Armin@gmx.de>
+Message-ID: <20230512184529.5094-1-W_Armin@gmx.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pcmcia/rsrc_nonstatic.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pcmcia/rsrc_nonstatic.c b/drivers/pcmcia/rsrc_nonstatic.c
+index 69a6e9a5d6d26..6e90927e65769 100644
+--- a/drivers/pcmcia/rsrc_nonstatic.c
++++ b/drivers/pcmcia/rsrc_nonstatic.c
+@@ -1053,6 +1053,8 @@ static void nonstatic_release_resource_db(struct pcmcia_socket *s)
+               q = p->next;
+               kfree(p);
+       }
++
++      kfree(data);
+ }
+ 
+ 
+-- 
+2.40.1
+

diff --git a/queue-5.10/phy-qcom-qmp-combo-fix-init-count-imbalance.patch b/queue-5.10/phy-qcom-qmp-combo-fix-init-count-imbalance.patch
new file mode 100644 (file)
index 0000000..0f7999c
--- /dev/null
+++ b/queue-5.10/phy-qcom-qmp-combo-fix-init-count-imbalance.patch
@@ -0,0 +1,53 @@
+From 81508cec7c4cb98544ca3f869378558a50442ab8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 May 2023 12:38:09 +0200
+Subject: phy: qcom-qmp-combo: fix init-count imbalance
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit 9bf03a0cbd80a256bc1e1c4bcc80bc2b06b8b2b9 ]
+
+The init counter is not decremented on initialisation errors, which
+prevents retrying initialisation and can lead to the runtime suspend
+callback attempting to disable resources that have never been enabled.
+
+Add the missing decrement on initialisation errors so that the counter
+reflects the state of the device.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Cc: stable@vger.kernel.org     # 4.12
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20230502103810.12061-2-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+index c7309e981bfb5..96282a118e635 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+@@ -5085,7 +5085,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+       ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
+       if (ret) {
+               dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
+-              goto err_unlock;
++              goto err_decrement_count;
+       }
+ 
+       for (i = 0; i < cfg->num_resets; i++) {
+@@ -5155,7 +5155,8 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+               reset_control_assert(qmp->resets[i]);
+ err_disable_regulators:
+       regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
+-err_unlock:
++err_decrement_count:
++      qmp->init_count--;
+       mutex_unlock(&qmp->phy_mutex);
+ 
+       return ret;
+-- 
+2.40.1
+

diff --git a/queue-5.10/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch b/queue-5.10/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
new file mode 100644 (file)
index 0000000..e6a1344
--- /dev/null
+++ b/queue-5.10/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
@@ -0,0 +1,31819 @@
+From 032030652d1705550abb894daa91c064a003c88f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 00:35:32 +0300
+Subject: phy: qcom-qmp: create copies of QMP PHY driver
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 94a407cc17a445ddb3f7315cee0b0916d35d177c ]
+
+In order to split and cleanup the single monstrous QMP PHY driver,
+create blind copies of the current file. They will be used for:
+- PCIe (and a separate msm8996 PCIe PHY driver)
+- UFS
+- USB
+- Combo DP + USB
+
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20220607213203.2819885-2-dmitry.baryshkov@linaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Stable-dep-of: 9bf03a0cbd80 ("phy: qcom-qmp-combo: fix init-count imbalance")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c     | 6350 +++++++++++++++++
+ .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c  | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c       | 6350 +++++++++++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c       | 6350 +++++++++++++++++
+ 5 files changed, 31750 insertions(+)
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+new file mode 100644
+index 0000000000000..c7309e981bfb5
+--- /dev/null
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -0,0 +1,6350 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include <dt-bindings/phy/phy.h>
++
++#include "phy-qcom-qmp.h"
++
++/* QPHY_SW_RESET bit */
++#define SW_RESET                              BIT(0)
++/* QPHY_POWER_DOWN_CONTROL */
++#define SW_PWRDN                              BIT(0)
++#define REFCLK_DRV_DSBL                               BIT(1)
++/* QPHY_START_CONTROL bits */
++#define SERDES_START                          BIT(0)
++#define PCS_START                             BIT(1)
++#define PLL_READY_GATE_EN                     BIT(3)
++/* QPHY_PCS_STATUS bit */
++#define PHYSTATUS                             BIT(6)
++#define PHYSTATUS_4_20                                BIT(7)
++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
++#define PCS_READY                             BIT(0)
++
++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
++/* DP PHY soft reset */
++#define SW_DPPHY_RESET                                BIT(0)
++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
++#define SW_DPPHY_RESET_MUX                    BIT(1)
++/* USB3 PHY soft reset */
++#define SW_USB3PHY_RESET                      BIT(2)
++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
++#define SW_USB3PHY_RESET_MUX                  BIT(3)
++
++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
++#define USB3_MODE                             BIT(0) /* enables USB3 mode */
++#define DP_MODE                                       BIT(1) /* enables DP mode */
++
++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
++#define ARCVR_DTCT_EN                         BIT(0)
++#define ALFPS_DTCT_EN                         BIT(1)
++#define ARCVR_DTCT_EVENT_SEL                  BIT(4)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
++#define IRQ_CLEAR                             BIT(0)
++
++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
++#define RCVR_DETECT                           BIT(0)
++
++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
++#define CLAMP_EN                              BIT(0) /* enables i/o clamp_n */
++
++#define PHY_INIT_COMPLETE_TIMEOUT             10000
++#define POWER_DOWN_DELAY_US_MIN                       10
++#define POWER_DOWN_DELAY_US_MAX                       11
++
++#define MAX_PROP_NAME                         32
++
++/* Define the assumed distance between lanes for underspecified device trees. */
++#define QMP_PHY_LEGACY_LANE_STRIDE            0x400
++
++struct qmp_phy_init_tbl {
++      unsigned int offset;
++      unsigned int val;
++      /*
++       * register part of layout ?
++       * if yes, then offset gives index in the reg-layout
++       */
++      bool in_layout;
++      /*
++       * mask of lanes for which this register is written
++       * for cases when second lane needs different values
++       */
++      u8 lane_mask;
++};
++
++#define QMP_PHY_INIT_CFG(o, v)                \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_L(o, v)      \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .in_layout = true,      \
++              .lane_mask = 0xff,      \
++      }
++
++#define QMP_PHY_INIT_CFG_LANE(o, v, l)        \
++      {                               \
++              .offset = o,            \
++              .val = v,               \
++              .lane_mask = l,         \
++      }
++
++/* set of registers with offsets different per-PHY */
++enum qphy_reg_layout {
++      /* Common block control registers */
++      QPHY_COM_SW_RESET,
++      QPHY_COM_POWER_DOWN_CONTROL,
++      QPHY_COM_START_CONTROL,
++      QPHY_COM_PCS_READY_STATUS,
++      /* PCS registers */
++      QPHY_PLL_LOCK_CHK_DLY_TIME,
++      QPHY_FLL_CNTRL1,
++      QPHY_FLL_CNTRL2,
++      QPHY_FLL_CNT_VAL_L,
++      QPHY_FLL_CNT_VAL_H_TOL,
++      QPHY_FLL_MAN_CODE,
++      QPHY_SW_RESET,
++      QPHY_START_CTRL,
++      QPHY_PCS_READY_STATUS,
++      QPHY_PCS_STATUS,
++      QPHY_PCS_AUTONOMOUS_MODE_CTRL,
++      QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
++      QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
++      QPHY_PCS_POWER_DOWN_CONTROL,
++      /* PCS_MISC registers */
++      QPHY_PCS_MISC_TYPEC_CTRL,
++      /* Keep last to ensure regs_layout arrays are properly initialized */
++      QPHY_LAYOUT_SIZE
++};
++
++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                         = 0x00,
++      [QPHY_START_CTRL]                       = 0x44,
++      [QPHY_PCS_STATUS]                       = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
++};
++
++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_COM_SW_RESET]             = 0x400,
++      [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
++      [QPHY_COM_START_CONTROL]        = 0x408,
++      [QPHY_COM_PCS_READY_STATUS]     = 0x448,
++      [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
++      [QPHY_FLL_CNTRL1]               = 0xc4,
++      [QPHY_FLL_CNTRL2]               = 0xc8,
++      [QPHY_FLL_CNT_VAL_L]            = 0xcc,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
++      [QPHY_FLL_MAN_CODE]             = 0xd4,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_FLL_CNTRL1]               = 0xc0,
++      [QPHY_FLL_CNTRL2]               = 0xc4,
++      [QPHY_FLL_CNT_VAL_L]            = 0xc8,
++      [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
++      [QPHY_FLL_MAN_CODE]             = 0xd0,
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x17c,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
++};
++
++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
++};
++
++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x174,
++};
++
++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_STATUS]               = 0x2ac,
++};
++
++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
++};
++
++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
++};
++
++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
++};
++
++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
++      [QPHY_START_CTRL]               = 0x08,
++      [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
++      [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
++      [QPHY_PCS_STATUS]               = 0x174,
++      [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
++};
++
++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x160,
++};
++
++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = 0x00,
++      [QPHY_PCS_READY_STATUS]         = 0x168,
++};
++
++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_SW_RESET]                 = 0x00,
++      [QPHY_START_CTRL]               = 0x44,
++      [QPHY_PCS_STATUS]               = 0x14,
++      [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
++};
++
++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
++      [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
++      [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
++      [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
++};
++
++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
++
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
++      /* PLL and Loop filter settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      /* SSC settings */
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++};
++
++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
++      QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
++};
++
++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
++      QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++      QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
++      QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
++};
++
++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
++      QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
++      QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
++      QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
++      QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
++      QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
++};
++
++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
++      QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++};
++
++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
++      /* FLL settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
++      QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
++      QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
++};
++
++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
++      QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
++};
++
++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
++      QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
++};
++
++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
++
++};
++
++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
++      /* Lock Det settings */
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
++};
++
++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
++};
++
++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
++};
++
++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
++};
++
++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
++
++      /* Rate B */
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
++      QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
++};
++
++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
++      QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
++};
++
++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
++      QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
++      QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
++
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
++      QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
++};
++
++/* Register names should be validated, they might be different for this PHY */
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
++      QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
++};
++
++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
++      QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
++};
++
++struct qmp_phy;
++
++/* struct qmp_phy_cfg - per-PHY initialization config */
++struct qmp_phy_cfg {
++      /* phy-type - PCIE/UFS/USB */
++      unsigned int type;
++      /* number of lanes provided by phy */
++      int nlanes;
++
++      /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
++      const struct qmp_phy_init_tbl *serdes_tbl;
++      int serdes_tbl_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_sec;
++      int serdes_tbl_num_sec;
++      const struct qmp_phy_init_tbl *tx_tbl;
++      int tx_tbl_num;
++      const struct qmp_phy_init_tbl *tx_tbl_sec;
++      int tx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *rx_tbl;
++      int rx_tbl_num;
++      const struct qmp_phy_init_tbl *rx_tbl_sec;
++      int rx_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_tbl;
++      int pcs_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_tbl_sec;
++      int pcs_tbl_num_sec;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl;
++      int pcs_misc_tbl_num;
++      const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
++      int pcs_misc_tbl_num_sec;
++
++      /* Init sequence for DP PHY block link rates */
++      const struct qmp_phy_init_tbl *serdes_tbl_rbr;
++      int serdes_tbl_rbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr;
++      int serdes_tbl_hbr_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
++      int serdes_tbl_hbr2_num;
++      const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
++      int serdes_tbl_hbr3_num;
++
++      /* DP PHY callbacks */
++      int (*configure_dp_phy)(struct qmp_phy *qphy);
++      void (*configure_dp_tx)(struct qmp_phy *qphy);
++      int (*calibrate_dp_phy)(struct qmp_phy *qphy);
++      void (*dp_aux_init)(struct qmp_phy *qphy);
++
++      /* clock ids to be requested */
++      const char * const *clk_list;
++      int num_clks;
++      /* resets to be requested */
++      const char * const *reset_list;
++      int num_resets;
++      /* regulators to be requested */
++      const char * const *vreg_list;
++      int num_vregs;
++
++      /* array of registers with different offsets */
++      const unsigned int *regs;
++
++      unsigned int start_ctrl;
++      unsigned int pwrdn_ctrl;
++      unsigned int mask_com_pcs_ready;
++      /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
++      unsigned int phy_status;
++
++      /* true, if PHY has a separate PHY_COM control block */
++      bool has_phy_com_ctrl;
++      /* true, if PHY has a reset for individual lanes */
++      bool has_lane_rst;
++      /* true, if PHY needs delay after POWER_DOWN */
++      bool has_pwrdn_delay;
++      /* power_down delay in usec */
++      int pwrdn_delay_min;
++      int pwrdn_delay_max;
++
++      /* true, if PHY has a separate DP_COM control block */
++      bool has_phy_dp_com_ctrl;
++      /* true, if PHY has secondary tx/rx lanes to be configured */
++      bool is_dual_lane_phy;
++
++      /* true, if PCS block has no separate SW_RESET register */
++      bool no_pcs_sw_reset;
++};
++
++struct qmp_phy_combo_cfg {
++      const struct qmp_phy_cfg *usb_cfg;
++      const struct qmp_phy_cfg *dp_cfg;
++};
++
++/**
++ * struct qmp_phy - per-lane phy descriptor
++ *
++ * @phy: generic phy
++ * @cfg: phy specific configuration
++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
++ * @tx: iomapped memory space for lane's tx
++ * @rx: iomapped memory space for lane's rx
++ * @pcs: iomapped memory space for lane's pcs
++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
++ * @pcs_misc: iomapped memory space for lane's pcs_misc
++ * @pipe_clk: pipe clock
++ * @index: lane index
++ * @qmp: QMP phy to which this lane belongs
++ * @lane_rst: lane's reset controller
++ * @mode: current PHY mode
++ * @dp_aux_cfg: Display port aux config
++ * @dp_opts: Display port optional config
++ * @dp_clks: Display port clocks
++ */
++struct qmp_phy {
++      struct phy *phy;
++      const struct qmp_phy_cfg *cfg;
++      void __iomem *serdes;
++      void __iomem *tx;
++      void __iomem *rx;
++      void __iomem *pcs;
++      void __iomem *tx2;
++      void __iomem *rx2;
++      void __iomem *pcs_misc;
++      struct clk *pipe_clk;
++      unsigned int index;
++      struct qcom_qmp *qmp;
++      struct reset_control *lane_rst;
++      enum phy_mode mode;
++      unsigned int dp_aux_cfg;
++      struct phy_configure_opts_dp dp_opts;
++      struct qmp_phy_dp_clks *dp_clks;
++};
++
++struct qmp_phy_dp_clks {
++      struct qmp_phy *qphy;
++      struct clk_hw dp_link_hw;
++      struct clk_hw dp_pixel_hw;
++};
++
++/**
++ * struct qcom_qmp - structure holding QMP phy block attributes
++ *
++ * @dev: device
++ * @dp_com: iomapped memory space for phy's dp_com control block
++ *
++ * @clks: array of clocks required by phy
++ * @resets: array of resets required by phy
++ * @vregs: regulator supplies bulk data
++ *
++ * @phys: array of per-lane phy descriptors
++ * @phy_mutex: mutex lock for PHY common block initialization
++ * @init_count: phy common block initialization count
++ * @ufs_reset: optional UFS PHY reset handle
++ */
++struct qcom_qmp {
++      struct device *dev;
++      void __iomem *dp_com;
++
++      struct clk_bulk_data *clks;
++      struct reset_control **resets;
++      struct regulator_bulk_data *vregs;
++
++      struct qmp_phy **phys;
++
++      struct mutex phy_mutex;
++      int init_count;
++
++      struct reset_control *ufs_reset;
++};
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
++
++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg |= val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
++{
++      u32 reg;
++
++      reg = readl(base + offset);
++      reg &= ~val;
++      writel(reg, base + offset);
++
++      /* ensure that above write is through */
++      readl(base + offset);
++}
++
++/* list of clocks required by phy */
++static const char * const msm8996_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref",
++};
++
++static const char * const msm8996_ufs_phy_clk_l[] = {
++      "ref",
++};
++
++static const char * const qmp_v3_phy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "com_aux",
++};
++
++static const char * const sdm845_pciephy_clk_l[] = {
++      "aux", "cfg_ahb", "ref", "refgen",
++};
++
++static const char * const qmp_v4_phy_clk_l[] = {
++      "aux", "ref_clk_src", "ref", "com_aux",
++};
++
++/* the primary usb3 phy on sm8250 doesn't have a ref clock */
++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
++      "aux", "ref_clk_src", "com_aux"
++};
++
++static const char * const sm8450_ufs_phy_clk_l[] = {
++      "qref", "ref", "ref_aux",
++};
++
++static const char * const sdm845_ufs_phy_clk_l[] = {
++      "ref", "ref_aux",
++};
++
++/* usb3 phy on sdx55 doesn't have com_aux clock */
++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
++      "aux", "cfg_ahb", "ref"
++};
++
++static const char * const qcm2290_usb3phy_clk_l[] = {
++      "cfg_ahb", "ref", "com_aux",
++};
++
++/* list of resets */
++static const char * const msm8996_pciephy_reset_l[] = {
++      "phy", "common", "cfg",
++};
++
++static const char * const msm8996_usb3phy_reset_l[] = {
++      "phy", "common",
++};
++
++static const char * const sc7180_usb3phy_reset_l[] = {
++      "phy",
++};
++
++static const char * const qcm2290_usb3phy_reset_l[] = {
++      "phy_phy", "phy",
++};
++
++static const char * const sdm845_pciephy_reset_l[] = {
++      "phy",
++};
++
++/* list of regulators */
++static const char * const qmp_phy_vreg_l[] = {
++      "vdda-phy", "vdda-pll",
++};
++
++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = ipq8074_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++      .pcs_tbl                = ipq8074_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 3,
++
++      .serdes_tbl             = msm8996_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
++      .tx_tbl                 = msm8996_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
++      .rx_tbl                 = msm8996_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
++      .pcs_tbl                = msm8996_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .mask_com_pcs_ready     = PCS_READY,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = true,
++      .has_lane_rst           = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg msm8996_ufs_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_ufs_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
++      .tx_tbl                 = msm8996_ufs_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
++      .rx_tbl                 = msm8996_ufs_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
++
++      .clk_list               = msm8996_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
++
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++
++      .regs                   = msm8996_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8996_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
++      .tx_tbl                 = msm8996_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++      .rx_tbl                 = msm8996_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
++      .pcs_tbl                = msm8996_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++};
++
++static const char * const ipq8074_pciephy_clk_l[] = {
++      "aux", "cfg_ahb",
++};
++/* list of resets */
++static const char * const ipq8074_pciephy_reset_l[] = {
++      "phy", "common",
++};
++
++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq8074_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
++      .tx_tbl                 = ipq8074_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
++      .rx_tbl                 = ipq8074_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
++      .pcs_tbl                = ipq8074_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = ipq6018_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
++      .tx_tbl                 = ipq6018_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
++      .rx_tbl                 = ipq6018_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
++      .pcs_tbl                = ipq6018_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
++      .clk_list               = ipq8074_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = NULL,
++      .num_vregs              = 0,
++      .regs                   = ipq_pciephy_gen3_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_phy_com_ctrl       = false,
++      .has_lane_rst           = false,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qmp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
++      .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
++      .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
++      .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_qhp_pciephy_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
++      .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
++      .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
++      .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
++      .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
++      .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
++      .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
++      .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v3_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
++      .usb_cfg                = &sc7180_usb3phy_cfg,
++      .dp_cfg                 = &sc7180_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
++      .tx_tbl                 = sdm845_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
++      .rx_tbl                 = sdm845_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
++      .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sdm845_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm6115_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
++      .rx_tbl                 = sm6115_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
++      .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm6115_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++
++      .is_dual_lane_phy       = false,
++      .no_pcs_sw_reset        = true,
++};
++
++static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
++      .type                   = PHY_TYPE_PCIE,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
++      .tx_tbl                 = msm8998_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
++      .rx_tbl                 = msm8998_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
++      .pcs_tbl                = msm8998_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = ipq8074_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = pciephy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++};
++
++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = msm8998_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
++      .tx_tbl                 = msm8998_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
++      .rx_tbl                 = msm8998_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
++      .pcs_tbl                = msm8998_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
++      .clk_list               = msm8996_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8150_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8150_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v3_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
++      .reset_list             = sc7180_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v3_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8150_usb3phy_cfg,
++      .dp_cfg                 = &sc8180x_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
++      .type                   = PHY_TYPE_DP,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qmp_v4_dp_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
++      .tx_tbl                 = qmp_v4_dp_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
++
++      .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
++      .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
++      .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
++      .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
++      .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
++      .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
++      .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
++      .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
++
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++
++      .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
++      .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
++      .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
++      .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
++};
++
++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
++      .usb_cfg                = &sm8250_usb3phy_cfg,
++      .dp_cfg                 = &sm8250_dpphy_cfg,
++};
++
++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
++      .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
++      .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
++      .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = PCS_START | SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sdm845_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
++      .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qmp_v4_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++
++      .has_phy_dp_com_ctrl    = true,
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
++      .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
++      .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
++      .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
++      .clk_list               = qmp_v4_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
++      .reset_list             = msm8996_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8350_usb3_uniphy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
++      .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
++};
++
++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
++      .type                   = PHY_TYPE_UFS,
++      .nlanes                 = 2,
++
++      .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
++      .tx_tbl                 = sm8350_ufsphy_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
++      .rx_tbl                 = sm8350_ufsphy_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
++      .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
++      .clk_list               = sm8450_ufs_phy_clk_l,
++      .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8150_ufsphy_regs_layout,
++
++      .start_ctrl             = SERDES_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 1,
++
++      .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS,
++
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
++      .type = PHY_TYPE_PCIE,
++      .nlanes = 2,
++
++      .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
++      .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
++      .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
++      .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
++      .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
++      .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
++      .clk_list               = sdm845_pciephy_clk_l,
++      .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
++      .reset_list             = sdm845_pciephy_reset_l,
++      .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = sm8250_pcie_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
++      .phy_status             = PHYSTATUS_4_20,
++
++      .is_dual_lane_phy       = true,
++      .has_pwrdn_delay        = true,
++      .pwrdn_delay_min        = 995,          /* us */
++      .pwrdn_delay_max        = 1005,         /* us */
++};
++
++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
++      .type                   = PHY_TYPE_USB3,
++      .nlanes                 = 1,
++
++      .serdes_tbl             = qcm2290_usb3_serdes_tbl,
++      .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
++      .tx_tbl                 = qcm2290_usb3_tx_tbl,
++      .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
++      .rx_tbl                 = qcm2290_usb3_rx_tbl,
++      .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
++      .pcs_tbl                = qcm2290_usb3_pcs_tbl,
++      .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
++      .clk_list               = qcm2290_usb3phy_clk_l,
++      .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
++      .reset_list             = qcm2290_usb3phy_reset_l,
++      .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
++      .vreg_list              = qmp_phy_vreg_l,
++      .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
++      .regs                   = qcm2290_usb3phy_regs_layout,
++
++      .start_ctrl             = SERDES_START | PCS_START,
++      .pwrdn_ctrl             = SW_PWRDN,
++      .phy_status             = PHYSTATUS,
++
++      .is_dual_lane_phy       = true,
++};
++
++static void qcom_qmp_phy_configure_lane(void __iomem *base,
++                                      const unsigned int *regs,
++                                      const struct qmp_phy_init_tbl tbl[],
++                                      int num,
++                                      u8 lane_mask)
++{
++      int i;
++      const struct qmp_phy_init_tbl *t = tbl;
++
++      if (!t)
++              return;
++
++      for (i = 0; i < num; i++, t++) {
++              if (!(t->lane_mask & lane_mask))
++                      continue;
++
++              if (t->in_layout)
++                      writel(t->val, base + regs[t->offset]);
++              else
++                      writel(t->val, base + t->offset);
++      }
++}
++
++static void qcom_qmp_phy_configure(void __iomem *base,
++                                 const unsigned int *regs,
++                                 const struct qmp_phy_init_tbl tbl[],
++                                 int num)
++{
++      qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
++}
++
++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
++      int serdes_tbl_num = cfg->serdes_tbl_num;
++      int ret;
++
++      qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
++      if (cfg->serdes_tbl_sec)
++              qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
++                                     cfg->serdes_tbl_num_sec);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              switch (dp_opts->link_rate) {
++              case 1620:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_rbr,
++                                             cfg->serdes_tbl_rbr_num);
++                      break;
++              case 2700:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr,
++                                             cfg->serdes_tbl_hbr_num);
++                      break;
++              case 5400:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr2,
++                                             cfg->serdes_tbl_hbr2_num);
++                      break;
++              case 8100:
++                      qcom_qmp_phy_configure(serdes, cfg->regs,
++                                             cfg->serdes_tbl_hbr3,
++                                             cfg->serdes_tbl_hbr3_num);
++                      break;
++              default:
++                      /* Other link rates aren't supported */
++                      return -EINVAL;
++              }
++      }
++
++
++      if (cfg->has_phy_com_ctrl) {
++              void __iomem *status;
++              unsigned int mask, val;
++
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++
++              status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
++              mask = cfg->mask_com_pcs_ready;
++
++              ret = readl_poll_timeout(status, val, (val & mask), 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev,
++                              "phy common block init timed-out\n");
++                      return ret;
++              }
++      }
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_LANE_0_1_PWRDN |
++             DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
++             DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(QSERDES_V3_COM_BIAS_EN |
++             QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
++             QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
++             QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
++             qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
++      { 0x00, 0x0c, 0x15, 0x1a },
++      { 0x02, 0x0e, 0x16, 0xff },
++      { 0x02, 0x11, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
++      { 0x02, 0x12, 0x16, 0x1a },
++      { 0x09, 0x19, 0x1f, 0xff },
++      { 0x10, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
++      { 0x00, 0x0c, 0x14, 0x19 },
++      { 0x00, 0x0b, 0x12, 0xff },
++      { 0x00, 0x0b, 0xff, 0xff },
++      { 0x04, 0xff, 0xff, 0xff }
++};
++
++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
++      { 0x08, 0x0f, 0x16, 0x1f },
++      { 0x11, 0x1e, 0x1f, 0xff },
++      { 0x19, 0x1f, 0xff, 0xff },
++      { 0x1f, 0xff, 0xff, 0xff }
++};
++
++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
++              unsigned int drv_lvl_reg, unsigned int emp_post_reg)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      unsigned int v_level = 0, p_level = 0;
++      u8 voltage_swing_cfg, pre_emphasis_cfg;
++      int i;
++
++      for (i = 0; i < dp_opts->lanes; i++) {
++              v_level = max(v_level, dp_opts->voltage[i]);
++              p_level = max(p_level, dp_opts->pre[i]);
++      }
++
++      if (dp_opts->link_rate <= 2700) {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
++      } else {
++              voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
++              pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
++      }
++
++      /* TODO: Move check to config check */
++      if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
++              return -EINVAL;
++
++      /* Enable MUX to use Cursor values from these registers */
++      voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
++      pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
++
++      writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
++      writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
++      writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
++
++      return 0;
++}
++
++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 bias_en, drvr_en;
++
++      if (qcom_qmp_phy_configure_dp_swing(qphy,
++                              QSERDES_V3_TX_TX_DRV_LVL,
++                              QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
++              return;
++
++      if (dp_opts->lanes == 1) {
++              bias_en = 0x3e;
++              drvr_en = 0x13;
++      } else {
++              bias_en = 0x3f;
++              drvr_en = 0x10;
++      }
++
++      writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
++      writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
++}
++
++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
++{
++      u32 val;
++      bool reverse = false;
++
++      val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++            DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
++
++      /*
++       * TODO: Assume orientation is CC1 for now and two lanes, need to
++       * use type-c connector to understand orientation and lanes.
++       *
++       * Otherwise val changes to be like below if this code understood
++       * the orientation of the type-c cable.
++       *
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
++       *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
++       * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
++       *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++       * if (orientation == ORIENTATION_CC2)
++       *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
++       */
++      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
++      writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
++
++      return reverse;
++}
++
++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++
++      qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000);
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
++{
++      writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
++             DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
++             qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++
++      /* Turn on BIAS current for PHY/PLL */
++      writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
++
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++      writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
++      writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
++      writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
++      writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
++      writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
++      qphy->dp_aux_cfg = 0;
++
++      writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
++             PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
++             PHY_AUX_REQ_ERR_MASK,
++             qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
++}
++
++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
++{
++      /* Program default values before writing proper values */
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      qcom_qmp_phy_configure_dp_swing(qphy,
++                      QSERDES_V4_TX_TX_DRV_LVL,
++                      QSERDES_V4_TX_TX_EMP_POST1_LVL);
++}
++
++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
++      const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
++      u32 phy_vco_div, status;
++      unsigned long pixel_freq;
++      u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
++      bool reverse;
++
++      writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
++
++      reverse = qcom_qmp_phy_configure_dp_mode(qphy);
++
++      writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++      writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
++
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
++      writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              phy_vco_div = 0x1;
++              pixel_freq = 1620000000UL / 2;
++              break;
++      case 2700:
++              phy_vco_div = 0x1;
++              pixel_freq = 2700000000UL / 2;
++              break;
++      case 5400:
++              phy_vco_div = 0x2;
++              pixel_freq = 5400000000UL / 4;
++              break;
++      case 8100:
++              phy_vco_div = 0x0;
++              pixel_freq = 8100000000UL / 6;
++              break;
++      default:
++              /* Other link rates aren't supported */
++              return -EINVAL;
++      }
++      writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
++
++      clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
++      clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
++
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
++      writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(0)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      /*
++       * At least for 7nm DP PHY this has to be done after enabling link
++       * clock.
++       */
++
++      if (dp_opts->lanes == 1) {
++              bias0_en = reverse ? 0x3e : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3e;
++              drvr0_en = reverse ? 0x13 : 0x10;
++              drvr1_en = reverse ? 0x10 : 0x13;
++      } else if (dp_opts->lanes == 2) {
++              bias0_en = reverse ? 0x3f : 0x15;
++              bias1_en = reverse ? 0x15 : 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      } else {
++              bias0_en = 0x3f;
++              bias1_en = 0x3f;
++              drvr0_en = 0x10;
++              drvr1_en = 0x10;
++      }
++
++      writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++      writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
++      writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
++
++      writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
++      udelay(2000);
++      writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
++
++      if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
++                      status,
++                      ((status & BIT(1)) > 0),
++                      500,
++                      10000))
++              return -ETIMEDOUT;
++
++      writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
++      writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
++
++      writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
++      writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
++
++      writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++      writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
++
++      return 0;
++}
++
++/*
++ * We need to calibrate the aux setting here as many times
++ * as the caller tries
++ */
++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
++{
++      static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
++      u8 val;
++
++      qphy->dp_aux_cfg++;
++      qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
++      val = cfg1_settings[qphy->dp_aux_cfg];
++
++      writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
++{
++      const struct phy_configure_opts_dp *dp_opts = &opts->dp;
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
++      if (qphy->dp_opts.set_voltages) {
++              cfg->configure_dp_tx(qphy);
++              qphy->dp_opts.set_voltages = 0;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->calibrate_dp_phy)
++              return cfg->calibrate_dp_phy(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *dp_com = qmp->dp_com;
++      int ret, i;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (qmp->init_count++) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      /* turn on regulator supplies */
++      ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
++      if (ret) {
++              dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
++              goto err_unlock;
++      }
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              ret = reset_control_assert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset assert failed\n",
++                              cfg->reset_list[i]);
++                      goto err_disable_regulators;
++              }
++      }
++
++      for (i = cfg->num_resets - 1; i >= 0; i--) {
++              ret = reset_control_deassert(qmp->resets[i]);
++              if (ret) {
++                      dev_err(qmp->dev, "%s reset deassert failed\n",
++                              qphy->cfg->reset_list[i]);
++                      goto err_assert_reset;
++              }
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              goto err_assert_reset;
++
++      if (cfg->has_phy_dp_com_ctrl) {
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
++                           SW_PWRDN);
++              /* override hardware control for reset of qmp phy */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              /* Default type-c orientation, i.e CC1 */
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
++
++              qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
++                           USB3_MODE | DP_MODE);
++
++              /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
++                           SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
++                           SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
++
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
++              qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
++      }
++
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      } else {
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
++                      qphy_setbits(pcs,
++                                      cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                      cfg->pwrdn_ctrl);
++              else
++                      qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++      }
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++
++err_assert_reset:
++      while (++i < cfg->num_resets)
++              reset_control_assert(qmp->resets[i]);
++err_disable_regulators:
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++err_unlock:
++      mutex_unlock(&qmp->phy_mutex);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
++{
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *serdes = qphy->serdes;
++      int i = cfg->num_resets;
++
++      mutex_lock(&qmp->phy_mutex);
++      if (--qmp->init_count) {
++              mutex_unlock(&qmp->phy_mutex);
++              return 0;
++      }
++
++      reset_control_assert(qmp->ufs_reset);
++      if (cfg->has_phy_com_ctrl) {
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
++                           SERDES_START | PCS_START);
++              qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
++                           SW_RESET);
++              qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
++                           SW_PWRDN);
++      }
++
++      while (--i >= 0)
++              reset_control_assert(qmp->resets[i]);
++
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
++
++      mutex_unlock(&qmp->phy_mutex);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_init(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret;
++      dev_vdbg(qmp->dev, "Initializing QMP phy\n");
++
++      if (cfg->no_pcs_sw_reset) {
++              /*
++               * Get UFS reset, which is delayed until now to avoid a
++               * circular dependency where UFS needs its PHY, but the PHY
++               * needs this UFS reset.
++               */
++              if (!qmp->ufs_reset) {
++                      qmp->ufs_reset =
++                              devm_reset_control_get_exclusive(qmp->dev,
++                                                               "ufsphy");
++
++                      if (IS_ERR(qmp->ufs_reset)) {
++                              ret = PTR_ERR(qmp->ufs_reset);
++                              dev_err(qmp->dev,
++                                      "failed to get UFS reset: %d\n",
++                                      ret);
++
++                              qmp->ufs_reset = NULL;
++                              return ret;
++                      }
++              }
++
++              ret = reset_control_assert(qmp->ufs_reset);
++              if (ret)
++                      return ret;
++      }
++
++      ret = qcom_qmp_phy_com_init(qphy);
++      if (ret)
++              return ret;
++
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->dp_aux_init(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_power_on(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      struct qcom_qmp *qmp = qphy->qmp;
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *tx = qphy->tx;
++      void __iomem *rx = qphy->rx;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      void __iomem *status;
++      unsigned int mask, val, ready;
++      int ret;
++
++      qcom_qmp_phy_serdes_init(qphy);
++
++      if (cfg->has_lane_rst) {
++              ret = reset_control_deassert(qphy->lane_rst);
++              if (ret) {
++                      dev_err(qmp->dev, "lane%d reset deassert failed\n",
++                              qphy->index);
++                      return ret;
++              }
++      }
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
++              goto err_reset_lane;
++      }
++
++      /* Tx, Rx, and PCS configurations */
++      qcom_qmp_phy_configure_lane(tx, cfg->regs,
++                                  cfg->tx_tbl, cfg->tx_tbl_num, 1);
++      if (cfg->tx_tbl_sec)
++              qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
++                                          cfg->tx_tbl_num_sec, 1);
++
++      /* Configuration for other LANE for USB-DP combo PHY */
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                          cfg->tx_tbl, cfg->tx_tbl_num, 2);
++              if (cfg->tx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
++                                                  cfg->tx_tbl_sec,
++                                                  cfg->tx_tbl_num_sec, 2);
++      }
++
++      /* Configure special DP tx tunings */
++      if (cfg->type == PHY_TYPE_DP)
++              cfg->configure_dp_tx(qphy);
++
++      qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                  cfg->rx_tbl, cfg->rx_tbl_num, 1);
++      if (cfg->rx_tbl_sec)
++              qcom_qmp_phy_configure_lane(rx, cfg->regs,
++                                          cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
++
++      if (cfg->is_dual_lane_phy) {
++              qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                          cfg->rx_tbl, cfg->rx_tbl_num, 2);
++              if (cfg->rx_tbl_sec)
++                      qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
++                                                  cfg->rx_tbl_sec,
++                                                  cfg->rx_tbl_num_sec, 2);
++      }
++
++      /* Configure link rate, swing, etc. */
++      if (cfg->type == PHY_TYPE_DP) {
++              cfg->configure_dp_phy(qphy);
++      } else {
++              qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
++              if (cfg->pcs_tbl_sec)
++                      qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
++                                             cfg->pcs_tbl_num_sec);
++      }
++
++      ret = reset_control_deassert(qmp->ufs_reset);
++      if (ret)
++              goto err_disable_pipe_clk;
++
++      qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
++                             cfg->pcs_misc_tbl_num);
++      if (cfg->pcs_misc_tbl_sec)
++              qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
++                                     cfg->pcs_misc_tbl_num_sec);
++
++      /*
++       * Pull out PHY from POWER DOWN state.
++       * This is active low enable signal to power-down PHY.
++       */
++      if(cfg->type == PHY_TYPE_PCIE)
++              qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
++
++      if (cfg->has_pwrdn_delay)
++              usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
++
++      if (cfg->type != PHY_TYPE_DP) {
++              /* Pull PHY out of reset state */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++              /* start SerDes and Phy-Coding-Sublayer */
++              qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              if (cfg->type == PHY_TYPE_UFS) {
++                      status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
++                      mask = PCS_READY;
++                      ready = PCS_READY;
++              } else {
++                      status = pcs + cfg->regs[QPHY_PCS_STATUS];
++                      mask = cfg->phy_status;
++                      ready = 0;
++              }
++
++              ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
++                                       PHY_INIT_COMPLETE_TIMEOUT);
++              if (ret) {
++                      dev_err(qmp->dev, "phy initialization timed-out\n");
++                      goto err_disable_pipe_clk;
++              }
++      }
++      return 0;
++
++err_disable_pipe_clk:
++      clk_disable_unprepare(qphy->pipe_clk);
++err_reset_lane:
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_power_off(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      clk_disable_unprepare(qphy->pipe_clk);
++
++      if (cfg->type == PHY_TYPE_DP) {
++              /* Assert DP PHY power down */
++              writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
++      } else {
++              /* PHY reset */
++              if (!cfg->no_pcs_sw_reset)
++                      qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
++
++              /* stop SerDes and Phy-Coding-Sublayer */
++              qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
++
++              /* Put PHY into POWER DOWN state: active low */
++              if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
++                      qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
++                                   cfg->pwrdn_ctrl);
++              } else {
++                      qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
++                                      cfg->pwrdn_ctrl);
++              }
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_exit(struct phy *phy)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      if (cfg->has_lane_rst)
++              reset_control_assert(qphy->lane_rst);
++
++      qcom_qmp_phy_com_exit(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_enable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_init(phy);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_power_on(phy);
++      if (ret)
++              qcom_qmp_phy_exit(phy);
++
++      return ret;
++}
++
++static int qcom_qmp_phy_disable(struct phy *phy)
++{
++      int ret;
++
++      ret = qcom_qmp_phy_power_off(phy);
++      if (ret)
++              return ret;
++      return qcom_qmp_phy_exit(phy);
++}
++
++static int qcom_qmp_phy_set_mode(struct phy *phy,
++                               enum phy_mode mode, int submode)
++{
++      struct qmp_phy *qphy = phy_get_drvdata(phy);
++
++      qphy->mode = mode;
++
++      return 0;
++}
++
++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++      u32 intr_mask;
++
++      if (qphy->mode == PHY_MODE_USB_HOST_SS ||
++          qphy->mode == PHY_MODE_USB_DEVICE_SS)
++              intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
++      else
++              intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
++
++      /* Clear any pending interrupts status */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
++
++      /* Enable required PHY autonomous mode interrupts */
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
++
++      /* Enable i/o clamp_n for autonomous mode */
++      if (pcs_misc)
++              qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++}
++
++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
++{
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      void __iomem *pcs = qphy->pcs;
++      void __iomem *pcs_misc = qphy->pcs_misc;
++
++      /* Disable i/o clamp_n on resume for normal mode */
++      if (pcs_misc)
++              qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
++
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
++                   ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
++
++      qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++      /* Writing 1 followed by 0 clears the interrupt */
++      qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++
++      dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      qcom_qmp_phy_enable_autonomous_mode(qphy);
++
++      clk_disable_unprepare(qphy->pipe_clk);
++      clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++
++      return 0;
++}
++
++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct qmp_phy *qphy = qmp->phys[0];
++      const struct qmp_phy_cfg *cfg = qphy->cfg;
++      int ret = 0;
++
++      dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
++
++      /* Supported only for USB3 PHY and luckily USB3 is the first phy */
++      if (cfg->type != PHY_TYPE_USB3)
++              return 0;
++
++      if (!qmp->init_count) {
++              dev_vdbg(dev, "PHY not initialized, bailing out\n");
++              return 0;
++      }
++
++      ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
++      if (ret)
++              return ret;
++
++      ret = clk_prepare_enable(qphy->pipe_clk);
++      if (ret) {
++              dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
++              clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
++              return ret;
++      }
++
++      qcom_qmp_phy_disable_autonomous_mode(qphy);
++
++      return 0;
++}
++
++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_vregs;
++      int i;
++
++      qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
++      if (!qmp->vregs)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->vregs[i].supply = cfg->vreg_list[i];
++
++      return devm_regulator_bulk_get(dev, num, qmp->vregs);
++}
++
++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int i;
++
++      qmp->resets = devm_kcalloc(dev, cfg->num_resets,
++                                 sizeof(*qmp->resets), GFP_KERNEL);
++      if (!qmp->resets)
++              return -ENOMEM;
++
++      for (i = 0; i < cfg->num_resets; i++) {
++              struct reset_control *rst;
++              const char *name = cfg->reset_list[i];
++
++              rst = devm_reset_control_get_exclusive(dev, name);
++              if (IS_ERR(rst)) {
++                      dev_err(dev, "failed to get %s reset\n", name);
++                      return PTR_ERR(rst);
++              }
++              qmp->resets[i] = rst;
++      }
++
++      return 0;
++}
++
++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      int num = cfg->num_clks;
++      int i;
++
++      qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
++      if (!qmp->clks)
++              return -ENOMEM;
++
++      for (i = 0; i < num; i++)
++              qmp->clks[i].id = cfg->clk_list[i];
++
++      return devm_clk_bulk_get(dev, num, qmp->clks);
++}
++
++static void phy_clk_release_provider(void *res)
++{
++      of_clk_del_provider(res);
++}
++
++/*
++ * Register a fixed rate pipe clock.
++ *
++ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
++ * controls it. The <s>_pipe_clk coming out of the GCC is requested
++ * by the PHY driver for its operations.
++ * We register the <s>_pipe_clksrc here. The gcc driver takes care
++ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
++ * Below picture shows this relationship.
++ *
++ *         +---------------+
++ *         |   PHY block   |<<---------------------------------------+
++ *         |               |                                         |
++ *         |   +-------+   |                   +-----+               |
++ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
++ *    clk  |   +-------+   |                   +-----+
++ *         +---------------+
++ */
++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
++{
++      struct clk_fixed_rate *fixed;
++      struct clk_init_data init = { };
++      int ret;
++
++      ret = of_property_read_string(np, "clock-output-names", &init.name);
++      if (ret) {
++              dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
++              return ret;
++      }
++
++      fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
++      if (!fixed)
++              return -ENOMEM;
++
++      init.ops = &clk_fixed_rate_ops;
++
++      /* controllers using QMP phys use 125MHz pipe clock interface */
++      fixed->fixed_rate = 125000000;
++      fixed->hw.init = &init;
++
++      ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++/*
++ * Display Port PLL driver block diagram for branch clocks
++ *
++ *              +------------------------------+
++ *              |         DP_VCO_CLK           |
++ *              |                              |
++ *              |    +-------------------+     |
++ *              |    |   (DP PLL/VCO)    |     |
++ *              |    +---------+---------+     |
++ *              |              v               |
++ *              |   +----------+-----------+   |
++ *              |   | hsclk_divsel_clk_src |   |
++ *              |   +----------+-----------+   |
++ *              +------------------------------+
++ *                              |
++ *          +---------<---------v------------>----------+
++ *          |                                           |
++ * +--------v----------------+                          |
++ * |    dp_phy_pll_link_clk  |                          |
++ * |     link_clk            |                          |
++ * +--------+----------------+                          |
++ *          |                                           |
++ *          |                                           |
++ *          v                                           v
++ * Input to DISPCC block                                |
++ * for link clk, crypto clk                             |
++ * and interface clock                                  |
++ *                                                      |
++ *                                                      |
++ *      +--------<------------+-----------------+---<---+
++ *      |                     |                 |
++ * +----v---------+  +--------v-----+  +--------v------+
++ * | vco_divided  |  | vco_divided  |  | vco_divided   |
++ * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
++ * |              |  |              |  |               |
++ * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
++ * +-------+------+  +-----+--------+  +--------+------+
++ *         |                 |                  |
++ *         v---->----------v-------------<------v
++ *                         |
++ *              +----------+-----------------+
++ *              |   dp_phy_pll_vco_div_clk   |
++ *              +---------+------------------+
++ *                        |
++ *                        v
++ *              Input to DISPCC block
++ *              for DP pixel clock
++ *
++ */
++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
++                                              struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 1620000000UL / 2:
++      case 2700000000UL / 2:
++      /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++              return 1620000000UL / 2;
++      case 2700:
++              return 2700000000UL / 2;
++      case 5400:
++              return 5400000000UL / 4;
++      case 8100:
++              return 8100000000UL / 6;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
++      .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
++};
++
++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
++                                             struct clk_rate_request *req)
++{
++      switch (req->rate) {
++      case 162000000:
++      case 270000000:
++      case 540000000:
++      case 810000000:
++              return 0;
++      default:
++              return -EINVAL;
++      }
++}
++
++static unsigned long
++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++      const struct qmp_phy_dp_clks *dp_clks;
++      const struct qmp_phy *qphy;
++      const struct phy_configure_opts_dp *dp_opts;
++
++      dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
++      qphy = dp_clks->qphy;
++      dp_opts = &qphy->dp_opts;
++
++      switch (dp_opts->link_rate) {
++      case 1620:
++      case 2700:
++      case 5400:
++      case 8100:
++              return dp_opts->link_rate * 100000;
++      default:
++              return 0;
++      }
++}
++
++static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
++      .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
++      .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
++};
++
++static struct clk_hw *
++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct qmp_phy_dp_clks *dp_clks = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx >= 2) {
++              pr_err("%s: invalid index %u\n", __func__, idx);
++              return ERR_PTR(-EINVAL);
++      }
++
++      if (idx == 0)
++              return &dp_clks->dp_link_hw;
++
++      return &dp_clks->dp_pixel_hw;
++}
++
++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
++                              struct device_node *np)
++{
++      struct clk_init_data init = { };
++      struct qmp_phy_dp_clks *dp_clks;
++      char name[64];
++      int ret;
++
++      dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
++      if (!dp_clks)
++              return -ENOMEM;
++
++      dp_clks->qphy = qphy;
++      qphy->dp_clks = dp_clks;
++
++      snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_link_clk_ops;
++      init.name = name;
++      dp_clks->dp_link_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
++      if (ret)
++              return ret;
++
++      snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
++      init.ops = &qcom_qmp_dp_pixel_clk_ops;
++      init.name = name;
++      dp_clks->dp_pixel_hw.init = &init;
++      ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
++      if (ret)
++              return ret;
++
++      ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
++      if (ret)
++              return ret;
++
++      /*
++       * Roll a devm action because the clock provider is the child node, but
++       * the child node is not actually a device.
++       */
++      return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
++}
++
++static const struct phy_ops qcom_qmp_phy_gen_ops = {
++      .init           = qcom_qmp_phy_enable,
++      .exit           = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_phy_dp_ops = {
++      .init           = qcom_qmp_phy_init,
++      .configure      = qcom_qmp_dp_phy_configure,
++      .power_on       = qcom_qmp_phy_power_on,
++      .calibrate      = qcom_qmp_dp_phy_calibrate,
++      .power_off      = qcom_qmp_phy_power_off,
++      .exit           = qcom_qmp_phy_exit,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
++      .power_on       = qcom_qmp_phy_enable,
++      .power_off      = qcom_qmp_phy_disable,
++      .set_mode       = qcom_qmp_phy_set_mode,
++      .owner          = THIS_MODULE,
++};
++
++static void qcom_qmp_reset_control_put(void *data)
++{
++      reset_control_put(data);
++}
++
++static
++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
++                      void __iomem *serdes, const struct qmp_phy_cfg *cfg)
++{
++      struct qcom_qmp *qmp = dev_get_drvdata(dev);
++      struct phy *generic_phy;
++      struct qmp_phy *qphy;
++      const struct phy_ops *ops;
++      char prop_name[MAX_PROP_NAME];
++      int ret;
++
++      qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
++      if (!qphy)
++              return -ENOMEM;
++
++      qphy->cfg = cfg;
++      qphy->serdes = serdes;
++      /*
++       * Get memory resources for each phy lane:
++       * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
++       * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
++       * For single lane PHYs: pcs_misc (optional) -> 3.
++       */
++      qphy->tx = of_iomap(np, 0);
++      if (!qphy->tx)
++              return -ENOMEM;
++
++      qphy->rx = of_iomap(np, 1);
++      if (!qphy->rx)
++              return -ENOMEM;
++
++      qphy->pcs = of_iomap(np, 2);
++      if (!qphy->pcs)
++              return -ENOMEM;
++
++      /*
++       * If this is a dual-lane PHY, then there should be registers for the
++       * second lane. Some old device trees did not specify this, so fall
++       * back to old legacy behavior of assuming they can be reached at an
++       * offset from the first lane.
++       */
++      if (cfg->is_dual_lane_phy) {
++              qphy->tx2 = of_iomap(np, 3);
++              qphy->rx2 = of_iomap(np, 4);
++              if (!qphy->tx2 || !qphy->rx2) {
++                      dev_warn(dev,
++                               "Underspecified device tree, falling back to legacy register regions\n");
++
++                      /* In the old version, pcs_misc is at index 3. */
++                      qphy->pcs_misc = qphy->tx2;
++                      qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
++                      qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
++
++              } else {
++                      qphy->pcs_misc = of_iomap(np, 5);
++              }
++
++      } else {
++              qphy->pcs_misc = of_iomap(np, 3);
++      }
++
++      if (!qphy->pcs_misc)
++              dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
++
++      /*
++       * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
++       * based phys, so they essentially have pipe clock. So,
++       * we return error in case phy is USB3 or PIPE type.
++       * Otherwise, we initialize pipe clock to NULL for
++       * all phys that don't need this.
++       */
++      snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
++      qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
++      if (IS_ERR(qphy->pipe_clk)) {
++              if (cfg->type == PHY_TYPE_PCIE ||
++                  cfg->type == PHY_TYPE_USB3) {
++                      ret = PTR_ERR(qphy->pipe_clk);
++                      if (ret != -EPROBE_DEFER)
++                              dev_err(dev,
++                                      "failed to get lane%d pipe_clk, %d\n",
++                                      id, ret);
++                      return ret;
++              }
++              qphy->pipe_clk = NULL;
++      }
++
++      /* Get lane reset, if any */
++      if (cfg->has_lane_rst) {
++              snprintf(prop_name, sizeof(prop_name), "lane%d", id);
++              qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
++              if (IS_ERR(qphy->lane_rst)) {
++                      dev_err(dev, "failed to get lane%d reset\n", id);
++                      return PTR_ERR(qphy->lane_rst);
++              }
++              ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
++                                             qphy->lane_rst);
++              if (ret)
++                      return ret;
++      }
++
++      if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
++              ops = &qcom_qmp_pcie_ufs_ops;
++      else if (cfg->type == PHY_TYPE_DP)
++              ops = &qcom_qmp_phy_dp_ops;
++      else
++              ops = &qcom_qmp_phy_gen_ops;
++
++      generic_phy = devm_phy_create(dev, np, ops);
++      if (IS_ERR(generic_phy)) {
++              ret = PTR_ERR(generic_phy);
++              dev_err(dev, "failed to create qphy %d\n", ret);
++              return ret;
++      }
++
++      qphy->phy = generic_phy;
++      qphy->index = id;
++      qphy->qmp = qmp;
++      qmp->phys[id] = qphy;
++      phy_set_drvdata(generic_phy, qphy);
++
++      return 0;
++}
++
++static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,ipq8074-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-pcie-phy",
++              .data = &msm8996_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-ufs-phy",
++              .data = &msm8996_ufs_cfg,
++      }, {
++              .compatible = "qcom,msm8996-qmp-usb3-phy",
++              .data = &msm8996_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-pcie-phy",
++              .data = &msm8998_pciephy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,ipq8074-qmp-pcie-phy",
++              .data = &ipq8074_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-pcie-phy",
++              .data = &ipq6018_pciephy_cfg,
++      }, {
++              .compatible = "qcom,ipq6018-qmp-usb3-phy",
++              .data = &ipq8074_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-phy",
++              .data = &sc7180_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sc8180x-qmp-pcie-phy",
++              .data = &sc8180x_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8280xp-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sdm845-qhp-pcie-phy",
++              .data = &sdm845_qhp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-pcie-phy",
++              .data = &sdm845_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-phy",
++              .data = &qmp_v3_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
++              .data = &qmp_v3_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdm845-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,msm8998-qmp-usb3-phy",
++              .data = &msm8998_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm6115-qmp-ufs-phy",
++              .data = &sm6115_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm6350-qmp-ufs-phy",
++              .data = &sdm845_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-ufs-phy",
++              .data = &sm8150_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-phy",
++              .data = &sm8150_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
++              .data = &sm8150_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-phy",
++              .data = &sm8250_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              /* It's a combo phy */
++      }, {
++              .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
++              .data = &sm8250_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
++              .data = &sm8250_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-ufs-phy",
++              .data = &sm8350_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
++              .data = &sm8250_qmp_gen3x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-pcie-phy",
++              .data = &sdx55_qmp_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
++              .data = &sdx55_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
++              .data = &sdx65_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
++              .data = &sm8350_usb3_uniphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
++              .data = &sm8450_qmp_gen3x1_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
++              .data = &sm8450_qmp_gen4x2_pciephy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-ufs-phy",
++              .data = &sm8450_ufsphy_cfg,
++      }, {
++              .compatible = "qcom,sm8450-qmp-usb3-phy",
++              .data = &sm8350_usb3phy_cfg,
++      }, {
++              .compatible = "qcom,qcm2290-qmp-usb3-phy",
++              .data = &qcm2290_usb3phy_cfg,
++      },
++      { },
++};
++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
++
++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
++      {
++              .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
++              .data = &sc7180_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
++              .data = &sm8250_usb3dpphy_cfg,
++      },
++      {
++              .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
++              .data = &sc8180x_usb3dpphy_cfg,
++      },
++      { }
++};
++
++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
++      SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
++                         qcom_qmp_phy_runtime_resume, NULL)
++};
++
++static int qcom_qmp_phy_probe(struct platform_device *pdev)
++{
++      struct qcom_qmp *qmp;
++      struct device *dev = &pdev->dev;
++      struct device_node *child;
++      struct phy_provider *phy_provider;
++      void __iomem *serdes;
++      void __iomem *usb_serdes;
++      void __iomem *dp_serdes = NULL;
++      const struct qmp_phy_combo_cfg *combo_cfg = NULL;
++      const struct qmp_phy_cfg *cfg = NULL;
++      const struct qmp_phy_cfg *usb_cfg = NULL;
++      const struct qmp_phy_cfg *dp_cfg = NULL;
++      int num, id, expected_phys;
++      int ret;
++
++      qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
++      if (!qmp)
++              return -ENOMEM;
++
++      qmp->dev = dev;
++      dev_set_drvdata(dev, qmp);
++
++      /* Get the specific init parameters of QMP phy */
++      cfg = of_device_get_match_data(dev);
++      if (!cfg) {
++              const struct of_device_id *match;
++
++              match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
++              if (!match)
++                      return -EINVAL;
++
++              combo_cfg = match->data;
++              if (!combo_cfg)
++                      return -EINVAL;
++
++              usb_cfg = combo_cfg->usb_cfg;
++              cfg = usb_cfg; /* Setup clks and regulators */
++      }
++
++      /* per PHY serdes; usually located at base address */
++      usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(serdes))
++              return PTR_ERR(serdes);
++
++      /* per PHY dp_com; if PHY has dp_com control block */
++      if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
++              qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
++              if (IS_ERR(qmp->dp_com))
++                      return PTR_ERR(qmp->dp_com);
++      }
++
++      if (combo_cfg) {
++              /* Only two serdes for combo PHY */
++              dp_serdes = devm_platform_ioremap_resource(pdev, 2);
++              if (IS_ERR(dp_serdes))
++                      return PTR_ERR(dp_serdes);
++
++              dp_cfg = combo_cfg->dp_cfg;
++              expected_phys = 2;
++      } else {
++              expected_phys = cfg->nlanes;
++      }
++
++      mutex_init(&qmp->phy_mutex);
++
++      ret = qcom_qmp_phy_clk_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_reset_init(dev, cfg);
++      if (ret)
++              return ret;
++
++      ret = qcom_qmp_phy_vreg_init(dev, cfg);
++      if (ret) {
++              if (ret != -EPROBE_DEFER)
++                      dev_err(dev, "failed to get regulator supplies: %d\n",
++                              ret);
++              return ret;
++      }
++
++      num = of_get_available_child_count(dev->of_node);
++      /* do we have a rogue child node ? */
++      if (num > expected_phys)
++              return -EINVAL;
++
++      qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
++      if (!qmp->phys)
++              return -ENOMEM;
++
++      pm_runtime_set_active(dev);
++      pm_runtime_enable(dev);
++      /*
++       * Prevent runtime pm from being ON by default. Users can enable
++       * it using power/control in sysfs.
++       */
++      pm_runtime_forbid(dev);
++
++      id = 0;
++      for_each_available_child_of_node(dev->of_node, child) {
++              if (of_node_name_eq(child, "dp-phy")) {
++                      cfg = dp_cfg;
++                      serdes = dp_serdes;
++              } else if (of_node_name_eq(child, "usb3-phy")) {
++                      cfg = usb_cfg;
++                      serdes = usb_serdes;
++              }
++
++              /* Create per-lane phy */
++              ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
++              if (ret) {
++                      dev_err(dev, "failed to create lane%d phy, %d\n",
++                              id, ret);
++                      goto err_node_put;
++              }
++
++              /*
++               * Register the pipe clock provided by phy.
++               * See function description to see details of this pipe clock.
++               */
++              if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
++                      ret = phy_pipe_clk_register(qmp, child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register pipe clock source\n");
++                              goto err_node_put;
++                      }
++              } else if (cfg->type == PHY_TYPE_DP) {
++                      ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
++                      if (ret) {
++                              dev_err(qmp->dev,
++                                      "failed to register DP clock source\n");
++                              goto err_node_put;
++                      }
++              }
++              id++;
++      }
++
++      phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++      if (!IS_ERR(phy_provider))
++              dev_info(dev, "Registered Qcom-QMP phy\n");
++      else
++              pm_runtime_disable(dev);
++
++      return PTR_ERR_OR_ZERO(phy_provider);
++
++err_node_put:
++      pm_runtime_disable(dev);
++      of_node_put(child);
++      return ret;
++}
++
++static struct platform_driver qcom_qmp_phy_driver = {
++      .probe          = qcom_qmp_phy_probe,
++      .driver = {
++              .name   = "qcom-qmp-phy",
++              .pm     = &qcom_qmp_phy_pm_ops,
++              .of_match_table = qcom_qmp_phy_of_match_table,
++      },
++};
++
++module_platform_driver(qcom_qmp_phy_driver);
++
++MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
++MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
++MODULE_LICENSE("GPL v2");
+-- 
+2.40.1
+

diff --git a/queue-5.10/phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch b/queue-5.10/phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch
new file mode 100644 (file)
index 0000000..a64ab4d
--- /dev/null
+++ b/queue-5.10/phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch
@@ -0,0 +1,52 @@
+From f636412ecec8f65986fb5d90ffa60c13c283e284 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 May 2023 12:38:10 +0200
+Subject: phy: qcom-qmp-pcie-msm8996: fix init-count imbalance
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit e42f110700ed7293700c26145e1ed07ea05ac3f6 ]
+
+The init counter is not decremented on initialisation errors, which
+prevents retrying initialisation.
+
+Add the missing decrement on initialisation errors so that the counter
+reflects the state of the device.
+
+Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
+Cc: stable@vger.kernel.org      # 4.12
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20230502103810.12061-3-johan+linaro@kernel.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+index c7309e981bfb5..96282a118e635 100644
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+@@ -5085,7 +5085,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+       ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
+       if (ret) {
+               dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
+-              goto err_unlock;
++              goto err_decrement_count;
+       }
+ 
+       for (i = 0; i < cfg->num_resets; i++) {
+@@ -5155,7 +5155,8 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
+               reset_control_assert(qmp->resets[i]);
+ err_disable_regulators:
+       regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
+-err_unlock:
++err_decrement_count:
++      qmp->init_count--;
+       mutex_unlock(&qmp->phy_mutex);
+ 
+       return ret;
+-- 
+2.40.1
+

diff --git a/queue-5.10/powerpc-kasan-disable-kcov-in-kasan-code.patch b/queue-5.10/powerpc-kasan-disable-kcov-in-kasan-code.patch
new file mode 100644 (file)
index 0000000..e452be6
--- /dev/null
+++ b/queue-5.10/powerpc-kasan-disable-kcov-in-kasan-code.patch
@@ -0,0 +1,40 @@
+From 951760d6eb2c549d3f4121b7de58d0f6a2ff5d20 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 10 Jul 2023 14:41:43 +1000
+Subject: powerpc/kasan: Disable KCOV in KASAN code
+
+From: Benjamin Gray <bgray@linux.ibm.com>
+
+[ Upstream commit ccb381e1af1ace292153c88eb1fffa5683d16a20 ]
+
+As per the generic KASAN code in mm/kasan, disable KCOV with
+KCOV_INSTRUMENT := n in the makefile.
+
+This fixes a ppc64 boot hang when KCOV and KASAN are enabled.
+kasan_early_init() gets called before a PACA is initialised, but the
+KCOV hook expects a valid PACA.
+
+Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
+Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://msgid.link/20230710044143.146840-1-bgray@linux.ibm.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/mm/kasan/Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/powerpc/mm/kasan/Makefile b/arch/powerpc/mm/kasan/Makefile
+index bb1a5408b86b2..8636b17c6a20f 100644
+--- a/arch/powerpc/mm/kasan/Makefile
++++ b/arch/powerpc/mm/kasan/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+ KASAN_SANITIZE := n
++KCOV_INSTRUMENT := n
+ 
+ obj-$(CONFIG_PPC32)           += kasan_init_32.o
+ obj-$(CONFIG_PPC_8xx)         += 8xx.o
+-- 
+2.40.1
+

diff --git a/queue-5.10/quota-fix-warning-in-dqgrab.patch b/queue-5.10/quota-fix-warning-in-dqgrab.patch
new file mode 100644 (file)
index 0000000..e8e7d93
--- /dev/null
+++ b/queue-5.10/quota-fix-warning-in-dqgrab.patch
@@ -0,0 +1,104 @@
+From 06f9687848f4012a3ed2777a7048eb159aed7924 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Jun 2023 22:07:31 +0800
+Subject: quota: fix warning in dqgrab()
+
+From: Ye Bin <yebin10@huawei.com>
+
+[ Upstream commit d6a95db3c7ad160bc16b89e36449705309b52bcb ]
+
+There's issue as follows when do fault injection:
+WARNING: CPU: 1 PID: 14870 at include/linux/quotaops.h:51 dquot_disable+0x13b7/0x18c0
+Modules linked in:
+CPU: 1 PID: 14870 Comm: fsconfig Not tainted 6.3.0-next-20230505-00006-g5107a9c821af-dirty #541
+RIP: 0010:dquot_disable+0x13b7/0x18c0
+RSP: 0018:ffffc9000acc79e0 EFLAGS: 00010246
+RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffff88825e41b980
+RDX: 0000000000000000 RSI: ffff88825e41b980 RDI: 0000000000000002
+RBP: ffff888179f68000 R08: ffffffff82087ca7 R09: 0000000000000000
+R10: 0000000000000001 R11: ffffed102f3ed026 R12: ffff888179f68130
+R13: ffff888179f68110 R14: dffffc0000000000 R15: ffff888179f68118
+FS:  00007f450a073740(0000) GS:ffff88882fc00000(0000) knlGS:0000000000000000
+CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+CR2: 00007ffe96f2efd8 CR3: 000000025c8ad000 CR4: 00000000000006e0
+DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+Call Trace:
+ <TASK>
+ dquot_load_quota_sb+0xd53/0x1060
+ dquot_resume+0x172/0x230
+ ext4_reconfigure+0x1dc6/0x27b0
+ reconfigure_super+0x515/0xa90
+ __x64_sys_fsconfig+0xb19/0xd20
+ do_syscall_64+0x39/0xb0
+ entry_SYSCALL_64_after_hwframe+0x63/0xcd
+
+Above issue may happens as follows:
+ProcessA              ProcessB                    ProcessC
+sys_fsconfig
+  vfs_fsconfig_locked
+   reconfigure_super
+     ext4_remount
+      dquot_suspend -> suspend all type quota
+
+                 sys_fsconfig
+                  vfs_fsconfig_locked
+                    reconfigure_super
+                     ext4_remount
+                      dquot_resume
+                       ret = dquot_load_quota_sb
+                        add_dquot_ref
+                                           do_open  -> open file O_RDWR
+                                            vfs_open
+                                             do_dentry_open
+                                              get_write_access
+                                               atomic_inc_unless_negative(&inode->i_writecount)
+                                              ext4_file_open
+                                               dquot_file_open
+                                                dquot_initialize
+                                                  __dquot_initialize
+                                                   dqget
+                                                   atomic_inc(&dquot->dq_count);
+
+                          __dquot_initialize
+                           __dquot_initialize
+                            dqget
+                             if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags))
+                               ext4_acquire_dquot
+                               -> Return error DQ_ACTIVE_B flag isn't set
+                         dquot_disable
+                         invalidate_dquots
+                          if (atomic_read(&dquot->dq_count))
+                           dqgrab
+                            WARN_ON_ONCE(!test_bit(DQ_ACTIVE_B, &dquot->dq_flags))
+                             -> Trigger warning
+
+In the above scenario, 'dquot->dq_flags' has no DQ_ACTIVE_B is normal when
+dqgrab().
+To solve above issue just replace the dqgrab() use in invalidate_dquots() with
+atomic_inc(&dquot->dq_count).
+
+Signed-off-by: Ye Bin <yebin10@huawei.com>
+Signed-off-by: Jan Kara <jack@suse.cz>
+Message-Id: <20230605140731.2427629-3-yebin10@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/quota/dquot.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c
+index 135984a1a52f4..8d0cd68fc90a4 100644
+--- a/fs/quota/dquot.c
++++ b/fs/quota/dquot.c
+@@ -557,7 +557,7 @@ static void invalidate_dquots(struct super_block *sb, int type)
+                       continue;
+               /* Wait for dquot users */
+               if (atomic_read(&dquot->dq_count)) {
+-                      dqgrab(dquot);
++                      atomic_inc(&dquot->dq_count);
+                       spin_unlock(&dq_list_lock);
+                       /*
+                        * Once dqput() wakes us up, we know it's time to free
+-- 
+2.40.1
+

diff --git a/queue-5.10/quota-properly-disable-quotas-when-add_dquot_ref-fai.patch b/queue-5.10/quota-properly-disable-quotas-when-add_dquot_ref-fai.patch
new file mode 100644 (file)
index 0000000..06c761c
--- /dev/null
+++ b/queue-5.10/quota-properly-disable-quotas-when-add_dquot_ref-fai.patch
@@ -0,0 +1,43 @@
+From bf52d06178e6a266ab7e748be7edfea84c1b2b54 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Jun 2023 22:07:30 +0800
+Subject: quota: Properly disable quotas when add_dquot_ref() fails
+
+From: Jan Kara <jack@suse.cz>
+
+[ Upstream commit 6a4e3363792e30177cc3965697e34ddcea8b900b ]
+
+When add_dquot_ref() fails (usually due to IO error or ENOMEM), we want
+to disable quotas we are trying to enable. However dquot_disable() call
+was passed just the flags we are enabling so in case flags ==
+DQUOT_USAGE_ENABLED dquot_disable() call will just fail with EINVAL
+instead of properly disabling quotas. Fix the problem by always passing
+DQUOT_LIMITS_ENABLED | DQUOT_USAGE_ENABLED to dquot_disable() in this
+case.
+
+Reported-and-tested-by: Ye Bin <yebin10@huawei.com>
+Reported-by: syzbot+e633c79ceaecbf479854@syzkaller.appspotmail.com
+Signed-off-by: Jan Kara <jack@suse.cz>
+Message-Id: <20230605140731.2427629-2-yebin10@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/quota/dquot.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c
+index ad255f8ab5c55..135984a1a52f4 100644
+--- a/fs/quota/dquot.c
++++ b/fs/quota/dquot.c
+@@ -2415,7 +2415,8 @@ int dquot_load_quota_sb(struct super_block *sb, int type, int format_id,
+ 
+       error = add_dquot_ref(sb, type);
+       if (error)
+-              dquot_disable(sb, type, flags);
++              dquot_disable(sb, type,
++                            DQUOT_USAGE_ENABLED | DQUOT_LIMITS_ENABLED);
+ 
+       return error;
+ out_fmt:
+-- 
+2.40.1
+

diff --git a/queue-5.10/rdma-mlx5-return-the-firmware-result-upon-destroying.patch b/queue-5.10/rdma-mlx5-return-the-firmware-result-upon-destroying.patch
new file mode 100644 (file)
index 0000000..bb49061
--- /dev/null
+++ b/queue-5.10/rdma-mlx5-return-the-firmware-result-upon-destroying.patch
@@ -0,0 +1,112 @@
+From 1846100f1b30c263aea2c13f535fc187bb014749 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 5 Jun 2023 13:14:07 +0300
+Subject: RDMA/mlx5: Return the firmware result upon destroying QP/RQ
+
+From: Patrisious Haddad <phaddad@nvidia.com>
+
+[ Upstream commit 22664c06e997087fe37f9ba208008c948571214a ]
+
+Previously when destroying a QP/RQ, the result of the firmware
+destruction function was ignored and upper layers weren't informed
+about the failure.
+Which in turn could lead to various problems since when upper layer
+isn't aware of the failure it continues its operation thinking that the
+related QP/RQ was successfully destroyed while it actually wasn't,
+which could lead to the below kernel WARN.
+
+Currently, we return the correct firmware destruction status to upper
+layers which in case of the RQ would be mlx5_ib_destroy_wq() which
+was already capable of handling RQ destruction failure or in case of
+a QP to destroy_qp_common(), which now would actually warn upon qp
+destruction failure.
+
+WARNING: CPU: 3 PID: 995 at drivers/infiniband/core/rdma_core.c:940 uverbs_destroy_ufile_hw+0xcb/0xe0 [ib_uverbs]
+Modules linked in: xt_conntrack xt_MASQUERADE nf_conntrack_netlink nfnetlink xt_addrtype iptable_nat nf_nat br_netfilter rpcrdma rdma_ucm ib_iser libiscsi scsi_transport_iscsi rdma_cm ib_umad ib_ipoib iw_cm ib_cm mlx5_ib ib_uverbs ib_core overlay mlx5_core fuse
+CPU: 3 PID: 995 Comm: python3 Not tainted 5.16.0-rc5+ #1
+Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.13.0-0-gf21b5a4aeb02-prebuilt.qemu.org 04/01/2014
+RIP: 0010:uverbs_destroy_ufile_hw+0xcb/0xe0 [ib_uverbs]
+Code: 41 5c 41 5d 41 5e e9 44 34 f0 e0 48 89 df e8 4c 77 ff ff 49 8b 86 10 01 00 00 48 85 c0 74 a1 4c 89 e7 ff d0 eb 9a 0f 0b eb c1 <0f> 0b be 04 00 00 00 48 89 df e8 b6 f6 ff ff e9 75 ff ff ff 90 0f
+RSP: 0018:ffff8881533e3e78 EFLAGS: 00010287
+RAX: ffff88811b2cf3e0 RBX: ffff888106209700 RCX: 0000000000000000
+RDX: ffff888106209780 RSI: ffff8881533e3d30 RDI: ffff888109b101a0
+RBP: 0000000000000001 R08: ffff888127cb381c R09: 0de9890000000009
+R10: ffff888127cb3800 R11: 0000000000000000 R12: ffff888106209780
+R13: ffff888106209750 R14: ffff888100f20660 R15: 0000000000000000
+FS:  00007f8be353b740(0000) GS:ffff88852c980000(0000) knlGS:0000000000000000
+CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+CR2: 00007f8bd5b117c0 CR3: 000000012cd8a004 CR4: 0000000000370ea0
+DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+Call Trace:
+ <TASK>
+ ib_uverbs_close+0x1a/0x90 [ib_uverbs]
+ __fput+0x82/0x230
+ task_work_run+0x59/0x90
+ exit_to_user_mode_prepare+0x138/0x140
+ syscall_exit_to_user_mode+0x1d/0x50
+ ? __x64_sys_close+0xe/0x40
+ do_syscall_64+0x4a/0x90
+ entry_SYSCALL_64_after_hwframe+0x44/0xae
+RIP: 0033:0x7f8be3ae0abb
+Code: 03 00 00 00 0f 05 48 3d 00 f0 ff ff 77 41 c3 48 83 ec 18 89 7c 24 0c e8 83 43 f9 ff 8b 7c 24 0c 41 89 c0 b8 03 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 35 44 89 c7 89 44 24 0c e8 c1 43 f9 ff 8b 44
+RSP: 002b:00007ffdb51909c0 EFLAGS: 00000293 ORIG_RAX: 0000000000000003
+RAX: 0000000000000000 RBX: 0000557bb7f7c020 RCX: 00007f8be3ae0abb
+RDX: 0000557bb7c74010 RSI: 0000557bb7f14ca0 RDI: 0000000000000005
+RBP: 0000557bb7fbd598 R08: 0000000000000000 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000293 R12: 0000557bb7fbd5b8
+R13: 0000557bb7fbd5a8 R14: 0000000000001000 R15: 0000557bb7f7c020
+ </TASK>
+
+Signed-off-by: Patrisious Haddad <phaddad@nvidia.com>
+Link: https://lore.kernel.org/r/c6df677f931d18090bafbe7f7dbb9524047b7d9b.1685953497.git.leon@kernel.org
+Signed-off-by: Leon Romanovsky <leon@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/infiniband/hw/mlx5/qpc.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/infiniband/hw/mlx5/qpc.c b/drivers/infiniband/hw/mlx5/qpc.c
+index c683d7000168d..9a306da7f9496 100644
+--- a/drivers/infiniband/hw/mlx5/qpc.c
++++ b/drivers/infiniband/hw/mlx5/qpc.c
+@@ -297,8 +297,7 @@ int mlx5_core_destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp)
+       MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
+       MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
+       MLX5_SET(destroy_qp_in, in, uid, qp->uid);
+-      mlx5_cmd_exec_in(dev->mdev, destroy_qp, in);
+-      return 0;
++      return mlx5_cmd_exec_in(dev->mdev, destroy_qp, in);
+ }
+ 
+ int mlx5_core_set_delay_drop(struct mlx5_ib_dev *dev,
+@@ -542,14 +541,14 @@ int mlx5_core_xrcd_dealloc(struct mlx5_ib_dev *dev, u32 xrcdn)
+       return mlx5_cmd_exec_in(dev->mdev, dealloc_xrcd, in);
+ }
+ 
+-static void destroy_rq_tracked(struct mlx5_ib_dev *dev, u32 rqn, u16 uid)
++static int destroy_rq_tracked(struct mlx5_ib_dev *dev, u32 rqn, u16 uid)
+ {
+       u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {};
+ 
+       MLX5_SET(destroy_rq_in, in, opcode, MLX5_CMD_OP_DESTROY_RQ);
+       MLX5_SET(destroy_rq_in, in, rqn, rqn);
+       MLX5_SET(destroy_rq_in, in, uid, uid);
+-      mlx5_cmd_exec_in(dev->mdev, destroy_rq, in);
++      return mlx5_cmd_exec_in(dev->mdev, destroy_rq, in);
+ }
+ 
+ int mlx5_core_create_rq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
+@@ -580,8 +579,7 @@ int mlx5_core_destroy_rq_tracked(struct mlx5_ib_dev *dev,
+                                struct mlx5_core_qp *rq)
+ {
+       destroy_resource_common(dev, rq);
+-      destroy_rq_tracked(dev, rq->qpn, rq->uid);
+-      return 0;
++      return destroy_rq_tracked(dev, rq->qpn, rq->uid);
+ }
+ 
+ static void destroy_sq_tracked(struct mlx5_ib_dev *dev, u32 sqn, u16 uid)
+-- 
+2.40.1
+

diff --git a/queue-5.10/ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch b/queue-5.10/ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch
new file mode 100644 (file)
index 0000000..6ddad06
--- /dev/null
+++ b/queue-5.10/ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch
@@ -0,0 +1,243 @@
+From a6f0c2db8368eff0de8b24358bb59684cd550715 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 19 Jul 2023 15:58:47 +0800
+Subject: ring-buffer: Do not swap cpu_buffer during resize process
+
+From: Chen Lin <chen.lin5@zte.com.cn>
+
+[ Upstream commit 8a96c0288d0737ad77882024974c075345c72011 ]
+
+When ring_buffer_swap_cpu was called during resize process,
+the cpu buffer was swapped in the middle, resulting in incorrect state.
+Continuing to run in the wrong state will result in oops.
+
+This issue can be easily reproduced using the following two scripts:
+/tmp # cat test1.sh
+//#! /bin/sh
+for i in `seq 0 100000`
+do
+         echo 2000 > /sys/kernel/debug/tracing/buffer_size_kb
+         sleep 0.5
+         echo 5000 > /sys/kernel/debug/tracing/buffer_size_kb
+         sleep 0.5
+done
+/tmp # cat test2.sh
+//#! /bin/sh
+for i in `seq 0 100000`
+do
+        echo irqsoff > /sys/kernel/debug/tracing/current_tracer
+        sleep 1
+        echo nop > /sys/kernel/debug/tracing/current_tracer
+        sleep 1
+done
+/tmp # ./test1.sh &
+/tmp # ./test2.sh &
+
+A typical oops log is as follows, sometimes with other different oops logs.
+
+[  231.711293] WARNING: CPU: 0 PID: 9 at kernel/trace/ring_buffer.c:2026 rb_update_pages+0x378/0x3f8
+[  231.713375] Modules linked in:
+[  231.714735] CPU: 0 PID: 9 Comm: kworker/0:1 Tainted: G        W          6.5.0-rc1-00276-g20edcec23f92 #15
+[  231.716750] Hardware name: linux,dummy-virt (DT)
+[  231.718152] Workqueue: events update_pages_handler
+[  231.719714] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+[  231.721171] pc : rb_update_pages+0x378/0x3f8
+[  231.722212] lr : rb_update_pages+0x25c/0x3f8
+[  231.723248] sp : ffff800082b9bd50
+[  231.724169] x29: ffff800082b9bd50 x28: ffff8000825f7000 x27: 0000000000000000
+[  231.726102] x26: 0000000000000001 x25: fffffffffffff010 x24: 0000000000000ff0
+[  231.728122] x23: ffff0000c3a0b600 x22: ffff0000c3a0b5c0 x21: fffffffffffffe0a
+[  231.730203] x20: ffff0000c3a0b600 x19: ffff0000c0102400 x18: 0000000000000000
+[  231.732329] x17: 0000000000000000 x16: 0000000000000000 x15: 0000ffffe7aa8510
+[  231.734212] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000002
+[  231.736291] x11: ffff8000826998a8 x10: ffff800082b9baf0 x9 : ffff800081137558
+[  231.738195] x8 : fffffc00030e82c8 x7 : 0000000000000000 x6 : 0000000000000001
+[  231.740192] x5 : ffff0000ffbafe00 x4 : 0000000000000000 x3 : 0000000000000000
+[  231.742118] x2 : 00000000000006aa x1 : 0000000000000001 x0 : ffff0000c0007208
+[  231.744196] Call trace:
+[  231.744892]  rb_update_pages+0x378/0x3f8
+[  231.745893]  update_pages_handler+0x1c/0x38
+[  231.746893]  process_one_work+0x1f0/0x468
+[  231.747852]  worker_thread+0x54/0x410
+[  231.748737]  kthread+0x124/0x138
+[  231.749549]  ret_from_fork+0x10/0x20
+[  231.750434] ---[ end trace 0000000000000000 ]---
+[  233.720486] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
+[  233.721696] Mem abort info:
+[  233.721935]   ESR = 0x0000000096000004
+[  233.722283]   EC = 0x25: DABT (current EL), IL = 32 bits
+[  233.722596]   SET = 0, FnV = 0
+[  233.722805]   EA = 0, S1PTW = 0
+[  233.723026]   FSC = 0x04: level 0 translation fault
+[  233.723458] Data abort info:
+[  233.723734]   ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
+[  233.724176]   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
+[  233.724589]   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
+[  233.725075] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000104943000
+[  233.725592] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000
+[  233.726231] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
+[  233.726720] Modules linked in:
+[  233.727007] CPU: 0 PID: 9 Comm: kworker/0:1 Tainted: G        W          6.5.0-rc1-00276-g20edcec23f92 #15
+[  233.727777] Hardware name: linux,dummy-virt (DT)
+[  233.728225] Workqueue: events update_pages_handler
+[  233.728655] pstate: 200000c5 (nzCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+[  233.729054] pc : rb_update_pages+0x1a8/0x3f8
+[  233.729334] lr : rb_update_pages+0x154/0x3f8
+[  233.729592] sp : ffff800082b9bd50
+[  233.729792] x29: ffff800082b9bd50 x28: ffff8000825f7000 x27: 0000000000000000
+[  233.730220] x26: 0000000000000000 x25: ffff800082a8b840 x24: ffff0000c0102418
+[  233.730653] x23: 0000000000000000 x22: fffffc000304c880 x21: 0000000000000003
+[  233.731105] x20: 00000000000001f4 x19: ffff0000c0102400 x18: ffff800082fcbc58
+[  233.731727] x17: 0000000000000000 x16: 0000000000000001 x15: 0000000000000001
+[  233.732282] x14: ffff8000825fe0c8 x13: 0000000000000001 x12: 0000000000000000
+[  233.732709] x11: ffff8000826998a8 x10: 0000000000000ae0 x9 : ffff8000801b760c
+[  233.733148] x8 : fefefefefefefeff x7 : 0000000000000018 x6 : ffff0000c03298c0
+[  233.733553] x5 : 0000000000000002 x4 : 0000000000000000 x3 : 0000000000000000
+[  233.733972] x2 : ffff0000c3a0b600 x1 : 0000000000000000 x0 : 0000000000000000
+[  233.734418] Call trace:
+[  233.734593]  rb_update_pages+0x1a8/0x3f8
+[  233.734853]  update_pages_handler+0x1c/0x38
+[  233.735148]  process_one_work+0x1f0/0x468
+[  233.735525]  worker_thread+0x54/0x410
+[  233.735852]  kthread+0x124/0x138
+[  233.736064]  ret_from_fork+0x10/0x20
+[  233.736387] Code: 92400000 910006b5 aa000021 aa0303f7 (f9400060)
+[  233.736959] ---[ end trace 0000000000000000 ]---
+
+After analysis, the seq of the error is as follows [1-5]:
+
+int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+                       int cpu_id)
+{
+       for_each_buffer_cpu(buffer, cpu) {
+               cpu_buffer = buffer->buffers[cpu];
+               //1. get cpu_buffer, aka cpu_buffer(A)
+               ...
+               ...
+               schedule_work_on(cpu,
+                &cpu_buffer->update_pages_work);
+               //2. 'update_pages_work' is queue on 'cpu', cpu_buffer(A) is passed to
+               // update_pages_handler, do the update process, set 'update_done' in
+               // complete(&cpu_buffer->update_done) and to wakeup resize process.
+       //---->
+               //3. Just at this moment, ring_buffer_swap_cpu is triggered,
+               //cpu_buffer(A) be swaped to cpu_buffer(B), the max_buffer.
+               //ring_buffer_swap_cpu is called as the 'Call trace' below.
+
+               Call trace:
+                dump_backtrace+0x0/0x2f8
+                show_stack+0x18/0x28
+                dump_stack+0x12c/0x188
+                ring_buffer_swap_cpu+0x2f8/0x328
+                update_max_tr_single+0x180/0x210
+                check_critical_timing+0x2b4/0x2c8
+                tracer_hardirqs_on+0x1c0/0x200
+                trace_hardirqs_on+0xec/0x378
+                el0_svc_common+0x64/0x260
+                do_el0_svc+0x90/0xf8
+                el0_svc+0x20/0x30
+                el0_sync_handler+0xb0/0xb8
+                el0_sync+0x180/0x1c0
+       //<----
+
+       /* wait for all the updates to complete */
+       for_each_buffer_cpu(buffer, cpu) {
+               cpu_buffer = buffer->buffers[cpu];
+               //4. get cpu_buffer, cpu_buffer(B) is used in the following process,
+               //the state of cpu_buffer(A) and cpu_buffer(B) is totally wrong.
+               //for example, cpu_buffer(A)->update_done will leave be set 1, and will
+               //not 'wait_for_completion' at the next resize round.
+                 if (!cpu_buffer->nr_pages_to_update)
+                       continue;
+
+               if (cpu_online(cpu))
+                       wait_for_completion(&cpu_buffer->update_done);
+               cpu_buffer->nr_pages_to_update = 0;
+       }
+       ...
+}
+       //5. the state of cpu_buffer(A) and cpu_buffer(B) is totally wrong,
+       //Continuing to run in the wrong state, then oops occurs.
+
+Link: https://lore.kernel.org/linux-trace-kernel/202307191558478409990@zte.com.cn
+
+Signed-off-by: Chen Lin <chen.lin5@zte.com.cn>
+Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/ring_buffer.c | 14 +++++++++++++-
+ kernel/trace/trace.c       |  3 ++-
+ 2 files changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
+index 3b8c53264441e..f8126fa0630e2 100644
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -541,6 +541,7 @@ struct trace_buffer {
+       unsigned                        flags;
+       int                             cpus;
+       atomic_t                        record_disabled;
++      atomic_t                        resizing;
+       cpumask_var_t                   cpumask;
+ 
+       struct lock_class_key           *reader_lock_key;
+@@ -2041,7 +2042,7 @@ int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+ 
+       /* prevent another thread from changing buffer sizes */
+       mutex_lock(&buffer->mutex);
+-
++      atomic_inc(&buffer->resizing);
+ 
+       if (cpu_id == RING_BUFFER_ALL_CPUS) {
+               /*
+@@ -2184,6 +2185,7 @@ int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+               atomic_dec(&buffer->record_disabled);
+       }
+ 
++      atomic_dec(&buffer->resizing);
+       mutex_unlock(&buffer->mutex);
+       return 0;
+ 
+@@ -2204,6 +2206,7 @@ int ring_buffer_resize(struct trace_buffer *buffer, unsigned long size,
+               }
+       }
+  out_err_unlock:
++      atomic_dec(&buffer->resizing);
+       mutex_unlock(&buffer->mutex);
+       return err;
+ }
+@@ -5253,6 +5256,15 @@ int ring_buffer_swap_cpu(struct trace_buffer *buffer_a,
+       if (local_read(&cpu_buffer_b->committing))
+               goto out_dec;
+ 
++      /*
++       * When resize is in progress, we cannot swap it because
++       * it will mess the state of the cpu buffer.
++       */
++      if (atomic_read(&buffer_a->resizing))
++              goto out_dec;
++      if (atomic_read(&buffer_b->resizing))
++              goto out_dec;
++
+       buffer_a->buffers[cpu] = cpu_buffer_b;
+       buffer_b->buffers[cpu] = cpu_buffer_a;
+ 
+diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
+index 7e99319bd5365..167f2a19fd8a2 100644
+--- a/kernel/trace/trace.c
++++ b/kernel/trace/trace.c
+@@ -1882,9 +1882,10 @@ update_max_tr_single(struct trace_array *tr, struct task_struct *tsk, int cpu)
+                * place on this CPU. We fail to record, but we reset
+                * the max trace buffer (no one writes directly to it)
+                * and flag that it failed.
++               * Another reason is resize is in progress.
+                */
+               trace_array_printk_buf(tr->max_buffer.buffer, _THIS_IP_,
+-                      "Failed to swap buffers due to commit in progress\n");
++                      "Failed to swap buffers due to commit or resize in progress\n");
+       }
+ 
+       WARN_ON_ONCE(ret && ret != -EAGAIN && ret != -EBUSY);
+-- 
+2.40.1
+

diff --git a/queue-5.10/series b/queue-5.10/series
new file mode 100644 (file)
index 0000000..23066ce
--- /dev/null
+++ b/queue-5.10/series
@@ -0,0 +1,71 @@
+mmc-sdhci-f-sdh30-replace-with-sdhci_pltfm.patch
+macsec-fix-traffic-counters-statistics.patch
+macsec-use-dev_stats_inc.patch
+net-mlx5-refactor-init-clock-function.patch
+net-mlx5-move-all-internal-timer-metadata-into-a-ded.patch
+net-mlx5-skip-clock-update-work-when-device-is-in-er.patch
+drm-radeon-fix-integer-overflow-in-radeon_cs_parser_.patch
+alsa-emu10k1-roll-up-loops-in-dsp-setup-code-for-aud.patch
+asoc-intel-sof_sdw-add-quirk-for-mtl-rvp.patch
+asoc-intel-sof_sdw-add-quirk-for-lnl-rvp.patch
+pci-tegra194-fix-possible-array-out-of-bounds-access.patch
+arm-dts-imx6dl-prtrvt-prtvt7-prti6q-prtwd2-fix-usb-r.patch
+asoc-intel-sof_sdw-add-support-for-rex-soundwire.patch
+iopoll-call-cpu_relax-in-busy-loops.patch
+quota-properly-disable-quotas-when-add_dquot_ref-fai.patch
+quota-fix-warning-in-dqgrab.patch
+dma-remap-use-kvmalloc_array-kvfree-for-larger-dma-m.patch
+drm-amdgpu-install-stub-fence-into-potential-unused-.patch
+hid-add-quirk-for-03f0-464a-hp-elite-presenter-mouse.patch
+rdma-mlx5-return-the-firmware-result-upon-destroying.patch
+ovl-check-type-and-offset-of-struct-vfsmount-in-ovl_.patch
+udf-fix-uninitialized-array-access-for-some-pathname.patch
+fs-jfs-fix-ubsan-array-index-out-of-bounds-in-dballo.patch
+mips-dec-prom-address-warray-bounds-warning.patch
+fs-jfs-fix-null-ptr-deref-read-in-txbegin.patch
+fs-jfs-check-for-read-only-mounted-filesystem-in-txb.patch
+media-v4l2-mem2mem-add-lock-to-protect-parameter-num.patch
+usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch
+media-platform-mediatek-vpu-fix-null-ptr-dereference.patch
+usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch
+usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch
+gfs2-fix-possible-data-races-in-gfs2_show_options.patch
+pcmcia-rsrc_nonstatic-fix-memory-leak-in-nonstatic_r.patch
+bluetooth-l2cap-fix-use-after-free.patch
+bluetooth-btusb-add-mt7922-bluetooth-id-for-the-asus.patch
+drm-amdgpu-fix-potential-fence-use-after-free-v2.patch
+alsa-hda-realtek-add-quirks-for-unis-h3c-desktop-b76.patch
+alsa-hda-fix-a-possible-null-pointer-dereference-due.patch
+apparmor-fix-use-of-strcpy-in-policy_unpack_test.patch
+powerpc-kasan-disable-kcov-in-kasan-code.patch
+ring-buffer-do-not-swap-cpu_buffer-during-resize-pro.patch
+ima-allow-fix-uml-builds.patch
+iio-add-addac-subdirectory.patch
+dt-bindings-iio-add-ad74413r.patch
+iio-adc-stx104-utilize-iomap-interface.patch
+iio-adc-stx104-implement-and-utilize-register-struct.patch
+iio-addac-stx104-fix-race-condition-for-stx104_write.patch
+iio-addac-stx104-fix-race-condition-when-converting-.patch
+bus-mhi-add-mhi-pci-support-for-wwan-modems.patch
+bus-mhi-add-mmio-region-length-to-controller-structu.patch
+bus-mhi-move-host-mhi-code-to-host-directory.patch
+bus-mhi-host-range-check-chdboff-and-erdboff.patch
+irqchip-mips-gic-get-rid-of-the-reliance-on-irq_cpu_.patch
+irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch
+usb-cdnsp-device-side-header-file-for-cdnsp-driver.patch
+usb-gadget-udc-core-introduce-check_config-to-verify.patch
+usb-cdns3-allocate-tx-fifo-size-according-to-composi.patch
+usb-cdns3-fix-ncm-gadget-rx-speed-20x-slow-than-expe.patch
+phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
+phy-qcom-qmp-combo-fix-init-count-imbalance.patch
+phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch
+usb-dwc3-qcom-fix-null-deref-on-suspend.patch
+mmc-sdhci-spear-fix-deferred-probing.patch
+mmc-bcm2835-fix-deferred-probing.patch
+mmc-sunxi-fix-deferred-probing.patch
+mmc-core-add-devm_mmc_alloc_host.patch
+mmc-meson-gx-use-devm_mmc_alloc_host.patch
+mmc-meson-gx-fix-deferred-probing.patch
+tracing-probes-have-process_fetch_insn-take-a-void-i.patch
+tracing-probes-fix-to-update-dynamic-data-counter-if.patch
+net-ncsi-change-from-ndo_set_mac_address-to-dev_set_.patch

diff --git a/queue-5.10/tracing-probes-fix-to-update-dynamic-data-counter-if.patch b/queue-5.10/tracing-probes-fix-to-update-dynamic-data-counter-if.patch
new file mode 100644 (file)
index 0000000..dc3c65a
--- /dev/null
+++ b/queue-5.10/tracing-probes-fix-to-update-dynamic-data-counter-if.patch
@@ -0,0 +1,54 @@
+From 9acb7d2b0dfbf735d4e03553a223690b37baa88c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 11 Jul 2023 23:15:48 +0900
+Subject: tracing/probes: Fix to update dynamic data counter if fetcharg uses
+ it
+
+From: Masami Hiramatsu (Google) <mhiramat@kernel.org>
+
+[ Upstream commit e38e2c6a9efc435f9de344b7c91f7697e01b47d5 ]
+
+Fix to update dynamic data counter ('dyndata') and max length ('maxlen')
+only if the fetcharg uses the dynamic data. Also get out arg->dynamic
+from unlikely(). This makes dynamic data address wrong if
+process_fetch_insn() returns error on !arg->dynamic case.
+
+Link: https://lore.kernel.org/all/168908494781.123124.8160245359962103684.stgit@devnote2/
+
+Suggested-by: Steven Rostedt <rostedt@goodmis.org>
+Link: https://lore.kernel.org/all/20230710233400.5aaf024e@gandalf.local.home/
+Fixes: 9178412ddf5a ("tracing: probeevent: Return consumed bytes of dynamic area")
+Cc: stable@vger.kernel.org
+Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
+Reviewed-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/trace_probe_tmpl.h | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/trace/trace_probe_tmpl.h b/kernel/trace/trace_probe_tmpl.h
+index bbb479b3ba8fd..cf14a37dff8c8 100644
+--- a/kernel/trace/trace_probe_tmpl.h
++++ b/kernel/trace/trace_probe_tmpl.h
+@@ -206,11 +206,13 @@ store_trace_args(void *data, struct trace_probe *tp, void *rec,
+               if (unlikely(arg->dynamic))
+                       *dl = make_data_loc(maxlen, dyndata - base);
+               ret = process_fetch_insn(arg->code, rec, dl, base);
+-              if (unlikely(ret < 0 && arg->dynamic)) {
+-                      *dl = make_data_loc(0, dyndata - base);
+-              } else {
+-                      dyndata += ret;
+-                      maxlen -= ret;
++              if (arg->dynamic) {
++                      if (unlikely(ret < 0)) {
++                              *dl = make_data_loc(0, dyndata - base);
++                      } else {
++                              dyndata += ret;
++                              maxlen -= ret;
++                      }
+               }
+       }
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.10/tracing-probes-have-process_fetch_insn-take-a-void-i.patch b/queue-5.10/tracing-probes-have-process_fetch_insn-take-a-void-i.patch
new file mode 100644 (file)
index 0000000..24b1e56
--- /dev/null
+++ b/queue-5.10/tracing-probes-have-process_fetch_insn-take-a-void-i.patch
@@ -0,0 +1,97 @@
+From 24f3408d4c9c4a167042d42ca008cda21a18bfa5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 19 Aug 2021 00:13:28 -0400
+Subject: tracing/probes: Have process_fetch_insn() take a void * instead of
+ pt_regs
+
+From: Steven Rostedt (VMware) <rostedt@goodmis.org>
+
+[ Upstream commit 8565a45d0858078b63c7d84074a21a42ba9ebf01 ]
+
+In preparation to allow event probes to use the process_fetch_insn()
+callback in trace_probe_tmpl.h, change the data passed to it from a
+pointer to pt_regs, as the event probe will not be using regs, and make it
+a void pointer instead.
+
+Update the process_fetch_insn() callers for kprobe and uprobe events to
+have the regs defined in the function and just typecast the void pointer
+parameter.
+
+Link: https://lkml.kernel.org/r/20210819041842.291622924@goodmis.org
+
+Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+Stable-dep-of: e38e2c6a9efc ("tracing/probes: Fix to update dynamic data counter if fetcharg uses it")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/trace_kprobe.c     | 3 ++-
+ kernel/trace/trace_probe_tmpl.h | 6 +++---
+ kernel/trace/trace_uprobe.c     | 3 ++-
+ 3 files changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c
+index 41dd17390c732..b882c6519b035 100644
+--- a/kernel/trace/trace_kprobe.c
++++ b/kernel/trace/trace_kprobe.c
+@@ -1332,9 +1332,10 @@ probe_mem_read(void *dest, void *src, size_t size)
+ 
+ /* Note that we don't verify it, since the code does not come from user space */
+ static int
+-process_fetch_insn(struct fetch_insn *code, struct pt_regs *regs, void *dest,
++process_fetch_insn(struct fetch_insn *code, void *rec, void *dest,
+                  void *base)
+ {
++      struct pt_regs *regs = rec;
+       unsigned long val;
+ 
+ retry:
+diff --git a/kernel/trace/trace_probe_tmpl.h b/kernel/trace/trace_probe_tmpl.h
+index 29348874ebde7..bbb479b3ba8fd 100644
+--- a/kernel/trace/trace_probe_tmpl.h
++++ b/kernel/trace/trace_probe_tmpl.h
+@@ -54,7 +54,7 @@ fetch_apply_bitfield(struct fetch_insn *code, void *buf)
+  * If dest is NULL, don't store result and return required dynamic data size.
+  */
+ static int
+-process_fetch_insn(struct fetch_insn *code, struct pt_regs *regs,
++process_fetch_insn(struct fetch_insn *code, void *rec,
+                  void *dest, void *base);
+ static nokprobe_inline int fetch_store_strlen(unsigned long addr);
+ static nokprobe_inline int
+@@ -190,7 +190,7 @@ __get_data_size(struct trace_probe *tp, struct pt_regs *regs)
+ 
+ /* Store the value of each argument */
+ static nokprobe_inline void
+-store_trace_args(void *data, struct trace_probe *tp, struct pt_regs *regs,
++store_trace_args(void *data, struct trace_probe *tp, void *rec,
+                int header_size, int maxlen)
+ {
+       struct probe_arg *arg;
+@@ -205,7 +205,7 @@ store_trace_args(void *data, struct trace_probe *tp, struct pt_regs *regs,
+               /* Point the dynamic data area if needed */
+               if (unlikely(arg->dynamic))
+                       *dl = make_data_loc(maxlen, dyndata - base);
+-              ret = process_fetch_insn(arg->code, regs, dl, base);
++              ret = process_fetch_insn(arg->code, rec, dl, base);
+               if (unlikely(ret < 0 && arg->dynamic)) {
+                       *dl = make_data_loc(0, dyndata - base);
+               } else {
+diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c
+index 9900d4e3808cc..f6c47361c154e 100644
+--- a/kernel/trace/trace_uprobe.c
++++ b/kernel/trace/trace_uprobe.c
+@@ -217,9 +217,10 @@ static unsigned long translate_user_vaddr(unsigned long file_offset)
+ 
+ /* Note that we don't verify it, since the code does not come from user space */
+ static int
+-process_fetch_insn(struct fetch_insn *code, struct pt_regs *regs, void *dest,
++process_fetch_insn(struct fetch_insn *code, void *rec, void *dest,
+                  void *base)
+ {
++      struct pt_regs *regs = rec;
+       unsigned long val;
+ 
+       /* 1st stage: get value from context */
+-- 
+2.40.1
+

diff --git a/queue-5.10/udf-fix-uninitialized-array-access-for-some-pathname.patch b/queue-5.10/udf-fix-uninitialized-array-access-for-some-pathname.patch
new file mode 100644 (file)
index 0000000..0dfc95d
--- /dev/null
+++ b/queue-5.10/udf-fix-uninitialized-array-access-for-some-pathname.patch
@@ -0,0 +1,39 @@
+From 354db2f86849b43e2031dba7d6477366bcd73b1f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 21 Jun 2023 11:32:35 +0200
+Subject: udf: Fix uninitialized array access for some pathnames
+
+From: Jan Kara <jack@suse.cz>
+
+[ Upstream commit 028f6055c912588e6f72722d89c30b401bbcf013 ]
+
+For filenames that begin with . and are between 2 and 5 characters long,
+UDF charset conversion code would read uninitialized memory in the
+output buffer. The only practical impact is that the name may be prepended a
+"unification hash" when it is not actually needed but still it is good
+to fix this.
+
+Reported-by: syzbot+cd311b1e43cc25f90d18@syzkaller.appspotmail.com
+Link: https://lore.kernel.org/all/000000000000e2638a05fe9dc8f9@google.com
+Signed-off-by: Jan Kara <jack@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/udf/unicode.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/fs/udf/unicode.c b/fs/udf/unicode.c
+index 622569007b530..2142cbd1dde24 100644
+--- a/fs/udf/unicode.c
++++ b/fs/udf/unicode.c
+@@ -247,7 +247,7 @@ static int udf_name_from_CS0(struct super_block *sb,
+       }
+ 
+       if (translate) {
+-              if (str_o_len <= 2 && str_o[0] == '.' &&
++              if (str_o_len > 0 && str_o_len <= 2 && str_o[0] == '.' &&
+                   (str_o_len == 1 || str_o[1] == '.'))
+                       needsCRC = 1;
+               if (needsCRC) {
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-cdns3-allocate-tx-fifo-size-according-to-composi.patch b/queue-5.10/usb-cdns3-allocate-tx-fifo-size-according-to-composi.patch
new file mode 100644 (file)
index 0000000..15b2c1f
--- /dev/null
+++ b/queue-5.10/usb-cdns3-allocate-tx-fifo-size-according-to-composi.patch
@@ -0,0 +1,192 @@
+From dac5893ffa1be6b839081af4c8facc9412ecf5eb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 9 May 2022 11:40:55 -0500
+Subject: usb: cdns3: allocate TX FIFO size according to composite EP number
+
+From: Frank Li <Frank.Li@nxp.com>
+
+[ Upstream commit dce49449e04ff150838a31386ee65917beb9ebb5 ]
+
+Some devices have USB compositions which may require multiple endpoints.
+To get better performance, need bigger CDNS3_EP_BUF_SIZE.
+
+But bigger CDNS3_EP_BUF_SIZE may exceed total hardware FIFO size when
+multiple endpoints.
+
+By introducing the check_config() callback, calculate CDNS3_EP_BUF_SIZE.
+
+Move CDNS3_EP_BUF_SIZE into cnds3_device: ep_buf_size
+Combine CDNS3_EP_ISO_SS_BURST and CDNS3_EP_ISO_HS_MULT into
+cnds3_device:ep_iso_burst
+
+Using a simple algorithm to calculate ep_buf_size.
+ep_buf_size = ep_iso_burst = (onchip_buffers - 2k) / (number of IN EP +
+1).
+
+Test at 8qxp:
+
+       Gadget                  ep_buf_size
+
+       RNDIS:                          5
+       RNDIS+ACM:                      3
+       Mass Storage + NCM + ACM        2
+
+Previous CDNS3_EP_BUF_SIZE is 4, RNDIS + ACM will be failure because
+exceed FIFO memory.
+
+Acked-by: Peter Chen <peter.chen@kernel.org>
+Signed-off-by: Frank Li <Frank.Li@nxp.com>
+Link: https://lore.kernel.org/r/20220509164055.1815081-1-Frank.Li@nxp.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: dbe678f6192f ("usb: cdns3: fix NCM gadget RX speed 20x slow than expection at iMX8QM")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/cdns3/gadget.c | 47 ++++++++++++++++++++++++++++++++++----
+ drivers/usb/cdns3/gadget.h |  9 +++++---
+ 2 files changed, 49 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
+index e3a8b6c71aa1d..24dab7006b823 100644
+--- a/drivers/usb/cdns3/gadget.c
++++ b/drivers/usb/cdns3/gadget.c
+@@ -2041,7 +2041,7 @@ int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable)
+       u8 mult = 0;
+       int ret;
+ 
+-      buffering = CDNS3_EP_BUF_SIZE - 1;
++      buffering = priv_dev->ep_buf_size - 1;
+ 
+       cdns3_configure_dmult(priv_dev, priv_ep);
+ 
+@@ -2060,7 +2060,7 @@ int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable)
+               break;
+       default:
+               ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC);
+-              mult = CDNS3_EP_ISO_HS_MULT - 1;
++              mult = priv_dev->ep_iso_burst - 1;
+               buffering = mult + 1;
+       }
+ 
+@@ -2076,14 +2076,14 @@ int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable)
+               mult = 0;
+               max_packet_size = 1024;
+               if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
+-                      maxburst = CDNS3_EP_ISO_SS_BURST - 1;
++                      maxburst = priv_dev->ep_iso_burst - 1;
+                       buffering = (mult + 1) *
+                                   (maxburst + 1);
+ 
+                       if (priv_ep->interval > 1)
+                               buffering++;
+               } else {
+-                      maxburst = CDNS3_EP_BUF_SIZE - 1;
++                      maxburst = priv_dev->ep_buf_size - 1;
+               }
+               break;
+       default:
+@@ -2098,6 +2098,10 @@ int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable)
+       else
+               priv_ep->trb_burst_size = 16;
+ 
++      mult = min_t(u8, mult, EP_CFG_MULT_MAX);
++      buffering = min_t(u8, buffering, EP_CFG_BUFFERING_MAX);
++      maxburst = min_t(u8, maxburst, EP_CFG_MAXBURST_MAX);
++
+       /* onchip buffer is only allocated before configuration */
+       if (!priv_dev->hw_configured_flag) {
+               ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
+@@ -2971,6 +2975,40 @@ static int cdns3_gadget_udc_stop(struct usb_gadget *gadget)
+       return 0;
+ }
+ 
++/**
++ * cdns3_gadget_check_config - ensure cdns3 can support the USB configuration
++ * @gadget: pointer to the USB gadget
++ *
++ * Used to record the maximum number of endpoints being used in a USB composite
++ * device. (across all configurations)  This is to be used in the calculation
++ * of the TXFIFO sizes when resizing internal memory for individual endpoints.
++ * It will help ensured that the resizing logic reserves enough space for at
++ * least one max packet.
++ */
++static int cdns3_gadget_check_config(struct usb_gadget *gadget)
++{
++      struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
++      struct usb_ep *ep;
++      int n_in = 0;
++      int total;
++
++      list_for_each_entry(ep, &gadget->ep_list, ep_list) {
++              if (ep->claimed && (ep->address & USB_DIR_IN))
++                      n_in++;
++      }
++
++      /* 2KB are reserved for EP0, 1KB for out*/
++      total = 2 + n_in + 1;
++
++      if (total > priv_dev->onchip_buffers)
++              return -ENOMEM;
++
++      priv_dev->ep_buf_size = priv_dev->ep_iso_burst =
++                      (priv_dev->onchip_buffers - 2) / (n_in + 1);
++
++      return 0;
++}
++
+ static const struct usb_gadget_ops cdns3_gadget_ops = {
+       .get_frame = cdns3_gadget_get_frame,
+       .wakeup = cdns3_gadget_wakeup,
+@@ -2979,6 +3017,7 @@ static const struct usb_gadget_ops cdns3_gadget_ops = {
+       .udc_start = cdns3_gadget_udc_start,
+       .udc_stop = cdns3_gadget_udc_stop,
+       .match_ep = cdns3_gadget_match_ep,
++      .check_config = cdns3_gadget_check_config,
+ };
+ 
+ static void cdns3_free_all_eps(struct cdns3_device *priv_dev)
+diff --git a/drivers/usb/cdns3/gadget.h b/drivers/usb/cdns3/gadget.h
+index 21fa461c518ec..32825477edd3e 100644
+--- a/drivers/usb/cdns3/gadget.h
++++ b/drivers/usb/cdns3/gadget.h
+@@ -561,15 +561,18 @@ struct cdns3_usb_regs {
+ /* Max burst size (used only in SS mode). */
+ #define EP_CFG_MAXBURST_MASK  GENMASK(11, 8)
+ #define EP_CFG_MAXBURST(p)    (((p) << 8) & EP_CFG_MAXBURST_MASK)
++#define EP_CFG_MAXBURST_MAX   15
+ /* ISO max burst. */
+ #define EP_CFG_MULT_MASK      GENMASK(15, 14)
+ #define EP_CFG_MULT(p)                (((p) << 14) & EP_CFG_MULT_MASK)
++#define EP_CFG_MULT_MAX               2
+ /* ISO max burst. */
+ #define EP_CFG_MAXPKTSIZE_MASK        GENMASK(26, 16)
+ #define EP_CFG_MAXPKTSIZE(p)  (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
+ /* Max number of buffered packets. */
+ #define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
+ #define EP_CFG_BUFFERING(p)   (((p) << 27) & EP_CFG_BUFFERING_MASK)
++#define EP_CFG_BUFFERING_MAX  15
+ 
+ /* EP_CMD - bitmasks */
+ /* Endpoint reset. */
+@@ -1093,9 +1096,6 @@ struct cdns3_trb {
+ #define CDNS3_ENDPOINTS_MAX_COUNT     32
+ #define CDNS3_EP_ZLP_BUF_SIZE         1024
+ 
+-#define CDNS3_EP_BUF_SIZE             4       /* KB */
+-#define CDNS3_EP_ISO_HS_MULT          3
+-#define CDNS3_EP_ISO_SS_BURST         3
+ #define CDNS3_MAX_NUM_DESCMISS_BUF    32
+ #define CDNS3_DESCMIS_BUF_SIZE                2048    /* Bytes */
+ #define CDNS3_WA2_NUM_BUFFERS         128
+@@ -1330,6 +1330,9 @@ struct cdns3_device {
+       /*in KB */
+       u16                             onchip_buffers;
+       u16                             onchip_used_size;
++
++      u16                             ep_buf_size;
++      u16                             ep_iso_burst;
+ };
+ 
+ void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-cdns3-fix-ncm-gadget-rx-speed-20x-slow-than-expe.patch b/queue-5.10/usb-cdns3-fix-ncm-gadget-rx-speed-20x-slow-than-expe.patch
new file mode 100644 (file)
index 0000000..b2451e8
--- /dev/null
+++ b/queue-5.10/usb-cdns3-fix-ncm-gadget-rx-speed-20x-slow-than-expe.patch
@@ -0,0 +1,63 @@
+From cafa7e0b517f7e15e1060be521f38736424777f7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 18 May 2023 11:49:45 -0400
+Subject: usb: cdns3: fix NCM gadget RX speed 20x slow than expection at iMX8QM
+
+From: Frank Li <Frank.Li@nxp.com>
+
+[ Upstream commit dbe678f6192f27879ac9ff6bc7a1036aad85aae9 ]
+
+At iMX8QM platform, enable NCM gadget and run 'iperf3 -s'.
+At host, run 'iperf3 -V -c fe80::6863:98ff:feef:3e0%enxc6e147509498'
+
+[  5]   0.00-1.00   sec  1.55 MBytes  13.0 Mbits/sec   90   4.18 KBytes
+[  5]   1.00-2.00   sec  1.44 MBytes  12.0 Mbits/sec   75   4.18 KBytes
+[  5]   2.00-3.00   sec  1.48 MBytes  12.4 Mbits/sec   75   4.18 KBytes
+
+Expected speed should be bigger than 300Mbits/sec.
+
+The root cause of this performance drop was found to be data corruption
+happening at 4K borders in some Ethernet packets, leading to TCP
+checksum errors. This corruption occurs from the position
+(4K - (address & 0x7F)) to 4K. The u_ether function's allocation of
+skb_buff reserves 64B, meaning all RX addresses resemble 0xXXXX0040.
+
+Force trb_burst_size to 16 can fix this problem.
+
+Cc: stable@vger.kernel.org
+Fixes: 7733f6c32e36 ("usb: cdns3: Add Cadence USB3 DRD Driver")
+Signed-off-by: Frank Li <Frank.Li@nxp.com>
+Link: https://lore.kernel.org/r/20230518154946.3666662-1-Frank.Li@nxp.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/cdns3/gadget.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
+index 24dab7006b823..210c1d6150825 100644
+--- a/drivers/usb/cdns3/gadget.c
++++ b/drivers/usb/cdns3/gadget.c
+@@ -2098,6 +2098,19 @@ int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable)
+       else
+               priv_ep->trb_burst_size = 16;
+ 
++      /*
++       * In versions preceding DEV_VER_V2, for example, iMX8QM, there exit the bugs
++       * in the DMA. These bugs occur when the trb_burst_size exceeds 16 and the
++       * address is not aligned to 128 Bytes (which is a product of the 64-bit AXI
++       * and AXI maximum burst length of 16 or 0xF+1, dma_axi_ctrl0[3:0]). This
++       * results in data corruption when it crosses the 4K border. The corruption
++       * specifically occurs from the position (4K - (address & 0x7F)) to 4K.
++       *
++       * So force trb_burst_size to 16 at such platform.
++       */
++      if (priv_dev->dev_ver < DEV_VER_V2)
++              priv_ep->trb_burst_size = 16;
++
+       mult = min_t(u8, mult, EP_CFG_MULT_MAX);
+       buffering = min_t(u8, buffering, EP_CFG_BUFFERING_MAX);
+       maxburst = min_t(u8, maxburst, EP_CFG_MAXBURST_MAX);
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-cdnsp-device-side-header-file-for-cdnsp-driver.patch b/queue-5.10/usb-cdnsp-device-side-header-file-for-cdnsp-driver.patch
new file mode 100644 (file)
index 0000000..eb2bcaf
--- /dev/null
+++ b/queue-5.10/usb-cdnsp-device-side-header-file-for-cdnsp-driver.patch
@@ -0,0 +1,1499 @@
+From 8531c1c73a458b0c5007d12256fb10da96243983 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 7 Dec 2020 11:32:23 +0100
+Subject: usb: cdnsp: Device side header file for CDNSP driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Pawel Laszczak <pawell@cadence.com>
+
+[ Upstream commit e93e58d2740282d32c0278fab283eb0ae158bb59 ]
+
+Patch defines macros, registers and structures used by
+Device side driver.
+
+Because the size of main patch is very big, I’ve decided to create
+separate patch for cdnsp-gadget.h. It should simplify reviewing the code.
+
+Signed-off-by: Pawel Laszczak <pawell@cadence.com>
+Signed-off-by: Peter Chen <peter.chen@nxp.com>
+Stable-dep-of: dbe678f6192f ("usb: cdns3: fix NCM gadget RX speed 20x slow than expection at iMX8QM")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/cdns3/cdnsp-gadget.h | 1463 ++++++++++++++++++++++++++++++
+ 1 file changed, 1463 insertions(+)
+ create mode 100644 drivers/usb/cdns3/cdnsp-gadget.h
+
+diff --git a/drivers/usb/cdns3/cdnsp-gadget.h b/drivers/usb/cdns3/cdnsp-gadget.h
+new file mode 100644
+index 0000000000000..93da1dcdad600
+--- /dev/null
++++ b/drivers/usb/cdns3/cdnsp-gadget.h
+@@ -0,0 +1,1463 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Cadence CDNSP DRD Driver.
++ *
++ * Copyright (C) 2020 Cadence.
++ *
++ * Author: Pawel Laszczak <pawell@cadence.com>
++ *
++ * Code based on Linux XHCI driver.
++ * Origin: Copyright (C) 2008 Intel Corp.
++ */
++#ifndef __LINUX_CDNSP_GADGET_H
++#define __LINUX_CDNSP_GADGET_H
++
++#include <linux/io-64-nonatomic-lo-hi.h>
++#include <linux/usb/gadget.h>
++#include <linux/irq.h>
++
++/* Max number slots - only 1 is allowed. */
++#define CDNSP_DEV_MAX_SLOTS   1
++
++#define CDNSP_EP0_SETUP_SIZE  512
++
++/* One control and 15 for in and 15 for out endpoints. */
++#define CDNSP_ENDPOINTS_NUM   31
++
++/* Best Effort Service Latency. */
++#define CDNSP_DEFAULT_BESL    0
++
++/* Device Controller command default timeout value in us */
++#define CDNSP_CMD_TIMEOUT     (15 * 1000)
++
++/* Up to 16 ms to halt an device controller */
++#define CDNSP_MAX_HALT_USEC   (16 * 1000)
++
++#define CDNSP_CTX_SIZE        2112
++
++/*
++ * Controller register interface.
++ */
++
++/**
++ * struct cdnsp_cap_regs - CDNSP Registers.
++ * @hc_capbase:       Length of the capabilities register and controller
++ *              version number
++ * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
++ * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
++ * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
++ * @hcc_params: HCCPARAMS - Capability Parameters
++ * @db_off: DBOFF - Doorbell array offset
++ * @run_regs_off: RTSOFF - Runtime register space offset
++ * @hcc_params2: HCCPARAMS2 Capability Parameters 2,
++ */
++struct cdnsp_cap_regs {
++      __le32 hc_capbase;
++      __le32 hcs_params1;
++      __le32 hcs_params2;
++      __le32 hcs_params3;
++      __le32 hcc_params;
++      __le32 db_off;
++      __le32 run_regs_off;
++      __le32 hcc_params2;
++      /* Reserved up to (CAPLENGTH - 0x1C) */
++};
++
++/* hc_capbase bitmasks. */
++/* bits 7:0 - how long is the Capabilities register. */
++#define HC_LENGTH(p)          (((p) >> 00) & GENMASK(7, 0))
++/* bits 31:16 */
++#define HC_VERSION(p)         (((p) >> 16) & GENMASK(15, 1))
++
++/* HCSPARAMS1 - hcs_params1 - bitmasks */
++/* bits 0:7, Max Device Endpoints */
++#define HCS_ENDPOINTS_MASK    GENMASK(7, 0)
++#define HCS_ENDPOINTS(p)      (((p) & HCS_ENDPOINTS_MASK) >> 0)
++
++/* HCCPARAMS offset from PCI base address */
++#define HCC_PARAMS_OFFSET     0x10
++
++/* HCCPARAMS - hcc_params - bitmasks */
++/* 1: device controller can use 64-bit address pointers. */
++#define HCC_64BIT_ADDR(p)     ((p) & BIT(0))
++/* 1: device controller uses 64-byte Device Context structures. */
++#define HCC_64BYTE_CONTEXT(p) ((p) & BIT(2))
++/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */
++#define HCC_MAX_PSA(p)                ((((p) >> 12) & 0xf) + 1)
++/* Extended Capabilities pointer from PCI base. */
++#define HCC_EXT_CAPS(p)               (((p) & GENMASK(31, 16)) >> 16)
++
++#define CTX_SIZE(_hcc)                (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
++
++/* db_off bitmask - bits 0:1 reserved. */
++#define DBOFF_MASK    GENMASK(31, 2)
++
++/* run_regs_off bitmask - bits 0:4 reserved. */
++#define RTSOFF_MASK   GENMASK(31, 5)
++
++/**
++ * struct cdnsp_op_regs - Device Controller Operational Registers.
++ * @command: USBCMD - Controller command register.
++ * @status: USBSTS - Controller status register.
++ * @page_size: This indicates the page size that the device controller supports.
++ *             If bit n is set, the controller supports a page size of 2^(n+12),
++ *             up to a 128MB page size. 4K is the minimum page size.
++ * @dnctrl: DNCTRL - Device notification control register.
++ * @cmd_ring: CRP - 64-bit Command Ring Pointer.
++ * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer.
++ * @config_reg: CONFIG - Configure Register
++ * @port_reg_base: PORTSCn - base address for Port Status and Control
++ *                 Each port has a Port Status and Control register,
++ *                 followed by a Port Power Management Status and Control
++ *                 register, a Port Link Info register, and a reserved
++ *                 register.
++ */
++struct cdnsp_op_regs {
++      __le32 command;
++      __le32 status;
++      __le32 page_size;
++      __le32 reserved1;
++      __le32 reserved2;
++      __le32 dnctrl;
++      __le64 cmd_ring;
++      /* rsvd: offset 0x20-2F. */
++      __le32 reserved3[4];
++      __le64 dcbaa_ptr;
++      __le32 config_reg;
++      /* rsvd: offset 0x3C-3FF. */
++      __le32 reserved4[241];
++      /* port 1 registers, which serve as a base address for other ports. */
++      __le32 port_reg_base;
++};
++
++/* Number of registers per port. */
++#define NUM_PORT_REGS 4
++
++/**
++ * struct cdnsp_port_regs - Port Registers.
++ * @portsc: PORTSC - Port Status and Control Register.
++ * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register.
++ * @portli: PORTLI - Port Link Info register.
++ */
++struct cdnsp_port_regs {
++      __le32 portsc;
++      __le32 portpmsc;
++      __le32 portli;
++      __le32 reserved;
++};
++
++/*
++ * These bits are Read Only (RO) and should be saved and written to the
++ * registers: 0 (connect status) and  10:13 (port speed).
++ * These bits are also sticky - meaning they're in the AUX well and they aren't
++ * changed by a hot and warm.
++ */
++#define CDNSP_PORT_RO (PORT_CONNECT | DEV_SPEED_MASK)
++
++/*
++ * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
++ * bits 5:8 (link state), 25:26  ("wake on" enable state)
++ */
++#define CDNSP_PORT_RWS        (PORT_PLS_MASK | PORT_WKCONN_E | PORT_WKDISC_E)
++
++/*
++ * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
++ * bits 1 (port enable/disable), 17  ( connect changed),
++ * 21 (port reset changed) , 22 (Port Link State Change),
++ */
++#define CDNSP_PORT_RW1CS (PORT_PED | PORT_CSC | PORT_RC | PORT_PLC)
++
++/* USBCMD - USB command - bitmasks. */
++/* Run/Stop, controller execution - do not write unless controller is halted.*/
++#define CMD_R_S               BIT(0)
++/*
++ * Reset device controller - resets internal controller state machine and all
++ * registers (except PCI config regs).
++ */
++#define CMD_RESET     BIT(1)
++/* Event Interrupt Enable - a '1' allows interrupts from the controller. */
++#define CMD_INTE      BIT(2)
++/*
++ * Device System Error Interrupt Enable - get out-of-band signal for
++ * controller errors.
++ */
++#define CMD_DSEIE     BIT(3)
++/* device controller save/restore state. */
++#define CMD_CSS               BIT(8)
++#define CMD_CRS               BIT(9)
++/*
++ * Enable Wrap Event - '1' means device controller generates an event
++ * when MFINDEX wraps.
++ */
++#define CMD_EWE               BIT(10)
++/* 1: device enabled */
++#define CMD_DEVEN     BIT(17)
++/* bits 18:31 are reserved (and should be preserved on writes). */
++
++/* Command register values to disable interrupts. */
++#define CDNSP_IRQS    (CMD_INTE | CMD_DSEIE | CMD_EWE)
++
++/* USBSTS - USB status - bitmasks */
++/* controller not running - set to 1 when run/stop bit is cleared. */
++#define STS_HALT      BIT(0)
++/*
++ * serious error, e.g. PCI parity error. The controller will clear
++ * the run/stop bit.
++ */
++#define STS_FATAL     BIT(2)
++/* event interrupt - clear this prior to clearing any IP flags in IR set.*/
++#define STS_EINT      BIT(3)
++/* port change detect */
++#define STS_PCD               BIT(4)
++/* save state status - '1' means device controller is saving state. */
++#define STS_SSS               BIT(8)
++/* restore state status - '1' means controllers is restoring state. */
++#define STS_RSS               BIT(9)
++/* 1: save or restore error */
++#define STS_SRE               BIT(10)
++/* 1: device Not Ready to accept doorbell or op reg writes after reset. */
++#define STS_CNR               BIT(11)
++/* 1: internal Device Controller Error.*/
++#define STS_HCE               BIT(12)
++
++/* CRCR - Command Ring Control Register - cmd_ring bitmasks. */
++/* bit 0 is the command ring cycle state. */
++#define CMD_RING_CS           BIT(0)
++/* stop ring immediately - abort the currently executing command. */
++#define CMD_RING_ABORT                BIT(2)
++/*
++ * Command Ring Busy.
++ * Set when Doorbell register is written with DB for command and cleared when
++ * the controller reached end of CR.
++ */
++#define CMD_RING_BUSY(p)      ((p) & BIT(4))
++/* 1: command ring is running */
++#define CMD_RING_RUNNING      BIT(3)
++/* Command Ring pointer - bit mask for the lower 32 bits. */
++#define CMD_RING_RSVD_BITS    GENMASK(5, 0)
++
++/* CONFIG - Configure Register - config_reg bitmasks. */
++/* bits 0:7 - maximum number of device slots enabled. */
++#define MAX_DEVS              GENMASK(7, 0)
++/* bit 8: U3 Entry Enabled, assert PLC when controller enters U3. */
++#define CONFIG_U3E            BIT(8)
++
++/* PORTSC - Port Status and Control Register - port_reg_base bitmasks */
++/* 1: device connected. */
++#define PORT_CONNECT          BIT(0)
++/* 1: port enabled. */
++#define PORT_PED              BIT(1)
++/* 1: port reset signaling asserted. */
++#define PORT_RESET            BIT(4)
++/*
++ * Port Link State - bits 5:8
++ * A read gives the current link PM state of the port,
++ * a write with Link State Write Strobe sets the link state.
++ */
++#define PORT_PLS_MASK         GENMASK(8, 5)
++#define XDEV_U0                       (0x0 << 5)
++#define XDEV_U1                       (0x1 << 5)
++#define XDEV_U2                       (0x2 << 5)
++#define XDEV_U3                       (0x3 << 5)
++#define XDEV_DISABLED         (0x4 << 5)
++#define XDEV_RXDETECT         (0x5 << 5)
++#define XDEV_INACTIVE         (0x6 << 5)
++#define XDEV_POLLING          (0x7 << 5)
++#define XDEV_RECOVERY         (0x8 << 5)
++#define XDEV_HOT_RESET                (0x9 << 5)
++#define XDEV_COMP_MODE                (0xa << 5)
++#define XDEV_TEST_MODE                (0xb << 5)
++#define XDEV_RESUME           (0xf << 5)
++/* 1: port has power. */
++#define PORT_POWER            BIT(9)
++/*
++ * bits 10:13 indicate device speed:
++ * 0 - undefined speed - port hasn't be initialized by a reset yet
++ * 1 - full speed
++ * 2 - Reserved (Low Speed not supported
++ * 3 - high speed
++ * 4 - super speed
++ * 5 - super speed
++ * 6-15 reserved
++ */
++#define DEV_SPEED_MASK                GENMASK(13, 10)
++#define XDEV_FS                       (0x1 << 10)
++#define XDEV_HS                       (0x3 << 10)
++#define XDEV_SS                       (0x4 << 10)
++#define XDEV_SSP              (0x5 << 10)
++#define DEV_UNDEFSPEED(p)     (((p) & DEV_SPEED_MASK) == (0x0 << 10))
++#define DEV_FULLSPEED(p)      (((p) & DEV_SPEED_MASK) == XDEV_FS)
++#define DEV_HIGHSPEED(p)      (((p) & DEV_SPEED_MASK) == XDEV_HS)
++#define DEV_SUPERSPEED(p)     (((p) & DEV_SPEED_MASK) == XDEV_SS)
++#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
++#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
++#define DEV_PORT_SPEED(p)     (((p) >> 10) & 0x0f)
++/* Port Link State Write Strobe - set this when changing link state */
++#define PORT_LINK_STROBE      BIT(16)
++/* 1: connect status change */
++#define PORT_CSC              BIT(17)
++/* 1: warm reset for a USB 3.0 device is done. */
++#define PORT_WRC              BIT(19)
++/* 1: reset change - 1 to 0 transition of PORT_RESET */
++#define PORT_RC                       BIT(21)
++/*
++ * port link status change - set on some port link state transitions:
++ * Transition                 Reason
++ * ----------------------------------------------------------------------------
++ * - U3 to Resume             Wakeup signaling from a device
++ * - Resume to Recovery to U0 USB 3.0 device resume
++ * - Resume to U0             USB 2.0 device resume
++ * - U3 to Recovery to U0     Software resume of USB 3.0 device complete
++ * - U3 to U0                 Software resume of USB 2.0 device complete
++ * - U2 to U0                 L1 resume of USB 2.1 device complete
++ * - U0 to U0                 L1 entry rejection by USB 2.1 device
++ * - U0 to disabled           L1 entry error with USB 2.1 device
++ * - Any state to inactive    Error on USB 3.0 port
++ */
++#define PORT_PLC              BIT(22)
++/* Port configure error change - port failed to configure its link partner. */
++#define PORT_CEC              BIT(23)
++/* Wake on connect (enable). */
++#define PORT_WKCONN_E         BIT(25)
++/* Wake on disconnect (enable). */
++#define PORT_WKDISC_E         BIT(26)
++/* Indicates if Warm Reset is being received. */
++#define PORT_WR                       BIT(31)
++
++#define PORT_CHANGE_BITS (PORT_CSC | PORT_WRC | PORT_RC | PORT_PLC | PORT_CEC)
++
++/* PORTPMSCUSB3 - Port Power Management Status and Control - bitmasks. */
++/*  Enables U1 entry. */
++#define PORT_U1_TIMEOUT_MASK  GENMASK(7, 0)
++#define PORT_U1_TIMEOUT(p)    ((p) & PORT_U1_TIMEOUT_MASK)
++/* Enables U2 entry .*/
++#define PORT_U2_TIMEOUT_MASK  GENMASK(14, 8)
++#define PORT_U2_TIMEOUT(p)    (((p) << 8) & PORT_U2_TIMEOUT_MASK)
++
++/* PORTPMSCUSB2 - Port Power Management Status and Control - bitmasks. */
++#define PORT_L1S_MASK         GENMASK(2, 0)
++#define PORT_L1S(p)           ((p) & PORT_L1S_MASK)
++#define PORT_L1S_ACK          PORT_L1S(1)
++#define PORT_L1S_NYET         PORT_L1S(2)
++#define PORT_L1S_STALL                PORT_L1S(3)
++#define PORT_L1S_TIMEOUT      PORT_L1S(4)
++/* Remote Wake Enable. */
++#define PORT_RWE              BIT(3)
++/* Best Effort Service Latency (BESL). */
++#define PORT_BESL(p)          (((p) << 4) & GENMASK(7, 4))
++/* Hardware LPM Enable (HLE). */
++#define PORT_HLE              BIT(16)
++/* Received Best Effort Service Latency (BESL). */
++#define PORT_RRBESL(p)                (((p) & GENMASK(20, 17)) >> 17)
++/* Port Test Control. */
++#define PORT_TEST_MODE_MASK   GENMASK(31, 28)
++#define PORT_TEST_MODE(p)     (((p) << 28) & PORT_TEST_MODE_MASK)
++
++/**
++ * struct cdnsp_intr_reg - Interrupt Register Set.
++ * @irq_pending: IMAN - Interrupt Management Register. Used to enable
++ *               interrupts and check for pending interrupts.
++ * @irq_control: IMOD - Interrupt Moderation Register.
++ *               Used to throttle interrupts.
++ * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
++ * @erst_base: ERST base address.
++ * @erst_dequeue: Event ring dequeue pointer.
++ *
++ * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
++ * Ring Segment Table (ERST) associated with it. The event ring is comprised of
++ * multiple segments of the same size. The controller places events on the ring
++ * and "updates the Cycle bit in the TRBs to indicate to software the current
++ * position of the Enqueue Pointer." The driver processes those events and
++ * updates the dequeue pointer.
++ */
++struct cdnsp_intr_reg {
++      __le32 irq_pending;
++      __le32 irq_control;
++      __le32 erst_size;
++      __le32 rsvd;
++      __le64 erst_base;
++      __le64 erst_dequeue;
++};
++
++/* IMAN - Interrupt Management Register - irq_pending bitmasks l. */
++#define IMAN_IE                       BIT(1)
++#define IMAN_IP                       BIT(0)
++/* bits 2:31 need to be preserved */
++#define IMAN_IE_SET(p)                (((p) & IMAN_IE) | 0x2)
++#define IMAN_IE_CLEAR(p)      (((p) & IMAN_IE) & ~(0x2))
++
++/* IMOD - Interrupter Moderation Register - irq_control bitmasks. */
++/*
++ * Minimum interval between interrupts (in 250ns intervals). The interval
++ * between interrupts will be longer if there are no events on the event ring.
++ * Default is 4000 (1 ms).
++ */
++#define IMOD_INTERVAL_MASK    GENMASK(15, 0)
++/* Counter used to count down the time to the next interrupt - HW use only */
++#define IMOD_COUNTER_MASK     GENMASK(31, 16)
++#define IMOD_DEFAULT_INTERVAL 0
++
++/* erst_size bitmasks. */
++/* Preserve bits 16:31 of erst_size. */
++#define ERST_SIZE_MASK                GENMASK(31, 16)
++
++/* erst_dequeue bitmasks. */
++/*
++ * Dequeue ERST Segment Index (DESI) - Segment number (or alias)
++ * where the current dequeue pointer lies. This is an optional HW hint.
++ */
++#define ERST_DESI_MASK                GENMASK(2, 0)
++/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced. */
++#define ERST_EHB              BIT(3)
++#define ERST_PTR_MASK         GENMASK(3, 0)
++
++/**
++ * struct cdnsp_run_regs
++ * @microframe_index: MFINDEX - current microframe number.
++ * @ir_set: Array of Interrupter registers.
++ *
++ * Device Controller Runtime Registers:
++ * "Software should read and write these registers using only Dword (32 bit)
++ * or larger accesses"
++ */
++struct cdnsp_run_regs {
++      __le32 microframe_index;
++      __le32 rsvd[7];
++      struct cdnsp_intr_reg ir_set[128];
++};
++
++/**
++ * USB2.0 Port Peripheral Configuration Registers.
++ * @ext_cap: Header register for Extended Capability.
++ * @port_reg1: Timer Configuration Register.
++ * @port_reg2: Timer Configuration Register.
++ * @port_reg3: Timer Configuration Register.
++ * @port_reg4: Timer Configuration Register.
++ * @port_reg5: Timer Configuration Register.
++ * @port_reg6: Chicken bits for USB20PPP.
++ */
++struct cdnsp_20port_cap {
++      __le32 ext_cap;
++      __le32 port_reg1;
++      __le32 port_reg2;
++      __le32 port_reg3;
++      __le32 port_reg4;
++      __le32 port_reg5;
++      __le32 port_reg6;
++};
++
++/* Extended capability register fields */
++#define EXT_CAPS_ID(p)                        (((p) >> 0) & GENMASK(7, 0))
++#define EXT_CAPS_NEXT(p)              (((p) >> 8) & GENMASK(7, 0))
++/* Extended capability IDs - ID 0 reserved */
++#define EXT_CAPS_PROTOCOL             2
++
++/* USB 2.0 Port Peripheral Configuration Extended Capability */
++#define EXT_CAP_CFG_DEV_20PORT_CAP_ID 0xC1
++/*
++ * Setting this bit to '1' enables automatic wakeup from L1 state on transfer
++ * TRB prepared when USBSSP operates in USB2.0 mode.
++ */
++#define PORT_REG6_L1_L0_HW_EN         BIT(1)
++/*
++ * Setting this bit to '1' forces Full Speed when USBSSP operates in USB2.0
++ * mode (disables High Speed).
++ */
++#define PORT_REG6_FORCE_FS            BIT(0)
++
++/**
++ * USB3.x Port Peripheral Configuration Registers.
++ * @ext_cap: Header register for Extended Capability.
++ * @mode_addr: Miscellaneous 3xPORT operation mode configuration register.
++ * @mode_2: 3x Port Control Register 2.
++ */
++struct cdnsp_3xport_cap {
++      __le32 ext_cap;
++      __le32 mode_addr;
++      __le32 reserved[52];
++      __le32 mode_2;
++};
++
++/* Extended Capability Header for 3XPort Configuration Registers. */
++#define D_XEC_CFG_3XPORT_CAP          0xC0
++#define CFG_3XPORT_SSP_SUPPORT                BIT(31)
++#define CFG_3XPORT_U1_PIPE_CLK_GATE_EN        BIT(0)
++
++/* Revision Extended Capability ID */
++#define RTL_REV_CAP                   0xC4
++#define RTL_REV_CAP_RX_BUFF_CMD_SIZE  BITMASK(31, 24)
++#define RTL_REV_CAP_RX_BUFF_SIZE      BITMASK(15, 0)
++#define RTL_REV_CAP_TX_BUFF_CMD_SIZE  BITMASK(31, 24)
++#define RTL_REV_CAP_TX_BUFF_SIZE      BITMASK(15, 0)
++
++#define CDNSP_VER_1 0x00000000
++#define CDNSP_VER_2 0x10000000
++
++#define CDNSP_IF_EP_EXIST(pdev, ep_num, dir) ((pdev)->rev_cap.ep_supported & \
++                        (BIT(ep_num) << ((dir) ? 0 : 16)))
++
++/**
++ * struct cdnsp_rev_cap - controller capabilities .
++ * @ext_cap: Header for RTL Revision Extended Capability.
++ * @rtl_revision: RTL revision.
++ * @rx_buff_size: Rx buffer sizes.
++ * @tx_buff_size: Tx buffer sizes.
++ * @ep_supported: Supported endpoints.
++ * @ctrl_revision: Controller revision ID.
++ */
++struct cdnsp_rev_cap {
++      __le32 ext_cap;
++      __le32 rtl_revision;
++      __le32 rx_buff_size;
++      __le32 tx_buff_size;
++      __le32 ep_supported;
++      __le32 ctrl_revision;
++};
++
++/* USB2.0 Port Peripheral Configuration Registers. */
++#define D_XEC_PRE_REGS_CAP            0xC8
++#define REG_CHICKEN_BITS_2_OFFSET     0x48
++#define CHICKEN_XDMA_2_TP_CACHE_DIS   BIT(28)
++
++/* XBUF Extended Capability ID. */
++#define XBUF_CAP_ID                   0xCB
++#define XBUF_RX_TAG_MASK_0_OFFSET     0x1C
++#define XBUF_RX_TAG_MASK_1_OFFSET     0x24
++#define XBUF_TX_CMD_OFFSET            0x2C
++
++/**
++ * struct cdnsp_doorbell_array.
++ * @cmd_db: Command ring doorbell register.
++ * @ep_db: Endpoint ring doorbell register.
++ *         Bits 0 - 7: Endpoint target.
++ *         Bits 8 - 15: RsvdZ.
++ *         Bits 16 - 31: Stream ID.
++ */
++struct cdnsp_doorbell_array {
++      __le32 cmd_db;
++      __le32 ep_db;
++};
++
++#define DB_VALUE(ep, stream)          ((((ep) + 1) & 0xff) | ((stream) << 16))
++#define DB_VALUE_EP0_OUT(ep, stream)  ((ep) & 0xff)
++#define DB_VALUE_CMD                  0x00000000
++
++/**
++ * struct cdnsp_container_ctx.
++ * @type: Type of context. Used to calculated offsets to contained contexts.
++ * @size: Size of the context data.
++ * @ctx_size: context data structure size - 64 or 32 bits.
++ * @dma: dma address of the bytes.
++ * @bytes: The raw context data given to HW.
++ *
++ * Represents either a Device or Input context. Holds a pointer to the raw
++ * memory used for the context (bytes) and dma address of it (dma).
++ */
++struct cdnsp_container_ctx {
++      unsigned int type;
++#define CDNSP_CTX_TYPE_DEVICE 0x1
++#define CDNSP_CTX_TYPE_INPUT  0x2
++      int size;
++      int ctx_size;
++      dma_addr_t dma;
++      u8 *bytes;
++};
++
++/**
++ * struct cdnsp_slot_ctx
++ * @dev_info: Device speed, and last valid endpoint.
++ * @dev_port: Device port number that is needed to access the USB device.
++ * @int_target: Interrupter target number.
++ * @dev_state: Slot state and device address.
++ *
++ * Slot Context - This assumes the controller uses 32-byte context
++ * structures. If the controller uses 64-byte contexts, there is an additional
++ * 32 bytes reserved at the end of the slot context for controller internal use.
++ */
++struct cdnsp_slot_ctx {
++      __le32 dev_info;
++      __le32 dev_port;
++      __le32 int_target;
++      __le32 dev_state;
++      /* offset 0x10 to 0x1f reserved for controller internal use. */
++      __le32 reserved[4];
++};
++
++/* Bits 20:23 in the Slot Context are the speed for the device. */
++#define SLOT_SPEED_FS         (XDEV_FS << 10)
++#define SLOT_SPEED_HS         (XDEV_HS << 10)
++#define SLOT_SPEED_SS         (XDEV_SS << 10)
++#define SLOT_SPEED_SSP                (XDEV_SSP << 10)
++
++/* dev_info bitmasks. */
++/* Device speed - values defined by PORTSC Device Speed field - 20:23. */
++#define DEV_SPEED             GENMASK(23, 20)
++#define GET_DEV_SPEED(n)      (((n) & DEV_SPEED) >> 20)
++/* Index of the last valid endpoint context in this device context - 27:31. */
++#define LAST_CTX_MASK         GENMASK(31, 27)
++#define LAST_CTX(p)           ((p) << 27)
++#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
++#define SLOT_FLAG             BIT(0)
++#define EP0_FLAG              BIT(1)
++
++/* dev_port bitmasks */
++/* Device port number that is needed to access the USB device. */
++#define DEV_PORT(p)           (((p) & 0xff) << 16)
++
++/* dev_state bitmasks */
++/* USB device address - assigned by the controller. */
++#define DEV_ADDR_MASK         GENMASK(7, 0)
++/* Slot state */
++#define SLOT_STATE            GENMASK(31, 27)
++#define GET_SLOT_STATE(p)     (((p) & SLOT_STATE) >> 27)
++
++#define SLOT_STATE_DISABLED   0
++#define SLOT_STATE_ENABLED    SLOT_STATE_DISABLED
++#define SLOT_STATE_DEFAULT    1
++#define SLOT_STATE_ADDRESSED  2
++#define SLOT_STATE_CONFIGURED 3
++
++/**
++ * struct cdnsp_ep_ctx.
++ * @ep_info: Endpoint state, streams, mult, and interval information.
++ * @ep_info2: Information on endpoint type, max packet size, max burst size,
++ *            error count, and whether the controller will force an event for
++ *            all transactions.
++ * @deq: 64-bit ring dequeue pointer address. If the endpoint only
++ *       defines one stream, this points to the endpoint transfer ring.
++ *       Otherwise, it points to a stream context array, which has a
++ *       ring pointer for each flow.
++ * @tx_info: Average TRB lengths for the endpoint ring and
++ *         max payload within an Endpoint Service Interval Time (ESIT).
++ *
++ * Endpoint Context - This assumes the controller uses 32-byte context
++ * structures. If the controller uses 64-byte contexts, there is an additional
++ * 32 bytes reserved at the end of the endpoint context for controller internal
++ * use.
++ */
++struct cdnsp_ep_ctx {
++      __le32 ep_info;
++      __le32 ep_info2;
++      __le64 deq;
++      __le32 tx_info;
++      /* offset 0x14 - 0x1f reserved for controller internal use. */
++      __le32 reserved[3];
++};
++
++/* ep_info bitmasks. */
++/*
++ * Endpoint State - bits 0:2:
++ * 0 - disabled
++ * 1 - running
++ * 2 - halted due to halt condition
++ * 3 - stopped
++ * 4 - TRB error
++ * 5-7 - reserved
++ */
++#define EP_STATE_MASK         GENMASK(3, 0)
++#define EP_STATE_DISABLED     0
++#define EP_STATE_RUNNING      1
++#define EP_STATE_HALTED               2
++#define EP_STATE_STOPPED      3
++#define EP_STATE_ERROR                4
++#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
++
++/* Mult - Max number of burst within an interval, in EP companion desc. */
++#define EP_MULT(p)                    (((p) << 8) & GENMASK(9, 8))
++#define CTX_TO_EP_MULT(p)             (((p) & GENMASK(9, 8)) >> 8)
++/* bits 10:14 are Max Primary Streams. */
++/* bit 15 is Linear Stream Array. */
++/* Interval - period between requests to an endpoint - 125u increments. */
++#define EP_INTERVAL(p)                        (((p) << 16) & GENMASK(23, 16))
++#define EP_INTERVAL_TO_UFRAMES(p)     (1 << (((p) & GENMASK(23, 16)) >> 16))
++#define CTX_TO_EP_INTERVAL(p)         (((p) & GENMASK(23, 16)) >> 16)
++#define EP_MAXPSTREAMS_MASK           GENMASK(14, 10)
++#define EP_MAXPSTREAMS(p)             (((p) << 10) & EP_MAXPSTREAMS_MASK)
++#define CTX_TO_EP_MAXPSTREAMS(p)      (((p) & EP_MAXPSTREAMS_MASK) >> 10)
++/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
++#define EP_HAS_LSA                    BIT(15)
++
++/* ep_info2 bitmasks */
++#define ERROR_COUNT(p)                (((p) & 0x3) << 1)
++#define CTX_TO_EP_TYPE(p)     (((p) >> 3) & 0x7)
++#define EP_TYPE(p)            ((p) << 3)
++#define ISOC_OUT_EP           1
++#define BULK_OUT_EP           2
++#define INT_OUT_EP            3
++#define CTRL_EP                       4
++#define ISOC_IN_EP            5
++#define BULK_IN_EP            6
++#define INT_IN_EP             7
++/* bit 6 reserved. */
++/* bit 7 is Device Initiate Disable - for disabling stream selection. */
++#define MAX_BURST(p)          (((p) << 8) & GENMASK(15, 8))
++#define CTX_TO_MAX_BURST(p)   (((p) & GENMASK(15, 8)) >> 8)
++#define MAX_PACKET(p)         (((p) << 16) & GENMASK(31, 16))
++#define MAX_PACKET_MASK               GENMASK(31, 16)
++#define MAX_PACKET_DECODED(p) (((p) & GENMASK(31, 16)) >> 16)
++
++/* tx_info bitmasks. */
++#define EP_AVG_TRB_LENGTH(p)          ((p) & GENMASK(15, 0))
++#define EP_MAX_ESIT_PAYLOAD_LO(p)     (((p) << 16) & GENMASK(31, 16))
++#define EP_MAX_ESIT_PAYLOAD_HI(p)     ((((p) & GENMASK(23, 16)) >> 16) << 24)
++#define CTX_TO_MAX_ESIT_PAYLOAD_LO(p) (((p) & GENMASK(31, 16)) >> 16)
++#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) & GENMASK(31, 24)) >> 24)
++
++/* deq bitmasks. */
++#define EP_CTX_CYCLE_MASK             BIT(0)
++#define CTX_DEQ_MASK                  (~0xfL)
++
++/**
++ * struct cdnsp_input_control_context
++ * Input control context;
++ *
++ * @drop_context: Set the bit of the endpoint context you want to disable.
++ * @add_context: Set the bit of the endpoint context you want to enable.
++ */
++struct cdnsp_input_control_ctx {
++      __le32 drop_flags;
++      __le32 add_flags;
++      __le32 rsvd2[6];
++};
++
++/**
++ * Represents everything that is needed to issue a command on the command ring.
++ *
++ * @in_ctx: Pointer to input context structure.
++ * @status: Command Completion Code for last command.
++ * @command_trb: Pointer to command TRB.
++ */
++struct cdnsp_command {
++      /* Input context for changing device state. */
++      struct cdnsp_container_ctx *in_ctx;
++      u32 status;
++      union cdnsp_trb *command_trb;
++};
++
++/**
++ * Stream context structure.
++ *
++ * @stream_ring: 64-bit stream ring address, cycle state, and stream type.
++ * @reserved: offset 0x14 - 0x1f reserved for controller internal use.
++ */
++struct cdnsp_stream_ctx {
++      __le64 stream_ring;
++      __le32 reserved[2];
++};
++
++/* Stream Context Types - bits 3:1 of stream ctx deq ptr. */
++#define SCT_FOR_CTX(p)                (((p) << 1) & GENMASK(3, 1))
++/* Secondary stream array type, dequeue pointer is to a transfer ring. */
++#define SCT_SEC_TR            0
++/* Primary stream array type, dequeue pointer is to a transfer ring. */
++#define SCT_PRI_TR            1
++
++/**
++ *  struct cdnsp_stream_info: Representing everything that is needed to
++ *                            supports stream capable endpoints.
++ *  @stream_rings: Array of pointers containing Transfer rings for all
++ *                 supported streams.
++ *  @num_streams: Number of streams, including stream 0.
++ *  @stream_ctx_array: The stream context array may be bigger than the number
++ *                     of streams the driver asked for.
++ *  @num_stream_ctxs: Number of streams.
++ *  @ctx_array_dma: Dma address of Context Stream Array.
++ *  @trb_address_map: For mapping physical TRB addresses to segments in
++ *                    stream rings.
++ *  @td_count: Number of TDs associated with endpoint.
++ *  @first_prime_det: First PRIME packet detected.
++ *  @drbls_count: Number of allowed doorbells.
++ */
++struct cdnsp_stream_info {
++      struct cdnsp_ring **stream_rings;
++      unsigned int num_streams;
++      struct cdnsp_stream_ctx *stream_ctx_array;
++      unsigned int num_stream_ctxs;
++      dma_addr_t ctx_array_dma;
++      struct radix_tree_root trb_address_map;
++      int td_count;
++      u8 first_prime_det;
++#define STREAM_DRBL_FIFO_DEPTH 2
++      u8 drbls_count;
++};
++
++#define STREAM_LOG_STREAMS 4
++#define STREAM_NUM_STREAMS BIT(STREAM_LOG_STREAMS)
++
++#if STREAM_LOG_STREAMS > 16 && STREAM_LOG_STREAMS < 1
++#error "Not suupported stream value"
++#endif
++
++/**
++ * struct cdnsp_ep - extended device side representation of USB endpoint.
++ * @endpoint: usb endpoint
++ * @pending_req_list: List of requests queuing on transfer ring.
++ * @pdev: Device associated with this endpoint.
++ * @number: Endpoint number (1 - 15).
++ * idx: The device context index (DCI).
++ * interval: Interval between packets used for ISOC endpoint.
++ * @name: A human readable name e.g. ep1out.
++ * @direction: Endpoint direction.
++ * @buffering: Number of on-chip buffers related to endpoint.
++ * @buffering_period; Number of on-chip buffers related to periodic endpoint.
++ * @in_ctx: Pointer to input endpoint context structure.
++ * @out_ctx: Pointer to output endpoint context structure.
++ * @ring: Pointer to transfer ring.
++ * @stream_info: Hold stream information.
++ * @ep_state: Current state of endpoint.
++ * @skip: Sometimes the controller can not process isochronous endpoint ring
++ *        quickly enough, and it will miss some isoc tds on the ring and
++ *        generate Missed Service Error Event.
++ *        Set skip flag when receive a Missed Service Error Event and
++ *        process the missed tds on the endpoint ring.
++ */
++struct cdnsp_ep {
++      struct usb_ep endpoint;
++      struct list_head pending_list;
++      struct cdnsp_device *pdev;
++      u8 number;
++      u8 idx;
++      u32 interval;
++      char name[20];
++      u8 direction;
++      u8 buffering;
++      u8 buffering_period;
++      struct cdnsp_ep_ctx *in_ctx;
++      struct cdnsp_ep_ctx *out_ctx;
++      struct cdnsp_ring *ring;
++      struct cdnsp_stream_info stream_info;
++      unsigned int ep_state;
++#define EP_ENABLED            BIT(0)
++#define EP_DIS_IN_RROGRESS    BIT(1)
++#define EP_HALTED             BIT(2)
++#define EP_STOPPED            BIT(3)
++#define EP_WEDGE              BIT(4)
++#define EP0_HALTED_STATUS     BIT(5)
++#define EP_HAS_STREAMS                BIT(6)
++
++      bool skip;
++};
++
++/**
++ * struct cdnsp_device_context_array
++ * @dev_context_ptr: Array of 64-bit DMA addresses for device contexts.
++ * @dma: DMA address for device contexts structure.
++ */
++struct cdnsp_device_context_array {
++      __le64 dev_context_ptrs[CDNSP_DEV_MAX_SLOTS + 1];
++      dma_addr_t dma;
++};
++
++/**
++ * struct cdnsp_transfer_event.
++ * @buffer: 64-bit buffer address, or immediate data.
++ * @transfer_len: Data length transferred.
++ * @flags: Field is interpreted differently based on the type of TRB.
++ */
++struct cdnsp_transfer_event {
++      __le64 buffer;
++      __le32 transfer_len;
++      __le32 flags;
++};
++
++/* Invalidate event after disabling endpoint. */
++#define TRB_EVENT_INVALIDATE 8
++
++/* Transfer event TRB length bit mask. */
++/* bits 0:23 */
++#define EVENT_TRB_LEN(p)                      ((p) & GENMASK(23, 0))
++/* Completion Code - only applicable for some types of TRBs */
++#define COMP_CODE_MASK                                (0xff << 24)
++#define GET_COMP_CODE(p)                      (((p) & COMP_CODE_MASK) >> 24)
++#define COMP_INVALID                          0
++#define COMP_SUCCESS                          1
++#define COMP_DATA_BUFFER_ERROR                        2
++#define COMP_BABBLE_DETECTED_ERROR            3
++#define COMP_TRB_ERROR                                5
++#define COMP_RESOURCE_ERROR                   7
++#define COMP_NO_SLOTS_AVAILABLE_ERROR         9
++#define COMP_INVALID_STREAM_TYPE_ERROR                10
++#define COMP_SLOT_NOT_ENABLED_ERROR           11
++#define COMP_ENDPOINT_NOT_ENABLED_ERROR               12
++#define COMP_SHORT_PACKET                     13
++#define COMP_RING_UNDERRUN                    14
++#define COMP_RING_OVERRUN                     15
++#define COMP_VF_EVENT_RING_FULL_ERROR         16
++#define COMP_PARAMETER_ERROR                  17
++#define COMP_CONTEXT_STATE_ERROR              19
++#define COMP_EVENT_RING_FULL_ERROR            21
++#define COMP_INCOMPATIBLE_DEVICE_ERROR                22
++#define COMP_MISSED_SERVICE_ERROR             23
++#define COMP_COMMAND_RING_STOPPED             24
++#define COMP_COMMAND_ABORTED                  25
++#define COMP_STOPPED                          26
++#define COMP_STOPPED_LENGTH_INVALID           27
++#define COMP_STOPPED_SHORT_PACKET             28
++#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
++#define COMP_ISOCH_BUFFER_OVERRUN             31
++#define COMP_EVENT_LOST_ERROR                 32
++#define COMP_UNDEFINED_ERROR                  33
++#define COMP_INVALID_STREAM_ID_ERROR          34
++
++/*Transfer Event NRDY bit fields */
++#define TRB_TO_DEV_STREAM(p)                  ((p) & GENMASK(16, 0))
++#define TRB_TO_HOST_STREAM(p)                 ((p) & GENMASK(16, 0))
++#define STREAM_PRIME_ACK                      0xFFFE
++#define STREAM_REJECTED                               0xFFFF
++
++/** Transfer Event bit fields **/
++#define TRB_TO_EP_ID(p)                               (((p) & GENMASK(20, 16)) >> 16)
++
++/**
++ * struct cdnsp_link_trb
++ * @segment_ptr: 64-bit segment pointer.
++ * @intr_target: Interrupter target.
++ * @control: Flags.
++ */
++struct cdnsp_link_trb {
++      __le64 segment_ptr;
++      __le32 intr_target;
++      __le32 control;
++};
++
++/* control bitfields */
++#define LINK_TOGGLE   BIT(1)
++
++/**
++ * struct cdnsp_event_cmd - Command completion event TRB.
++ * cmd_trb: Pointer to command TRB, or the value passed by the event data trb
++ * status: Command completion parameters and error code.
++ * flags: Flags.
++ */
++struct cdnsp_event_cmd {
++      __le64 cmd_trb;
++      __le32 status;
++      __le32 flags;
++};
++
++/* flags bitmasks */
++
++/* Address device - disable SetAddress. */
++#define TRB_BSR               BIT(9)
++
++/* Configure Endpoint - Deconfigure. */
++#define TRB_DC                BIT(9)
++
++/* Force Header */
++#define TRB_FH_TO_PACKET_TYPE(p)      ((p) & GENMASK(4, 0))
++#define TRB_FH_TR_PACKET              0x4
++#define TRB_FH_TO_DEVICE_ADDRESS(p)   (((p) << 25) & GENMASK(31, 25))
++#define TRB_FH_TR_PACKET_DEV_NOT      0x6
++#define TRB_FH_TO_NOT_TYPE(p)         (((p) << 4) & GENMASK(7, 4))
++#define TRB_FH_TR_PACKET_FUNCTION_WAKE        0x1
++#define TRB_FH_TO_INTERFACE(p)                (((p) << 8) & GENMASK(15, 8))
++
++enum cdnsp_setup_dev {
++      SETUP_CONTEXT_ONLY,
++      SETUP_CONTEXT_ADDRESS,
++};
++
++/* bits 24:31 are the slot ID. */
++#define TRB_TO_SLOT_ID(p)             (((p) & GENMASK(31, 24)) >> 24)
++#define SLOT_ID_FOR_TRB(p)            (((p) << 24) & GENMASK(31, 24))
++
++/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB. */
++#define TRB_TO_EP_INDEX(p)            (((p) >> 16) & 0x1f)
++
++#define EP_ID_FOR_TRB(p)              ((((p) + 1) << 16) & GENMASK(20, 16))
++
++#define SUSPEND_PORT_FOR_TRB(p)               (((p) & 1) << 23)
++#define TRB_TO_SUSPEND_PORT(p)                (((p) >> 23) & 0x1)
++#define LAST_EP_INDEX                 30
++
++/* Set TR Dequeue Pointer command TRB fields. */
++#define TRB_TO_STREAM_ID(p)           ((((p) & GENMASK(31, 16)) >> 16))
++#define STREAM_ID_FOR_TRB(p)          ((((p)) << 16) & GENMASK(31, 16))
++#define SCT_FOR_TRB(p)                        (((p) << 1) & 0x7)
++
++/* Link TRB specific fields. */
++#define TRB_TC                                BIT(1)
++
++/* Port Status Change Event TRB fields. */
++/* Port ID - bits 31:24. */
++#define GET_PORT_ID(p)                        (((p) & GENMASK(31, 24)) >> 24)
++#define SET_PORT_ID(p)                        (((p) << 24) & GENMASK(31, 24))
++#define EVENT_DATA                    BIT(2)
++
++/* Normal TRB fields. */
++/* transfer_len bitmasks - bits 0:16. */
++#define TRB_LEN(p)                    ((p) & GENMASK(16, 0))
++/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31). */
++#define TRB_TD_SIZE(p)                        (min((p), (u32)31) << 17)
++#define GET_TD_SIZE(p)                        (((p) & GENMASK(21, 17)) >> 17)
++/*
++ * Controller uses the TD_SIZE field for TBC if Extended TBC
++ * is enabled (ETE).
++ */
++#define TRB_TD_SIZE_TBC(p)            (min((p), (u32)31) << 17)
++/* Interrupter Target - which MSI-X vector to target the completion event at. */
++#define TRB_INTR_TARGET(p)            (((p) << 22) & GENMASK(31, 22))
++#define GET_INTR_TARGET(p)            (((p) & GENMASK(31, 22)) >> 22)
++/*
++ * Total burst count field, Rsvdz on controller with Extended TBC
++ * enabled (ETE).
++ */
++#define TRB_TBC(p)                    (((p) & 0x3) << 7)
++#define TRB_TLBPC(p)                  (((p) & 0xf) << 16)
++
++/* Cycle bit - indicates TRB ownership by driver or driver.*/
++#define TRB_CYCLE                     BIT(0)
++/*
++ * Force next event data TRB to be evaluated before task switch.
++ * Used to pass OS data back after a TD completes.
++ */
++#define TRB_ENT                               BIT(1)
++/* Interrupt on short packet. */
++#define TRB_ISP                               BIT(2)
++/* Set PCIe no snoop attribute. */
++#define TRB_NO_SNOOP                  BIT(3)
++/* Chain multiple TRBs into a TD. */
++#define TRB_CHAIN                     BIT(4)
++/* Interrupt on completion. */
++#define TRB_IOC                               BIT(5)
++/* The buffer pointer contains immediate data. */
++#define TRB_IDT                               BIT(6)
++/* 0 - NRDY during data stage, 1 - NRDY during status stage (only control). */
++#define TRB_STAT                      BIT(7)
++/* Block Event Interrupt. */
++#define TRB_BEI                               BIT(9)
++
++/* Control transfer TRB specific fields. */
++#define TRB_DIR_IN                    BIT(16)
++
++/* TRB bit mask in Data Stage TRB */
++#define TRB_SETUPID_BITMASK           GENMASK(9, 8)
++#define TRB_SETUPID(p)                        ((p) << 8)
++#define TRB_SETUPID_TO_TYPE(p)                (((p) & TRB_SETUPID_BITMASK) >> 8)
++
++#define TRB_SETUP_SPEEDID_USB3                0x1
++#define TRB_SETUP_SPEEDID_USB2                0x0
++#define TRB_SETUP_SPEEDID(p)          ((p) & (1 << 7))
++
++#define TRB_SETUPSTAT_ACK             0x1
++#define TRB_SETUPSTAT_STALL           0x0
++#define TRB_SETUPSTAT(p)              ((p) << 6)
++
++/* Isochronous TRB specific fields */
++#define TRB_SIA                               BIT(31)
++#define TRB_FRAME_ID(p)                       (((p) << 20) & GENMASK(30, 20))
++
++struct cdnsp_generic_trb {
++      __le32 field[4];
++};
++
++union cdnsp_trb {
++      struct cdnsp_link_trb link;
++      struct cdnsp_transfer_event trans_event;
++      struct cdnsp_event_cmd event_cmd;
++      struct cdnsp_generic_trb generic;
++};
++
++/* TRB bit mask. */
++#define TRB_TYPE_BITMASK      GENMASK(15, 10)
++#define TRB_TYPE(p)           ((p) << 10)
++#define TRB_FIELD_TO_TYPE(p)  (((p) & TRB_TYPE_BITMASK) >> 10)
++
++/* TRB type IDs. */
++/* bulk, interrupt, isoc scatter/gather, and control data stage. */
++#define TRB_NORMAL            1
++/* Setup Stage for control transfers. */
++#define TRB_SETUP             2
++/* Data Stage for control transfers. */
++#define TRB_DATA              3
++/* Status Stage for control transfers. */
++#define TRB_STATUS            4
++/* ISOC transfers. */
++#define TRB_ISOC              5
++/* TRB for linking ring segments. */
++#define TRB_LINK              6
++#define TRB_EVENT_DATA                7
++/* Transfer Ring No-op (not for the command ring). */
++#define TRB_TR_NOOP           8
++
++/* Command TRBs */
++/* Enable Slot Command. */
++#define TRB_ENABLE_SLOT               9
++/* Disable Slot Command. */
++#define TRB_DISABLE_SLOT      10
++/* Address Device Command. */
++#define TRB_ADDR_DEV          11
++/* Configure Endpoint Command. */
++#define TRB_CONFIG_EP         12
++/* Evaluate Context Command. */
++#define TRB_EVAL_CONTEXT      13
++/* Reset Endpoint Command. */
++#define TRB_RESET_EP          14
++/* Stop Transfer Ring Command. */
++#define TRB_STOP_RING         15
++/* Set Transfer Ring Dequeue Pointer Command. */
++#define TRB_SET_DEQ           16
++/* Reset Device Command. */
++#define TRB_RESET_DEV         17
++/* Force Event Command (opt). */
++#define TRB_FORCE_EVENT               18
++/* Force Header Command - generate a transaction or link management packet. */
++#define TRB_FORCE_HEADER      22
++/* No-op Command - not for transfer rings. */
++#define TRB_CMD_NOOP          23
++/* TRB IDs 24-31 reserved. */
++
++/* Event TRBS. */
++/* Transfer Event. */
++#define TRB_TRANSFER          32
++/* Command Completion Event. */
++#define TRB_COMPLETION                33
++/* Port Status Change Event. */
++#define TRB_PORT_STATUS               34
++/* Device Controller Event. */
++#define TRB_HC_EVENT          37
++/* MFINDEX Wrap Event - microframe counter wrapped. */
++#define TRB_MFINDEX_WRAP      39
++/* TRB IDs 40-47 reserved. */
++/* Endpoint Not Ready Event. */
++#define TRB_ENDPOINT_NRDY     48
++/* TRB IDs 49-53 reserved. */
++/* Halt Endpoint Command. */
++#define TRB_HALT_ENDPOINT     54
++/* Doorbell Overflow Event. */
++#define TRB_DRB_OVERFLOW      57
++/* Flush Endpoint Command. */
++#define TRB_FLUSH_ENDPOINT    58
++
++#define TRB_TYPE_LINK(x)      (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
++#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
++                                      cpu_to_le32(TRB_TYPE(TRB_LINK)))
++#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
++                                      cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
++
++/*
++ * TRBS_PER_SEGMENT must be a multiple of 4.
++ * The command ring is 64-byte aligned, so it must also be greater than 16.
++ */
++#define TRBS_PER_SEGMENT              256
++#define TRBS_PER_EVENT_SEGMENT                256
++#define TRBS_PER_EV_DEQ_UPDATE                100
++#define TRB_SEGMENT_SIZE              (TRBS_PER_SEGMENT * 16)
++#define TRB_SEGMENT_SHIFT             (ilog2(TRB_SEGMENT_SIZE))
++/* TRB buffer pointers can't cross 64KB boundaries. */
++#define TRB_MAX_BUFF_SHIFT            16
++#define TRB_MAX_BUFF_SIZE             BIT(TRB_MAX_BUFF_SHIFT)
++/* How much data is left before the 64KB boundary? */
++#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
++                                      ((addr) & (TRB_MAX_BUFF_SIZE - 1)))
++
++/**
++ * struct cdnsp_segment - segment related data.
++ * @trbs: Array of Transfer Request Blocks.
++ * @next: Pointer to the next segment.
++ * @dma: DMA address of current segment.
++ * @bounce_dma: Bounce  buffer DMA address .
++ * @bounce_buf: Bounce buffer virtual address.
++ * bounce_offs: Bounce buffer offset.
++ * bounce_len: Bounce buffer length.
++ */
++struct cdnsp_segment {
++      union cdnsp_trb *trbs;
++      struct cdnsp_segment *next;
++      dma_addr_t dma;
++      /* Max packet sized bounce buffer for td-fragmant alignment */
++      dma_addr_t bounce_dma;
++      void *bounce_buf;
++      unsigned int bounce_offs;
++      unsigned int bounce_len;
++};
++
++/**
++ * struct cdnsp_td - Transfer Descriptor object.
++ * @td_list: Used for binding TD with ep_ring->td_list.
++ * @preq: Request associated with this TD
++ * @start_seg: Segment containing the first_trb in TD.
++ * @first_trb: First TRB for this TD.
++ * @last_trb: Last TRB related with TD.
++ * @bounce_seg: Bounce segment for this TD.
++ * @request_length_set: actual_length of the request has already been set.
++ * @drbl - TD has been added to HW scheduler - only for stream capable
++ *         endpoints.
++ */
++struct cdnsp_td {
++      struct list_head td_list;
++      struct cdnsp_request *preq;
++      struct cdnsp_segment *start_seg;
++      union cdnsp_trb *first_trb;
++      union cdnsp_trb *last_trb;
++      struct cdnsp_segment *bounce_seg;
++      bool request_length_set;
++      bool drbl;
++};
++
++/**
++ * struct cdnsp_dequeue_state - New dequeue pointer for Transfer Ring.
++ * @new_deq_seg: New dequeue segment.
++ * @new_deq_ptr: New dequeue pointer.
++ * @new_cycle_state: New cycle state.
++ * @stream_id: stream id for which new dequeue pointer has been selected.
++ */
++struct cdnsp_dequeue_state {
++      struct cdnsp_segment *new_deq_seg;
++      union cdnsp_trb *new_deq_ptr;
++      int new_cycle_state;
++      unsigned int stream_id;
++};
++
++enum cdnsp_ring_type {
++      TYPE_CTRL = 0,
++      TYPE_ISOC,
++      TYPE_BULK,
++      TYPE_INTR,
++      TYPE_STREAM,
++      TYPE_COMMAND,
++      TYPE_EVENT,
++};
++
++/**
++ * struct cdnsp_ring - information describing transfer, command or event ring.
++ * @first_seg: First segment on transfer ring.
++ * @last_seg: Last segment on transfer ring.
++ * @enqueue: SW enqueue pointer address.
++ * @enq_seg: SW enqueue segment address.
++ * @dequeue: SW dequeue pointer address.
++ * @deq_seg: SW dequeue segment address.
++ * @td_list: transfer descriptor list associated with this ring.
++ * @cycle_state: Current cycle bit. Write the cycle state into the TRB cycle
++ *               field to give ownership of the TRB to the device controller
++ *               (if we are the producer) or to check if we own the TRB
++ *               (if we are the consumer).
++ * @stream_id: Stream id
++ * @stream_active: Stream is active - PRIME packet has been detected.
++ * @stream_rejected: This ring has been rejected by host.
++ * @num_tds: Number of TDs associated with ring.
++ * @num_segs: Number of segments.
++ * @num_trbs_free: Number of free TRBs on the ring.
++ * @bounce_buf_len: Length of bounce buffer.
++ * @type: Ring type - event, transfer, or command ring.
++ * @last_td_was_short - TD is short TD.
++ * @trb_address_map: For mapping physical TRB addresses to segments in
++ *                   stream rings.
++ */
++struct cdnsp_ring {
++      struct cdnsp_segment *first_seg;
++      struct cdnsp_segment *last_seg;
++      union cdnsp_trb  *enqueue;
++      struct cdnsp_segment *enq_seg;
++      union cdnsp_trb  *dequeue;
++      struct cdnsp_segment *deq_seg;
++      struct list_head td_list;
++      u32 cycle_state;
++      unsigned int stream_id;
++      unsigned int stream_active;
++      unsigned int stream_rejected;
++      int num_tds;
++      unsigned int num_segs;
++      unsigned int num_trbs_free;
++      unsigned int bounce_buf_len;
++      enum cdnsp_ring_type type;
++      bool last_td_was_short;
++      struct radix_tree_root *trb_address_map;
++};
++
++/**
++ * struct cdnsp_erst_entry - even ring segment table entry object.
++ * @seg_addr: 64-bit event ring segment address.
++ * seg_size: Number of TRBs in segment.;
++ */
++struct cdnsp_erst_entry {
++      __le64 seg_addr;
++      __le32 seg_size;
++      /* Set to zero */
++      __le32 rsvd;
++};
++
++/**
++ * struct cdnsp_erst - even ring segment table for event ring.
++ * @entries: Array of event ring segments
++ * @num_entries: Number of segments in entries array.
++ * @erst_dma_addr: DMA address for entries array.
++ */
++struct cdnsp_erst {
++      struct cdnsp_erst_entry *entries;
++      unsigned int num_entries;
++      dma_addr_t erst_dma_addr;
++};
++
++/**
++ * struct cdnsp_request - extended device side representation of usb_request
++ *                        object .
++ * @td: Transfer descriptor associated with this request.
++ * @request: Generic usb_request object describing single I/O request.
++ * @list: Used to adding request to endpoint pending_list.
++ * @pep: Extended representation of usb_ep object
++ * @epnum: Endpoint number associated with usb request.
++ * @direction: Endpoint direction for usb request.
++ */
++struct cdnsp_request {
++      struct  cdnsp_td td;
++      struct usb_request request;
++      struct list_head list;
++      struct cdnsp_ep  *pep;
++      u8 epnum;
++      unsigned direction:1;
++};
++
++#define       ERST_NUM_SEGS   1
++
++/* Stages used during enumeration process.*/
++enum cdnsp_ep0_stage {
++      CDNSP_SETUP_STAGE,
++      CDNSP_DATA_STAGE,
++      CDNSP_STATUS_STAGE,
++};
++
++/**
++ * struct cdnsp_port - holds information about detected ports.
++ * @port_num: Port number.
++ * @exist: Indicate if port exist.
++ * maj_rev: Major revision.
++ * min_rev: Minor revision.
++ */
++struct cdnsp_port {
++      struct cdnsp_port_regs __iomem *regs;
++      u8 port_num;
++      u8 exist;
++      u8 maj_rev;
++      u8 min_rev;
++};
++
++#define CDNSP_EXT_PORT_MAJOR(x)               (((x) >> 24) & 0xff)
++#define CDNSP_EXT_PORT_MINOR(x)               (((x) >> 16) & 0xff)
++#define CDNSP_EXT_PORT_OFF(x)         ((x) & 0xff)
++#define CDNSP_EXT_PORT_COUNT(x)               (((x) >> 8) & 0xff)
++
++/**
++ * struct cdnsp_device - represent USB device.
++ * @dev: Pointer to device structure associated whit this controller.
++ * @gadget: Device side representation of the peripheral controller.
++ * @gadget_driver: Pointer to the gadget driver.
++ * @irq: IRQ line number used by device side.
++ * @regs:IO device memory.
++ * @cap_regs: Capability registers.
++ * @op_regs: Operational registers.
++ * @run_regs: Runtime registers.
++ * @dba: Device base address register.
++ * @ir_set: Current interrupter register set.
++ * @port20_regs: Port 2.0 Peripheral Configuration Registers.
++ * @port3x_regs: USB3.x Port Peripheral Configuration Registers.
++ * @hcs_params1: Cached register copies of read-only HCSPARAMS1
++ * @hcc_params: Cached register copies of read-only HCCPARAMS1
++ * @rev_cap: Controller capability.
++ * @setup: Temporary buffer for setup packet.
++ * @ep0_preq: Internal allocated request used during enumeration.
++ * @ep0_stage: ep0 stage during enumeration process.
++ * @three_stage_setup: Three state or two state setup.
++ * @ep0_expect_in: Data IN expected for control transfer.
++ * @setup_id: Setup identifier.
++ * @setup_speed - Speed detected for current SETUP packet.
++ * @setup_buf: Buffer for SETUP packet.
++ * @device_address: Current device address.
++ * @may_wakeup: remote wakeup enabled/disabled.
++ * @lock: Lock used in interrupt thread context.
++ * @hci_version: device controller version.
++ * @dcbaa: Device context base address array.
++ * @cmd_ring: Command ring.
++ * @cmd: Represent all what is needed to issue command on Command Ring.
++ * @event_ring: Event ring.
++ * @erst: Event Ring Segment table
++ * @slot_id: Current Slot ID. Should be 0 or 1.
++ * @out_ctx: Output context.
++ * @in_ctx: Input context.
++ * @eps: array of endpoints object associated with device.
++ * @usb2_hw_lpm_capable: hardware lpm is enabled;
++ * @u1_allowed: Allow device transition to U1 state.
++ * @u2_allowed: Allow device transition to U2 state
++ * @device_pool: DMA pool for allocating input and output context.
++ * @segment_pool: DMA pool for allocating new segments.
++ * @cdnsp_state: Current state of controller.
++ * @link_state: Current link state.
++ * @usb2_port - Port USB 2.0.
++ * @usb3_port - Port USB 3.0.
++ * @active_port - Current selected Port.
++ * @test_mode: selected Test Mode.
++ */
++struct cdnsp_device {
++      struct device *dev;
++      struct usb_gadget gadget;
++      struct usb_gadget_driver *gadget_driver;
++      unsigned int irq;
++      void __iomem *regs;
++
++      /* Registers map */
++      struct cdnsp_cap_regs __iomem *cap_regs;
++      struct cdnsp_op_regs __iomem *op_regs;
++      struct cdnsp_run_regs __iomem *run_regs;
++      struct cdnsp_doorbell_array __iomem *dba;
++      struct  cdnsp_intr_reg __iomem *ir_set;
++      struct cdnsp_20port_cap __iomem *port20_regs;
++      struct cdnsp_3xport_cap __iomem *port3x_regs;
++
++      /* Cached register copies of read-only CDNSP data */
++      __u32 hcs_params1;
++      __u32 hcs_params3;
++      __u32 hcc_params;
++      struct cdnsp_rev_cap rev_cap;
++      /* Lock used in interrupt thread context. */
++      spinlock_t lock;
++      struct usb_ctrlrequest setup;
++      struct cdnsp_request ep0_preq;
++      enum cdnsp_ep0_stage ep0_stage;
++      u8 three_stage_setup;
++      u8 ep0_expect_in;
++      u8 setup_id;
++      u8 setup_speed;
++      void *setup_buf;
++      u8 device_address;
++      int may_wakeup;
++      u16 hci_version;
++
++      /* data structures */
++      struct cdnsp_device_context_array *dcbaa;
++      struct cdnsp_ring *cmd_ring;
++      struct cdnsp_command cmd;
++      struct cdnsp_ring *event_ring;
++      struct cdnsp_erst erst;
++      int slot_id;
++
++      /*
++       * Commands to the hardware are passed an "input context" that
++       * tells the hardware what to change in its data structures.
++       * The hardware will return changes in an "output context" that
++       * software must allocate for the hardware. .
++       */
++      struct cdnsp_container_ctx out_ctx;
++      struct cdnsp_container_ctx in_ctx;
++      struct cdnsp_ep eps[CDNSP_ENDPOINTS_NUM];
++      u8 usb2_hw_lpm_capable:1;
++      u8 u1_allowed:1;
++      u8 u2_allowed:1;
++
++      /* DMA pools */
++      struct dma_pool *device_pool;
++      struct dma_pool *segment_pool;
++
++#define CDNSP_STATE_HALTED            BIT(1)
++#define CDNSP_STATE_DYING             BIT(2)
++#define CDNSP_STATE_DISCONNECT_PENDING        BIT(3)
++#define CDNSP_WAKEUP_PENDING          BIT(4)
++      unsigned int cdnsp_state;
++      unsigned int link_state;
++
++      struct cdnsp_port usb2_port;
++      struct cdnsp_port usb3_port;
++      struct cdnsp_port *active_port;
++      u16 test_mode;
++};
++
++#endif /* __LINUX_CDNSP_GADGET_H */
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch b/queue-5.10/usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch
new file mode 100644 (file)
index 0000000..7874d1a
--- /dev/null
+++ b/queue-5.10/usb-chipidea-imx-add-missing-usb-phy-dpdm-wakeup-set.patch
@@ -0,0 +1,41 @@
+From 0a5dbccb64b1e160f2a78a09c0140da7527d1eb6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 May 2023 16:19:07 +0800
+Subject: usb: chipidea: imx: add missing USB PHY DPDM wakeup setting
+
+From: Xu Yang <xu.yang_2@nxp.com>
+
+[ Upstream commit 53d061c19dc4cb68409df6dc11c40389c8c42a75 ]
+
+USB PHY DPDM wakeup bit is enabled by default, when USB wakeup
+is not required(/sys/.../wakeup is disabled), this bit should be
+disabled, otherwise we will have unexpected wakeup if do USB device
+connect/disconnect while system sleep.
+This bit can be enabled for both host and device mode.
+
+Signed-off-by: Li Jun <jun.li@nxp.com>
+Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
+Acked-by: Peter Chen <peter.chen@kernel.org>
+Message-ID: <20230517081907.3410465-3-xu.yang_2@nxp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/chipidea/usbmisc_imx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c
+index 425b29168b4d0..9b1d5c11dc340 100644
+--- a/drivers/usb/chipidea/usbmisc_imx.c
++++ b/drivers/usb/chipidea/usbmisc_imx.c
+@@ -135,7 +135,7 @@
+ #define TXVREFTUNE0_MASK              (0xf << 20)
+ 
+ #define MX6_USB_OTG_WAKEUP_BITS (MX6_BM_WAKEUP_ENABLE | MX6_BM_VBUS_WAKEUP | \
+-                               MX6_BM_ID_WAKEUP)
++                               MX6_BM_ID_WAKEUP | MX6SX_BM_DPDM_WAKEUP_EN)
+ 
+ struct usbmisc_ops {
+       /* It's called once when probe a usb device */
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch b/queue-5.10/usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch
new file mode 100644 (file)
index 0000000..3fe0ff7
--- /dev/null
+++ b/queue-5.10/usb-chipidea-imx-don-t-request-qos-for-imx8ulp.patch
@@ -0,0 +1,49 @@
+From 5e6f58a77c1cb95ad4814eb9cd4370aa8bc2a416 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 30 May 2023 18:40:07 +0800
+Subject: usb: chipidea: imx: don't request QoS for imx8ulp
+
+From: Xu Yang <xu.yang_2@nxp.com>
+
+[ Upstream commit 9a070e8e208995a9d638b538ed7abf28bd6ea6f0 ]
+
+Use dedicated imx8ulp usb compatible to remove QoS request
+since imx8ulp has no such limitation of imx7ulp: DMA will
+not work if system enters idle.
+
+Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
+Signed-off-by: Li Jun <jun.li@nxp.com>
+Acked-by: Peter Chen <peter.chen@kernel.org>
+Message-ID: <20230530104007.1294702-2-xu.yang_2@nxp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/chipidea/ci_hdrc_imx.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c
+index f798455942844..4d47fe89864d9 100644
+--- a/drivers/usb/chipidea/ci_hdrc_imx.c
++++ b/drivers/usb/chipidea/ci_hdrc_imx.c
+@@ -70,6 +70,10 @@ static const struct ci_hdrc_imx_platform_flag imx7ulp_usb_data = {
+               CI_HDRC_PMQOS,
+ };
+ 
++static const struct ci_hdrc_imx_platform_flag imx8ulp_usb_data = {
++      .flags = CI_HDRC_SUPPORTS_RUNTIME_PM,
++};
++
+ static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
+       { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data},
+       { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
+@@ -80,6 +84,7 @@ static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
+       { .compatible = "fsl,imx6ul-usb", .data = &imx6ul_usb_data},
+       { .compatible = "fsl,imx7d-usb", .data = &imx7d_usb_data},
+       { .compatible = "fsl,imx7ulp-usb", .data = &imx7ulp_usb_data},
++      { .compatible = "fsl,imx8ulp-usb", .data = &imx8ulp_usb_data},
+       { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, ci_hdrc_imx_dt_ids);
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-dwc3-qcom-fix-null-deref-on-suspend.patch b/queue-5.10/usb-dwc3-qcom-fix-null-deref-on-suspend.patch
new file mode 100644 (file)
index 0000000..a8879e9
--- /dev/null
+++ b/queue-5.10/usb-dwc3-qcom-fix-null-deref-on-suspend.patch
@@ -0,0 +1,68 @@
+From 160892370791d9524190f3218e3ee101aa97b34b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Jun 2023 12:05:39 +0200
+Subject: USB: dwc3: qcom: fix NULL-deref on suspend
+
+From: Johan Hovold <johan+linaro@kernel.org>
+
+[ Upstream commit d2d69354226de0b333d4405981f3d9c41ba8430a ]
+
+The Qualcomm dwc3 glue driver is currently accessing the driver data of
+the child core device during suspend and on wakeup interrupts. This is
+clearly a bad idea as the child may not have probed yet or could have
+been unbound from its driver.
+
+The first such layering violation was part of the initial version of the
+driver, but this was later made worse when the hack that accesses the
+driver data of the grand child xhci device to configure the wakeup
+interrupts was added.
+
+Fixing this properly is not that easily done, so add a sanity check to
+make sure that the child driver data is non-NULL before dereferencing it
+for now.
+
+Note that this relies on subtleties like the fact that driver core is
+making sure that the parent is not suspended while the child is probing.
+
+Reported-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/all/20230325165217.31069-4-manivannan.sadhasivam@linaro.org/
+Fixes: d9152161b4bf ("usb: dwc3: Add Qualcomm DWC3 glue layer driver")
+Fixes: 6895ea55c385 ("usb: dwc3: qcom: Configure wakeup interrupts during suspend")
+Cc: stable@vger.kernel.org     # 3.18: a872ab303d5d: "usb: dwc3: qcom: fix use-after-free on runtime-PM wakeup"
+Cc: Sandeep Maheswaram <quic_c_sanm@quicinc.com>
+Cc: Krishna Kurapati <quic_kriskura@quicinc.com>
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Message-ID: <20230607100540.31045-2-johan+linaro@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/dwc3-qcom.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
+index ec8c43231746e..3973f6c18857e 100644
+--- a/drivers/usb/dwc3/dwc3-qcom.c
++++ b/drivers/usb/dwc3/dwc3-qcom.c
+@@ -306,7 +306,16 @@ static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
+ /* Only usable in contexts where the role can not change. */
+ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
+ {
+-      struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
++      struct dwc3 *dwc;
++
++      /*
++       * FIXME: Fix this layering violation.
++       */
++      dwc = platform_get_drvdata(qcom->dwc3);
++
++      /* Core driver may not have probed yet. */
++      if (!dwc)
++              return false;
+ 
+       return dwc->xhci;
+ }
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch b/queue-5.10/usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch
new file mode 100644 (file)
index 0000000..14f27aa
--- /dev/null
+++ b/queue-5.10/usb-gadget-u_serial-avoid-spinlock-recursion-in-__gs.patch
@@ -0,0 +1,61 @@
+From ca5a1f67510fb72c0eec85d0dc62f9fea5896e98 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 9 May 2023 18:57:52 +0530
+Subject: usb: gadget: u_serial: Avoid spinlock recursion in __gs_console_push
+
+From: Prashanth K <quic_prashk@quicinc.com>
+
+[ Upstream commit e5990469943c711cb00bfde6338d2add6c6d0bfe ]
+
+When serial console over USB is enabled, gs_console_connect
+queues gs_console_work, where it acquires the spinlock and
+queues the usb request, and this request goes to gadget layer.
+Now consider a situation where gadget layer prints something
+to dmesg, this will eventually call gs_console_write() which
+requires cons->lock. And this causes spinlock recursion. Avoid
+this by excluding usb_ep_queue from the spinlock.
+
+ spin_lock_irqsave //needs cons->lock
+ gs_console_write
+       .
+       .
+ _printk
+ __warn_printk
+ dev_warn/pr_err
+       .
+       .
+ [USB Gadget Layer]
+       .
+       .
+ usb_ep_queue
+ gs_console_work
+ __gs_console_push // acquires cons->lock
+ process_one_work
+
+Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
+Link: https://lore.kernel.org/r/1683638872-6885-1-git-send-email-quic_prashk@quicinc.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/gadget/function/u_serial.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/usb/gadget/function/u_serial.c b/drivers/usb/gadget/function/u_serial.c
+index 3b5a6430e2418..a717b53847a8e 100644
+--- a/drivers/usb/gadget/function/u_serial.c
++++ b/drivers/usb/gadget/function/u_serial.c
+@@ -917,8 +917,11 @@ static void __gs_console_push(struct gs_console *cons)
+       }
+ 
+       req->length = size;
++
++      spin_unlock_irq(&cons->lock);
+       if (usb_ep_queue(ep, req, GFP_ATOMIC))
+               req->length = 0;
++      spin_lock_irq(&cons->lock);
+ }
+ 
+ static void gs_console_work(struct work_struct *work)
+-- 
+2.40.1
+

diff --git a/queue-5.10/usb-gadget-udc-core-introduce-check_config-to-verify.patch b/queue-5.10/usb-gadget-udc-core-introduce-check_config-to-verify.patch
new file mode 100644 (file)
index 0000000..69c1d40
--- /dev/null
+++ b/queue-5.10/usb-gadget-udc-core-introduce-check_config-to-verify.patch
@@ -0,0 +1,87 @@
+From b01be3f9face6ae43ff30675dd1eadeafc00a255 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 10 Jul 2021 02:13:10 -0700
+Subject: usb: gadget: udc: core: Introduce check_config to verify USB
+ configuration
+
+From: Wesley Cheng <wcheng@codeaurora.org>
+
+[ Upstream commit ce7d0008c2356626f69f37ef1afce8fbc83fe142 ]
+
+Some UDCs may have constraints on how many high bandwidth endpoints it can
+support in a certain configuration.  This API allows for the composite
+driver to pass down the total number of endpoints to the UDC so it can verify
+it has the required resources to support the configuration.
+
+Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
+Link: https://lore.kernel.org/r/1625908395-5498-2-git-send-email-wcheng@codeaurora.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Stable-dep-of: dbe678f6192f ("usb: cdns3: fix NCM gadget RX speed 20x slow than expection at iMX8QM")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/gadget/udc/core.c | 19 +++++++++++++++++++
+ include/linux/usb/gadget.h    |  4 ++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
+index 3a3b5a03dda75..14d9d1ee16fc4 100644
+--- a/drivers/usb/gadget/udc/core.c
++++ b/drivers/usb/gadget/udc/core.c
+@@ -1004,6 +1004,25 @@ int usb_gadget_ep_match_desc(struct usb_gadget *gadget,
+ }
+ EXPORT_SYMBOL_GPL(usb_gadget_ep_match_desc);
+ 
++/**
++ * usb_gadget_check_config - checks if the UDC can support the binded
++ *    configuration
++ * @gadget: controller to check the USB configuration
++ *
++ * Ensure that a UDC is able to support the requested resources by a
++ * configuration, and that there are no resource limitations, such as
++ * internal memory allocated to all requested endpoints.
++ *
++ * Returns zero on success, else a negative errno.
++ */
++int usb_gadget_check_config(struct usb_gadget *gadget)
++{
++      if (gadget->ops->check_config)
++              return gadget->ops->check_config(gadget);
++      return 0;
++}
++EXPORT_SYMBOL_GPL(usb_gadget_check_config);
++
+ /* ------------------------------------------------------------------------- */
+ 
+ static void usb_gadget_state_work(struct work_struct *work)
+diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
+index e7351d64f11fa..11df3d5b40c6b 100644
+--- a/include/linux/usb/gadget.h
++++ b/include/linux/usb/gadget.h
+@@ -326,6 +326,7 @@ struct usb_gadget_ops {
+       struct usb_ep *(*match_ep)(struct usb_gadget *,
+                       struct usb_endpoint_descriptor *,
+                       struct usb_ss_ep_comp_descriptor *);
++      int     (*check_config)(struct usb_gadget *gadget);
+ };
+ 
+ /**
+@@ -596,6 +597,7 @@ int usb_gadget_connect(struct usb_gadget *gadget);
+ int usb_gadget_disconnect(struct usb_gadget *gadget);
+ int usb_gadget_deactivate(struct usb_gadget *gadget);
+ int usb_gadget_activate(struct usb_gadget *gadget);
++int usb_gadget_check_config(struct usb_gadget *gadget);
+ #else
+ static inline int usb_gadget_frame_number(struct usb_gadget *gadget)
+ { return 0; }
+@@ -619,6 +621,8 @@ static inline int usb_gadget_deactivate(struct usb_gadget *gadget)
+ { return 0; }
+ static inline int usb_gadget_activate(struct usb_gadget *gadget)
+ { return 0; }
++static inline int usb_gadget_check_config(struct usb_gadget *gadget)
++{ return 0; }
+ #endif /* CONFIG_USB_GADGET */
+ 
+ /*-------------------------------------------------------------------------*/
+-- 
+2.40.1
+