media: cedrus: hevc: Fix offset adjustments

As it turns out, current padding size check works fine in theory but it
doesn't in practice. Most probable reason are caching issues.

Let's rework reading data from bitstream using Cedrus engine instead of
CPU. That way we avoid all cache issues and make sure that we're reading
same data as Cedrus.

Fixes: e7060d9a78c2 ("media: uapi: Change data_bit_offset definition")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
index 4952fc17f3e6d9f23f235e47a2b9ba44b9da563d..625f77a8c5bde59ea79284188203a9ac5f3e7a27 100644 (file)
--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
@@ -242,6 +242,18 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
        }
 }
 
+static u32 cedrus_h265_show_bits(struct cedrus_dev *dev, int num)
+{
+       cedrus_write(dev, VE_DEC_H265_TRIGGER,
+                    VE_DEC_H265_TRIGGER_SHOW_BITS |
+                    VE_DEC_H265_TRIGGER_TYPE_N_BITS(num));
+
+       cedrus_wait_for(dev, VE_DEC_H265_STATUS,
+                       VE_DEC_H265_STATUS_VLD_BUSY);
+
+       return cedrus_read(dev, VE_DEC_H265_BITS_READ);
+}
+
 static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
                                           struct cedrus_run *run)
 {
@@ -406,7 +418,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
        u32 num_entry_point_offsets;
        u32 output_pic_list_index;
        u32 pic_order_cnt[2];
-       u8 *padding;
+       u8 padding;
        int count;
        u32 reg;
 
@@ -520,21 +532,22 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
        if (slice_params->data_byte_offset == 0)
                return -EOPNOTSUPP;
 
-       padding = (u8 *)vb2_plane_vaddr(&run->src->vb2_buf, 0) +
-               slice_params->data_byte_offset - 1;
+       cedrus_h265_skip_bits(dev, (slice_params->data_byte_offset - 1) * 8);
+
+       padding = cedrus_h265_show_bits(dev, 8);
 
        /* at least one bit must be set in that byte */
-       if (*padding == 0)
+       if (padding == 0)
                return -EINVAL;
 
        for (count = 0; count < 8; count++)
-               if (*padding & (1 << count))
+               if (padding & (1 << count))
                        break;
 
        /* Include the one bit. */
        count++;
 
-       cedrus_h265_skip_bits(dev, slice_params->data_byte_offset * 8 - count);
+       cedrus_h265_skip_bits(dev, 8 - count);
 
        /* Bitstream parameters. */
 

diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
index d81f7513ade0dc018ceac211546bfc21bf34119e..655c05b389cf51398884a0de7a4bf9d37e19deda 100644 (file)
--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
@@ -505,6 +505,8 @@
 #define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \
        SHIFT_AND_MASK_BITS(a, 7, 0)
 
+#define VE_DEC_H265_BITS_READ                  (VE_ENGINE_DEC_H265 + 0xdc)
+
 #define VE_DEC_H265_SRAM_OFFSET                        (VE_ENGINE_DEC_H265 + 0xe0)
 
 #define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0    0x00