arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline

This board can use a MIPI-DSI panel on the DSI0 connector: in
preparation for adding an overlay for the Radxa Display 8HD,
add a pipeline connecting VDOSYS0 components to DSI0.

This pipeline remains disabled by default, as it is expected
to be enabled only by a devicetree overlay that declares the
actual DSI panel node, completing the graph.

Link: https://lore.kernel.org/r/20250213112008.56394-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
index 41dc34837b02e7d2a02b720c899524bb35a23c0e..7184dc99296c7f5d749c7e6d378722677970b3b7 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
@@ -172,6 +172,32 @@
        cpu-supply = <&mt6315_6_vbuck1>;
 };
 
+&dither0_out {
+       remote-endpoint = <&dsi0_in>;
+};
+
+&dsi0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       dsi0_in: endpoint {
+                               remote-endpoint = <&dither0_out>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+                       dsi0_out: endpoint { };
+               };
+       };
+};
+
 &eth {
        phy-mode = "rgmii-rxid";
        phy-handle = <&rgmii_phy>;