drm/i915/ltphy: Fix SSC Enablement bit in PORT_CLOCK_CTL

According to Bspec we only need to write SSC Enable PLL A bit
and leave PLL B bit alone in PORT_CLOCK_CTL register.

Bspec: 74667, 74492
Fixes: 3383ba2479f7 ("drm/i915/ltphy: Enable SSC during port clock programming")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260701091503.1302226-3-suraj.kandpal@intel.com
(cherry picked from commit 8e27f752037e72ccee9c4a7c4a6202ecf3daf603)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 615ee980470ee217a423d8d4fd391cf43d9da3eb..34dbe450cc5b50cebb9324237b46d78e7cef51c3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1223,11 +1223,7 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
        else
                val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
 
-        /* DP2.0 10G and 20G rates enable MPLLA*/
-       if (port_clock == 1000000 || port_clock == 2000000)
-               val |= XELPDP_SSC_ENABLE_PLLA;
-       else
-               val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+       val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
 
        intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
                     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |