soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver

Remove legacy-of-mm-gpiochip.h header file. The above mentioned
file provides an OF API that's deprecated. There is no agnostic
alternatives to it and we have to open code the logic which was
hidden behind of_mm_gpiochip_add_data(). Note, most of the GPIO
drivers are using their own labeling schemas and resource retrieval
that only a few may gain of the code deduplication, so whenever
alternative is appear we can move drivers again to use that one.

As a side effect this change fixes a potential memory leak on
an error path, if of_mm_gpiochip_add_data() fails.

[Text copied from commit 34064c8267a6 ("powerpc/8xx: Drop
legacy-of-mm-gpiochip.h header")]

Suggested-by: Bartosz Golaszewski <brgl@bgdev.pl>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/e8a5d2c5b72233bd36da7fecc0a551ca54d39478.1758212309.git.christophe.leroy@csgroup.eu
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>

diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index fea3766eac0f311cb983757ad798aa299a18309e..5b689bd3ddf4dfa975a50ddc6e855200dff1c2f2 100644 (file)
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -232,7 +232,6 @@ config QE_GPIO
        bool "QE GPIO support"
        depends on QUICC_ENGINE
        select GPIOLIB
-       select OF_GPIO_MM_GPIOCHIP
        help
          Say Y here if you're going to use hardware that connects to the
          QE GPIOs.

diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index 04b44fc2bb5837a05d55ab012abbbbcf4fc716ef..c54154b404dfdf39eb2086f9990156e65800464a 100644 (file)
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -12,7 +12,6 @@
 #include <linux/spinlock.h>
 #include <linux/err.h>
 #include <linux/io.h>
-#include <linux/gpio/legacy-of-mm-gpiochip.h>
 #include <linux/gpio/consumer.h>
 #include <linux/gpio/driver.h>
 #include <linux/slab.h>
@@ -24,7 +23,8 @@
 #define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio)))
 
 struct qe_gpio_chip {
-       struct of_mm_gpio_chip mm_gc;
+       struct gpio_chip gc;
+       void __iomem *regs;
        spinlock_t lock;
 
        /* shadowed data register to clear/set bits safely */
@@ -34,11 +34,9 @@ struct qe_gpio_chip {
        struct qe_pio_regs saved_regs;
 };
 
-static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)
 {
-       struct qe_gpio_chip *qe_gc =
-               container_of(mm_gc, struct qe_gpio_chip, mm_gc);
-       struct qe_pio_regs __iomem *regs = mm_gc->regs;
+       struct qe_pio_regs __iomem *regs = qe_gc->regs;
 
        qe_gc->cpdata = ioread32be(&regs->cpdata);
        qe_gc->saved_regs.cpdata = qe_gc->cpdata;
@@ -51,8 +49,8 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
 
 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 {
-       struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-       struct qe_pio_regs __iomem *regs = mm_gc->regs;
+       struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
+       struct qe_pio_regs __iomem *regs = qe_gc->regs;
        u32 pin_mask = PIN_MASK(gpio);
 
        return !!(ioread32be(&regs->cpdata) & pin_mask);
@@ -60,9 +58,8 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 
 static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 {
-       struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
        struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
-       struct qe_pio_regs __iomem *regs = mm_gc->regs;
+       struct qe_pio_regs __iomem *regs = qe_gc->regs;
        unsigned long flags;
        u32 pin_mask = PIN_MASK(gpio);
 
@@ -83,9 +80,8 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 static int qe_gpio_set_multiple(struct gpio_chip *gc,
                                unsigned long *mask, unsigned long *bits)
 {
-       struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
        struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
-       struct qe_pio_regs __iomem *regs = mm_gc->regs;
+       struct qe_pio_regs __iomem *regs = qe_gc->regs;
        unsigned long flags;
        int i;
 
@@ -111,13 +107,12 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc,
 
 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 {
-       struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
        struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
        unsigned long flags;
 
        spin_lock_irqsave(&qe_gc->lock, flags);
 
-       __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
+       __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
 
        spin_unlock_irqrestore(&qe_gc->lock, flags);
 
@@ -126,7 +121,6 @@ static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 
 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 {
-       struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
        struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
        unsigned long flags;
 
@@ -134,7 +128,7 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 
        spin_lock_irqsave(&qe_gc->lock, flags);
 
-       __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
+       __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
 
        spin_unlock_irqrestore(&qe_gc->lock, flags);
 
@@ -240,7 +234,7 @@ EXPORT_SYMBOL(qe_pin_free);
 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
 {
        struct qe_gpio_chip *qe_gc = qe_pin->controller;
-       struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+       struct qe_pio_regs __iomem *regs = qe_gc->regs;
        struct qe_pio_regs *sregs = &qe_gc->saved_regs;
        int pin = qe_pin->num;
        u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
@@ -269,7 +263,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
 
        iowrite32be(qe_gc->cpdata, &regs->cpdata);
        qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
-
        spin_unlock_irqrestore(&qe_gc->lock, flags);
 }
 EXPORT_SYMBOL(qe_pin_set_dedicated);
@@ -284,7 +277,7 @@ EXPORT_SYMBOL(qe_pin_set_dedicated);
 void qe_pin_set_gpio(struct qe_pin *qe_pin)
 {
        struct qe_gpio_chip *qe_gc = qe_pin->controller;
-       struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+       struct qe_pio_regs __iomem *regs = qe_gc->regs;
        unsigned long flags;
 
        spin_lock_irqsave(&qe_gc->lock, flags);
@@ -301,7 +294,6 @@ static int qe_gpio_probe(struct platform_device *ofdev)
        struct device *dev = &ofdev->dev;
        struct device_node *np = dev->of_node;
        struct qe_gpio_chip *qe_gc;
-       struct of_mm_gpio_chip *mm_gc;
        struct gpio_chip *gc;
 
        qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
@@ -310,18 +302,29 @@ static int qe_gpio_probe(struct platform_device *ofdev)
 
        spin_lock_init(&qe_gc->lock);
 
-       mm_gc = &qe_gc->mm_gc;
-       gc = &mm_gc->gc;
+       gc = &qe_gc->gc;
 
-       mm_gc->save_regs = qe_gpio_save_regs;
+       gc->base = -1;
        gc->ngpio = QE_PIO_PINS;
        gc->direction_input = qe_gpio_dir_in;
        gc->direction_output = qe_gpio_dir_out;
        gc->get = qe_gpio_get;
        gc->set = qe_gpio_set;
        gc->set_multiple = qe_gpio_set_multiple;
+       gc->parent = dev;
+       gc->owner = THIS_MODULE;
+
+       gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
+       if (!gc->label)
+               return -ENOMEM;
+
+       qe_gc->regs = devm_of_iomap(dev, np, 0, NULL);
+       if (IS_ERR(qe_gc->regs))
+               return PTR_ERR(qe_gc->regs);
+
+       qe_gpio_save_regs(qe_gc);
 
-       return of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
+       return devm_gpiochip_add_data(dev, gc, qe_gc);
 }
 
 static const struct of_device_id qe_gpio_match[] = {