--- /dev/null
+From ca77fde8e62cecb2c0769052228d15b901367af8 Mon Sep 17 00:00:00 2001
+From: David Woodhouse <dwmw2@infradead.org>
+Date: Fri, 13 Feb 2009 23:18:03 +0000
+Subject: Fix Intel IOMMU write-buffer flushing
+
+From: David Woodhouse <dwmw2@infradead.org>
+
+commit ca77fde8e62cecb2c0769052228d15b901367af8 upstream.
+
+This is the cause of the DMA faults and disk corruption that people have
+been seeing. Some chipsets neglect to report the RWBF "capability" --
+the flag which says that we need to flush the chipset write-buffer when
+changing the DMA page tables, to ensure that the change is visible to
+the IOMMU.
+
+Override that bit on the affected chipsets, and everything is happy
+again.
+
+Thanks to Chris and Bhavesh and others for helping to debug.
+
+Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+Tested-by: Chris Wright <chrisw@sous-sol.org>
+Reviewed-by: Bhavesh Davda <bhavesh@vmware.com>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/pci/intel-iommu.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/intel-iommu.c
++++ b/drivers/pci/intel-iommu.c
+@@ -527,7 +527,7 @@ static void iommu_flush_write_buffer(str
+ u32 val;
+ unsigned long flag;
+
+- if (!cap_rwbf(iommu->cap))
++ if (!rwbf_quirk && !cap_rwbf(iommu->cap))
+ return;
+ val = iommu->gcmd | DMA_GCMD_WBF;
+
+@@ -1410,6 +1410,8 @@ static void domain_remove_dev_info(struc
+ spin_unlock_irqrestore(&device_domain_lock, flags);
+ }
+
++static int rwbf_quirk = 0;
++
+ /*
+ * find_domain
+ * Note: we use struct pci_dev->dev.archdata.iommu stores the info
+@@ -2453,3 +2455,12 @@ int __init intel_iommu_init(void)
+ return 0;
+ }
+
++static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
++{
++ /* Mobile 4 Series Chipset neglects to set RWBF capability,
++ but needs it */
++ printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
++ rwbf_quirk = 1;
++}
++
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
--- /dev/null
+From 26456dcfb8d8e43b1b64b2a14710694cf7a72f05 Mon Sep 17 00:00:00 2001
+From: Michael Neuling <mikey@neuling.org>
+Date: Thu, 12 Feb 2009 19:08:58 +0000
+Subject: powerpc/vsx: Fix VSX alignment handler for regs 32-63
+
+From: Michael Neuling <mikey@neuling.org>
+
+commit 26456dcfb8d8e43b1b64b2a14710694cf7a72f05 upstream.
+
+Fix the VSX alignment handler for VSX registers > 32. 32-63 are stored
+in the VMX part of the thread_struct not the FPR part.
+
+Signed-off-by: Michael Neuling <mikey@neuling.org>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/powerpc/kernel/align.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/powerpc/kernel/align.c
++++ b/arch/powerpc/kernel/align.c
+@@ -646,11 +646,16 @@ static int emulate_vsx(unsigned char __u
+ unsigned int areg, struct pt_regs *regs,
+ unsigned int flags, unsigned int length)
+ {
+- char *ptr = (char *) ¤t->thread.TS_FPR(reg);
++ char *ptr;
+ int ret = 0;
+
+ flush_vsx_to_thread(current);
+
++ if (reg < 32)
++ ptr = (char *) ¤t->thread.TS_FPR(reg);
++ else
++ ptr = (char *) ¤t->thread.vr[reg - 32];
++
+ if (flags & ST)
+ ret = __copy_to_user(addr, ptr, length);
+ else {
--- /dev/null
+From 7dac745b8e367c99175b8f0d014d996f0e5ed9e5 Mon Sep 17 00:00:00 2001
+From: Tejun Heo <tj@kernel.org>
+Date: Thu, 12 Feb 2009 10:34:32 +0900
+Subject: sata_nv: give up hardreset on nf2
+
+From: Tejun Heo <tj@kernel.org>
+
+commit 7dac745b8e367c99175b8f0d014d996f0e5ed9e5 upstream.
+
+Kernel bz#12176 reports that nf2 hardreset simply doesn't work. Give
+up. Argh...
+
+Signed-off-by: Tejun Heo <tj@kernel.org>
+Cc: Robert Hancock <hancockr@shaw.ca>
+Reported-by: Saro <saro_v@hotmail.it>
+Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/ata/sata_nv.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+--- a/drivers/ata/sata_nv.c
++++ b/drivers/ata/sata_nv.c
+@@ -421,19 +421,21 @@ static struct ata_port_operations nv_gen
+ .hardreset = ATA_OP_NULL,
+ };
+
+-/* OSDL bz3352 reports that nf2/3 controllers can't determine device
+- * signature reliably. Also, the following thread reports detection
+- * failure on cold boot with the standard debouncing timing.
++/* nf2 is ripe with hardreset related problems.
++ *
++ * kernel bz#3352 reports nf2/3 controllers can't determine device
++ * signature reliably. The following thread reports detection failure
++ * on cold boot with the standard debouncing timing.
+ *
+ * http://thread.gmane.org/gmane.linux.ide/34098
+ *
+- * Debounce with hotplug timing and request follow-up SRST.
++ * And bz#12176 reports that hardreset simply doesn't work on nf2.
++ * Give up on it and just don't do hardreset.
+ */
+ static struct ata_port_operations nv_nf2_ops = {
+- .inherits = &nv_common_ops,
++ .inherits = &nv_generic_ops,
+ .freeze = nv_nf2_freeze,
+ .thaw = nv_nf2_thaw,
+- .hardreset = nv_noclassify_hardreset,
+ };
+
+ /* For initial probing after boot and hot plugging, hardreset mostly
pid-implement-ns_of_pid.patch
mqueue-fix-si_pid-value-in-mqueue-do_notify.patch
+fix-intel-iommu-write-buffer-flushing.patch
+powerpc-vsx-fix-vsx-alignment-handler-for-regs-32-63.patch
+sata_nv-give-up-hardreset-on-nf2.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
