arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC

As per T7 datasheet add missing cache information to the Amlogic T7 SoC.

- Each Cortex-A53 core has 32 KB of instruction cache and
	32 KB of L1 data cache available.
- Each Cortex-A73 core has 64 KB of L1 instruction cache and
	64 KB of L1 data cache available.
- The little (A53) cluster has 256 KB of unified L2 cache available.
- The big (A73) cluster has 1 MB of unified L2 cache available.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-12-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index ec743cad57dbf99f3a4c38004f33e350c81b1d60..6510068bcff92b4b5a226855fdb94dc0b7623cec 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -53,6 +53,13 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                };
 
                cpu101: cpu@101 {
@@ -60,6 +67,13 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                };
 
                cpu102: cpu@102 {
@@ -67,6 +81,13 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                };
 
                cpu103: cpu@103 {
@@ -74,6 +95,13 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2_cache_l>;
                };
 
                cpu0: cpu@0 {
@@ -81,6 +109,13 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       d-cache-line-size = <64>;
+                       d-cache-size = <0x10000>;
+                       d-cache-sets = <64>;
+                       i-cache-line-size = <64>;
+                       i-cache-size = <0x10000>;
+                       i-cache-sets = <64>;
+                       next-level-cache = <&l2_cache_b>;
                };
 
                cpu1: cpu@1 {
@@ -88,6 +123,13 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       d-cache-line-size = <64>;
+                       d-cache-size = <0x10000>;
+                       d-cache-sets = <64>;
+                       i-cache-line-size = <64>;
+                       i-cache-size = <0x10000>;
+                       i-cache-sets = <64>;
+                       next-level-cache = <&l2_cache_b>;
                };
 
                cpu2: cpu@2 {
@@ -95,6 +137,13 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       d-cache-line-size = <64>;
+                       d-cache-size = <0x10000>;
+                       d-cache-sets = <64>;
+                       i-cache-line-size = <64>;
+                       i-cache-size = <0x10000>;
+                       i-cache-sets = <64>;
+                       next-level-cache = <&l2_cache_b>;
                };
 
                cpu3: cpu@3 {
@@ -102,6 +151,31 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       d-cache-line-size = <64>;
+                       d-cache-size = <0x10000>;
+                       d-cache-sets = <64>;
+                       i-cache-line-size = <64>;
+                       i-cache-size = <0x10000>;
+                       i-cache-sets = <64>;
+                       next-level-cache = <&l2_cache_b>;
+               };
+
+               l2_cache_l: l2-cache-cluster0 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x40000>;  /* L2. 256 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
+               };
+
+               l2_cache_b: l2-cache-cluster1 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x100000>; /* L2. 1 Mb */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };