--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Pali Rohár <pali.rohar@gmail.com>
+Date: Wed, 14 Dec 2016 22:29:44 +0100
+Subject: ARM: dts: n900: Mark eMMC slot with no-sdio and no-sd flags
+
+From: Pali Rohár <pali.rohar@gmail.com>
+
+
+[ Upstream commit 4cf48f1d7520a4d325af58eded4d8090e1b40be7 ]
+
+Trying to initialize eMMC slot as SDIO or SD cause failure in n900 port of
+qemu. eMMC itself is not detected and is not working.
+
+Real Nokia N900 harware does not have this problem. As eMMC is really not
+SDIO or SD based such change is harmless and will fix support for qemu.
+
+Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
+Acked-by: Pavel Machek <pavel@ucw.cz>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm/boot/dts/omap3-n900.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/boot/dts/omap3-n900.dts
++++ b/arch/arm/boot/dts/omap3-n900.dts
+@@ -582,6 +582,8 @@
+ vmmc_aux-supply = <&vsim>;
+ bus-width = <8>;
+ non-removable;
++ no-sdio;
++ no-sd;
+ };
+
+ &mmc3 {
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Fri, 23 Dec 2016 11:21:10 +0200
+Subject: ASoC: tlv320aic3x: Mark the RESET register as volatile
+
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+
+[ Upstream commit 63c3194b82530bd71fd49db84eb7ab656b8d404a ]
+
+The RESET register only have one self clearing bit and it should not be
+cached. If it is cached, when we sync the registers back to the chip we
+will initiate a software reset as well, which is not desirable.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ sound/soc/codecs/tlv320aic3x.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/sound/soc/codecs/tlv320aic3x.c
++++ b/sound/soc/codecs/tlv320aic3x.c
+@@ -122,6 +122,16 @@ static const struct reg_default aic3x_re
+ { 108, 0x00 }, { 109, 0x00 },
+ };
+
++static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case AIC3X_RESET:
++ return true;
++ default:
++ return false;
++ }
++}
++
+ static const struct regmap_config aic3x_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+@@ -129,6 +139,9 @@ static const struct regmap_config aic3x_
+ .max_register = DAC_ICC_ADJ,
+ .reg_defaults = aic3x_reg,
+ .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
++
++ .volatile_reg = aic3x_volatile_reg,
++
+ .cache_type = REGCACHE_RBTREE,
+ };
+
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Jordan Crouse <jcrouse@codeaurora.org>
+Date: Tue, 20 Dec 2016 08:54:29 -0700
+Subject: drm/msm: Ensure that the hardware write pointer is valid
+
+From: Jordan Crouse <jcrouse@codeaurora.org>
+
+
+[ Upstream commit 88b333b0ed790f9433ff542b163bf972953b74d3 ]
+
+Currently the value written to CP_RB_WPTR is calculated on the fly as
+(rb->next - rb->start). But as the code is designed rb->next is wrapped
+before writing the commands so if a series of commands happened to
+fit perfectly in the ringbuffer, rb->next would end up being equal to
+rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
+
+The easiest way to fix this is to mask WPTR when writing it to the
+hardware; it makes the hardware happy and the rest of the ringbuffer
+math appears to work and there isn't any point in upsetting anything.
+
+Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
+[squash in is_power_of_2() check]
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 ++++++++-
+ drivers/gpu/drm/msm/msm_ringbuffer.c | 3 ++-
+ 2 files changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+@@ -199,7 +199,14 @@ void adreno_flush(struct msm_gpu *gpu)
+ void adreno_idle(struct msm_gpu *gpu)
+ {
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+- uint32_t wptr = get_wptr(gpu->rb);
++ uint32_t wptr;
++
++ /*
++ * Mask wptr value that we calculate to fit in the HW range. This is
++ * to account for the possibility that the last command fit exactly into
++ * the ringbuffer and rb->next hasn't wrapped to zero yet
++ */
++ wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1);
+
+ /* wait for CP to drain ringbuffer: */
+ if (spin_until(adreno_gpu->memptrs->rptr == wptr))
+--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
++++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
+@@ -23,7 +23,8 @@ struct msm_ringbuffer *msm_ringbuffer_ne
+ struct msm_ringbuffer *ring;
+ int ret;
+
+- size = ALIGN(size, 4); /* size should be dword aligned */
++ if (WARN_ON(!is_power_of_2(size)))
++ return ERR_PTR(-EINVAL);
+
+ ring = kzalloc(sizeof(*ring), GFP_KERNEL);
+ if (!ring) {
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Jordan Crouse <jcrouse@codeaurora.org>
+Date: Tue, 20 Dec 2016 08:54:31 -0700
+Subject: drm/msm: Verify that MSM_SUBMIT_BO_FLAGS are set
+
+From: Jordan Crouse <jcrouse@codeaurora.org>
+
+
+[ Upstream commit a6cb3b864b21b7345f824a4faa12b723c8aaf099 ]
+
+For every submission buffer object one of MSM_SUBMIT_BO_WRITE
+and MSM_SUBMIT_BO_READ must be set (and nothing else). If we
+allowed zero then the buffer object would never get queued to
+be unreferenced.
+
+Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/msm/msm_gem_submit.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/msm/msm_gem_submit.c
++++ b/drivers/gpu/drm/msm/msm_gem_submit.c
+@@ -90,7 +90,8 @@ static int submit_lookup_objects(struct
+ pagefault_disable();
+ }
+
+- if (submit_bo.flags & ~MSM_SUBMIT_BO_FLAGS) {
++ if ((submit_bo.flags & ~MSM_SUBMIT_BO_FLAGS) ||
++ !(submit_bo.flags & MSM_SUBMIT_BO_FLAGS)) {
+ DRM_ERROR("invalid flags: %x\n", submit_bo.flags);
+ ret = -EINVAL;
+ goto out_unlock;
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Zheng Li <james.z.li@ericsson.com>
+Date: Wed, 28 Dec 2016 23:23:46 +0800
+Subject: ipv6: Should use consistent conditional judgement for ip6 fragment between __ip6_append_data and ip6_finish_output
+
+From: Zheng Li <james.z.li@ericsson.com>
+
+
+[ Upstream commit e4c5e13aa45c23692e4acf56f0b3533f328199b2 ]
+
+There is an inconsistent conditional judgement between __ip6_append_data
+and ip6_finish_output functions, the variable length in __ip6_append_data
+just include the length of application's payload and udp6 header, don't
+include the length of ipv6 header, but in ip6_finish_output use
+(skb->len > ip6_skb_dst_mtu(skb)) as judgement, and skb->len include the
+length of ipv6 header.
+
+That causes some particular application's udp6 payloads whose length are
+between (MTU - IPv6 Header) and MTU were fragmented by ip6_fragment even
+though the rst->dev support UFO feature.
+
+Add the length of ipv6 header to length in __ip6_append_data to keep
+consistent conditional judgement as ip6_finish_output for ip6 fragment.
+
+Signed-off-by: Zheng Li <james.z.li@ericsson.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ net/ipv6/ip6_output.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/net/ipv6/ip6_output.c
++++ b/net/ipv6/ip6_output.c
+@@ -1305,7 +1305,7 @@ emsgsize:
+
+ skb = skb_peek_tail(&sk->sk_write_queue);
+ cork->length += length;
+- if (((length > mtu) ||
++ if ((((length + fragheaderlen) > mtu) ||
+ (skb && skb_is_gso(skb))) &&
+ (sk->sk_protocol == IPPROTO_UDP) &&
+ (rt->dst.dev->features & NETIF_F_UFO) &&
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Leon Romanovsky <leonro@mellanox.com>
+Date: Thu, 29 Dec 2016 18:37:11 +0200
+Subject: net/mlx4: Remove BUG_ON from ICM allocation routine
+
+From: Leon Romanovsky <leonro@mellanox.com>
+
+
+[ Upstream commit c1d5f8ff80ea84768f5fae1ca9d1abfbb5e6bbaa ]
+
+This patch removes BUG_ON() macro from mlx4_alloc_icm_coherent()
+by checking DMA address alignment in advance and performing proper
+folding in case of error.
+
+Fixes: 5b0bf5e25efe ("mlx4_core: Support ICM tables in coherent memory")
+Reported-by: Ozgur Karatas <okaratas@member.fsf.org>
+Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
+Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/mellanox/mlx4/icm.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mellanox/mlx4/icm.c
++++ b/drivers/net/ethernet/mellanox/mlx4/icm.c
+@@ -117,8 +117,13 @@ static int mlx4_alloc_icm_coherent(struc
+ if (!buf)
+ return -ENOMEM;
+
++ if (offset_in_page(buf)) {
++ dma_free_coherent(dev, PAGE_SIZE << order,
++ buf, sg_dma_address(mem));
++ return -ENOMEM;
++ }
++
+ sg_set_buf(mem, buf, PAGE_SIZE << order);
+- BUG_ON(mem->offset);
+ sg_dma_len(mem) = PAGE_SIZE << order;
+ return 0;
+ }
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Chun-Hao Lin <hau@realtek.com>
+Date: Tue, 27 Dec 2016 16:29:43 +0800
+Subject: r8169: add support for RTL8168 series add-on card.
+
+From: Chun-Hao Lin <hau@realtek.com>
+
+
+[ Upstream commit 610c908773d30907c950ca3b2ee8ac4b2813537b ]
+
+This chip is the same as RTL8168, but its device id is 0x8161.
+
+Signed-off-by: Chun-Hao Lin <hau@realtek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/realtek/r8169.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/ethernet/realtek/r8169.c
++++ b/drivers/net/ethernet/realtek/r8169.c
+@@ -326,6 +326,7 @@ enum cfg_version {
+ static const struct pci_device_id rtl8169_pci_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
++ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
pstore-use-dynamic-spinlock-initializer.patch
net-skb_needs_check-accepts-checksum_none-for-tx.patch
tpm-fix-a-kernel-memory-leak-in-tpm-sysfs.c.patch
+x86-mce-amd-make-the-init-code-more-robust.patch
+r8169-add-support-for-rtl8168-series-add-on-card.patch
+arm-dts-n900-mark-emmc-slot-with-no-sdio-and-no-sd-flags.patch
+ipv6-should-use-consistent-conditional-judgement-for-ip6-fragment-between-__ip6_append_data-and-ip6_finish_output.patch
+net-mlx4-remove-bug_on-from-icm-allocation-routine.patch
+drm-msm-ensure-that-the-hardware-write-pointer-is-valid.patch
+drm-msm-verify-that-msm_submit_bo_flags-are-set.patch
+vfio-pci-use-32-bit-comparisons-for-register-address-for-gcc-4.5.patch
+asoc-tlv320aic3x-mark-the-reset-register-as-volatile.patch
+spi-dw-make-debugfs-name-unique-between-instances.patch
vlan-propagate-mac-address-to-vlans.patch
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Phil Reid <preid@electromag.com.au>
+Date: Thu, 22 Dec 2016 17:18:12 +0800
+Subject: spi: dw: Make debugfs name unique between instances
+
+From: Phil Reid <preid@electromag.com.au>
+
+
+[ Upstream commit 13288bdf4adbaa6bd1267f10044c1bc25d90ce7f ]
+
+Some system have multiple dw devices. Currently the driver uses a
+fixed name for the debugfs dir. Append dev name to the debugfs dir
+name to make it unique.
+
+Signed-off-by: Phil Reid <preid@electromag.com.au>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/spi/spi-dw.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-dw.c
++++ b/drivers/spi/spi-dw.c
+@@ -118,7 +118,10 @@ static const struct file_operations dw_s
+
+ static int dw_spi_debugfs_init(struct dw_spi *dws)
+ {
+- dws->debugfs = debugfs_create_dir("dw_spi", NULL);
++ char name[128];
++
++ snprintf(name, 128, "dw_spi-%s", dev_name(&dws->master->dev));
++ dws->debugfs = debugfs_create_dir(name, NULL);
+ if (!dws->debugfs)
+ return -ENOMEM;
+
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 30 Dec 2016 08:13:47 -0700
+Subject: vfio-pci: use 32-bit comparisons for register address for gcc-4.5
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+
+[ Upstream commit 45e869714489431625c569d21fc952428d761476 ]
+
+Using ancient compilers (gcc-4.5 or older) on ARM, we get a link
+failure with the vfio-pci driver:
+
+ERROR: "__aeabi_lcmp" [drivers/vfio/pci/vfio-pci.ko] undefined!
+
+The reason is that the compiler tries to do a comparison of
+a 64-bit range. This changes it to convert to a 32-bit number
+explicitly first, as newer compilers do for themselves.
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/vfio/pci/vfio_pci_rdwr.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/vfio/pci/vfio_pci_rdwr.c
++++ b/drivers/vfio/pci/vfio_pci_rdwr.c
+@@ -190,7 +190,10 @@ ssize_t vfio_pci_vga_rw(struct vfio_pci_
+ if (!vdev->has_vga)
+ return -EINVAL;
+
+- switch (pos) {
++ if (pos > 0xbfffful)
++ return -EINVAL;
++
++ switch ((u32)pos) {
+ case 0xa0000 ... 0xbffff:
+ count = min(count, (size_t)(0xc0000 - pos));
+ iomem = ioremap_nocache(0xa0000, 0xbffff - 0xa0000 + 1);
--- /dev/null
+From foo@baz Fri Aug 4 13:41:01 PDT 2017
+From: Thomas Gleixner <tglx@linutronix.de>
+Date: Mon, 26 Dec 2016 22:58:20 +0100
+Subject: x86/mce/AMD: Make the init code more robust
+
+From: Thomas Gleixner <tglx@linutronix.de>
+
+
+[ Upstream commit 0dad3a3014a0b9e72521ff44f17e0054f43dcdea ]
+
+If mce_device_init() fails then the mce device pointer is NULL and the
+AMD mce code happily dereferences it.
+
+Add a sanity check.
+
+Reported-by: Markus Trippelsdorf <markus@trippelsdorf.de>
+Reported-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/mcheck/mce_amd.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
+@@ -573,6 +573,9 @@ static int threshold_create_bank(unsigne
+ const char *name = th_names[bank];
+ int err = 0;
+
++ if (!dev)
++ return -ENODEV;
++
+ if (is_shared_bank(bank)) {
+ nb = node_to_amd_nb(amd_get_nb_id(cpu));
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
