/* update the per-port timeout */
uart_update_timeout(port, termios->c_cflag, baud);
+ /*
+ * disable CTS to ensure the transmit engine is not blocked by the flow
+ * control when there is dirty data in TX FIFO
+ */
+ lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
+
/*
* LPUART Transmission Complete Flag may never be set while queuing a break
* character, so skip waiting for transmission complete when UARTCTRL_SBK is
* asserted.
*/
- if (!(old_ctrl & UARTCTRL_SBK)) {
- lpuart32_write(port, 0, UARTMODIR);
+ if (!(old_ctrl & UARTCTRL_SBK))
lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC);
- }
/* disable transmit and receive */
lpuart32_write(port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
lpuart32_write(port, bd, UARTBAUD);
lpuart32_serial_setbrg(sport, baud);
- /* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */
- lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
/* restore control register */
lpuart32_write(port, ctrl, UARTCTRL);
/* re-enable the CTS if needed */