RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2...

Add asm dump check and run test for vec_duplicate + vsadd.vv
combine to vsadd.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index c86d77c3d4e6eff7db5cd20674b6183404b01e06..25652ec0e7b895960a96882445a371c49f677b18 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmax.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index f6524cb8398fa4e561d3109dc652a742fda8d0e3..cbf4e28982434c9171eddfe77024bf3baf6a8703 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmax.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index f1e8627c8d98e7c7915ab09ad76bc644e71fd404..e5519e6699fd6db6e774cebea4eb8521644fc13d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmax.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 9b0cbd29603aacbf3b1db4d793b4d53703c2b28f..beaf1741efbab15ef28c26ab0840ad2b4a950364 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vrem.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmax.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmin.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index fb1154c0ca91bbbc0494c5172b54204636b7fc7b..23c0ec9f3289c3c2f6d407f3991e1e96c9384c60 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index d4baa4ba0d715618609e4ebb42cd82fe309ac537..e5fc38ee501bf28bc1f99edac5a70cd9cc09af2d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 18c1a7897ed1fb7b6d3e4f84d4b7b6eae4c0610d..7701fc9bd1881a56fef9912485ad811d2f531386 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 5ce3c88bf7759ce0b8dc27d08c4b1e98ac75358a..4b8420478b71da85eb49b519e9b18ef243d18385 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 29659248a507f7a1de37053799dbd306319bcc24..09058a858314c72a72d2a83285f9ef699ec03a03 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index e7815e9b2806b573881a1b93c06677c5745ad74b..fa0ef4273c256430b2f7a0c81cb4883375bfd0a2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 063a7a1f86f6a70dbae1b54d08d4ac70448d24fd..7d8358ab7bc07ff3a0f36fa2c3b158c43e379e9d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 0efb60c050d77ab5fcf53cf857ee29be70fb239e..46579327b62240b63b99b6ac3a77243fdb307da2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -18,3 +18,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vrem.vx} } } */
 /* { dg-final { scan-assembler-not {vmax.vx} } } */
 /* { dg-final { scan-assembler-not {vmin.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index f12d1d144d4ca6424373e307d7463d9632a30da7..944a863300d524d0c0413740443c1de04d48cb82 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -294,26 +294,47 @@ DEF_SAT_U_SUB(uint16_t)
 DEF_SAT_U_SUB(uint32_t)
 DEF_SAT_U_SUB(uint64_t)
 
+#define DEF_SAT_S_ADD(T, UT, MIN, MAX) \
+T                                      \
+test_##T##_sat_add (T x, T y)          \
+{                                      \
+  T sum = (UT)x + (UT)y;               \
+  return (x ^ y) < 0                   \
+    ? sum                              \
+    : (sum ^ x) >= 0                   \
+      ? sum                            \
+      : x < 0 ? MIN : MAX;             \
+}
+
+DEF_SAT_S_ADD(int8_t, uint8_t, INT8_MIN, INT8_MAX)
+DEF_SAT_S_ADD(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+DEF_SAT_S_ADD(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+DEF_SAT_S_ADD(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
 #define SAT_U_ADD_FUNC(T) test_##T##_sat_add
 #define SAT_U_ADD_FUNC_WRAP(T) SAT_U_ADD_FUNC(T)
 
 #define SAT_U_SUB_FUNC(T) test_##T##_sat_sub
 #define SAT_U_SUB_FUNC_WRAP(T) SAT_U_SUB_FUNC(T)
 
-#define TEST_BINARY_VX_SIGNED_0(T)                      \
-  DEF_VX_BINARY_CASE_0_WRAP(T, +, add)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)                  \
-  DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)         \
-  DEF_VX_BINARY_CASE_0_WRAP(T, &, and)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, |, or)                   \
-  DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, /, div)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                  \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min)
+#define SAT_S_ADD_FUNC(T) test_##T##_sat_add
+#define SAT_S_ADD_FUNC_WRAP(T) SAT_S_ADD_FUNC(T)
+
+#define TEST_BINARY_VX_SIGNED_0(T)                         \
+  DEF_VX_BINARY_CASE_0_WRAP(T, +, add)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)                     \
+  DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)            \
+  DEF_VX_BINARY_CASE_0_WRAP(T, &, and)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, |, or)                      \
+  DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, /, div)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                     \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_ADD_FUNC(T), sat_add) \
 
 #define TEST_BINARY_VX_UNSIGNED_0(T)                       \
   DEF_VX_BINARY_CASE_0_WRAP(T, +, add)                     \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index f475e36c7dc94c24dacf5ee9e58ff9aee8311e1f..9020eaf18a7e2223955a56900c3f1f4f19c8a881 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -4514,4 +4514,200 @@ uint64_t TEST_BINARY_DATA(uint64_t, sat_sub)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 127 },
+    {
+       127,  127,  127,  127,
+      -128, -128, -128, -128,
+      -127, -127, -127, -127,
+         1,    1,    1,    1,
+    },
+    {
+       127,  127,  127,  127,
+        -1,   -1,   -1,   -1,
+         0,    0,    0,    0,
+       127,  127,  127,  127,
+    },
+  },
+  {
+    { -128 },
+    {
+       127,  127,  127,  127,
+        -1,   -1,   -1,   -1,
+      -128, -128, -128, -128,
+         1,    1,    1,    1,
+    },
+    {
+        -1,   -1,   -1,   -1,
+      -128, -128, -128, -128,
+      -128, -128, -128, -128,
+      -127, -127, -127, -127,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 32767 },
+    {
+       32767,  32767,  32767,  32767,
+      -32768, -32768, -32768, -32768,
+      -32767, -32767, -32767, -32767,
+           1,      1,      1,      1,
+    },
+    {
+       32767,  32767,  32767,  32767,
+          -1,     -1,     -1,     -1,
+           0,      0,      0,      0,
+       32767,  32767,  32767,  32767,
+    },
+  },
+  {
+    { -32768 },
+    {
+       32767,  32767,  32767,  32767,
+          -1,     -1,     -1,     -1,
+      -32768, -32768, -32768, -32768,
+           1,      1,      1,      1,
+    },
+    {
+          -1,     -1,     -1,     -1,
+      -32768, -32768, -32768, -32768,
+      -32768, -32768, -32768, -32768,
+      -32767, -32767, -32767, -32767,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 2147483647 },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+      -2147483647, -2147483647, -2147483647, -2147483647,
+                1,           1,           1,           1,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+               -1,          -1,          -1,          -1,
+                0,           0,           0,           0,
+       2147483647,  2147483647,  2147483647,  2147483647,
+    },
+  },
+  {
+    { -2147483648 },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+               -1,          -1,          -1,          -1,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+                1,           1,           1,           1,
+    },
+    {
+               -1,          -1,          -1,          -1,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+      -2147483647, -2147483647, -2147483647, -2147483647,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 9223372036854775807ull },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+      -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull,
+                            1,                       1,                       1,                       1,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+        -1,   -1,   -1,   -1,
+         0,    0,    0,    0,
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+    },
+  },
+  {
+    { -9223372036854775808ull },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                           -1,                      -1,                      -1,                      -1,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+                            1,                       1,                       1,                       1,
+    },
+    {
+                           -1,                      -1,                      -1,                      -1,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+      -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c
new file mode 100644 (file)
index 0000000..1f0fd46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          int16_t
+#define NAME       sat_add
+#define FUNC       SAT_S_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c
new file mode 100644 (file)
index 0000000..4a8df0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          int32_t
+#define NAME       sat_add
+#define FUNC       SAT_S_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c
new file mode 100644 (file)
index 0000000..534cd25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          int64_t
+#define NAME       sat_add
+#define FUNC       SAT_S_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c
new file mode 100644 (file)
index 0000000..de2a9b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          int8_t
+#define NAME       sat_add
+#define FUNC       SAT_S_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"