irqchip/riscv-imsic: Add kernel parameter to disable IPIs

When injecting IPIs to a set of harts, the IMSIC IPI support will do a
separate MMIO write to the SETIPNUM_LE register of each target hart. This
means on a platform where IMSIC is trap-n-emulated, there will be N MMIO
traps when injecting IPI to N target harts hence IMSIC IPIs will be slow on
such platforms compared to the SBI IPI extension.

Unfortunately, there is no DT, ACPI, or any other way of discovering
whether the underlying IMSIC is trap-n-emulated. Using MMIO write to the
SETIPNUM_LE register for injecting IPI is purely a software choice in the
IMSIC driver hence add a kernel parameter to allow users to disable IMSIC
IPIs on platforms with trap-n-emulated IMSIC.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20250716123745.557585-1-apatel@ventanamicro.com

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index f1f2c0874da9ddfc95058c464fdf5dabaf0de713..7f0e12d0d2604bc80872240745e47aa1668484ea 100644 (file)
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2538,6 +2538,13 @@
                        requires the kernel to be built with
                        CONFIG_ARM64_PSEUDO_NMI.
 
+       irqchip.riscv_imsic_noipi
+                       [RISC-V,EARLY]
+                       Force the kernel to not use IMSIC software injected MSIs
+                       as IPIs. Intended for system where IMSIC is trap-n-emulated,
+                       and thus want to reduce MMIO traps when triggering IPIs
+                       to multiple harts.
+
        irqfixup        [HW]
                        When an interrupt is not handled search all handlers
                        for it. Intended to get systems with badly broken

diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
index d9ae87808651ab190d71fdb0e5b983856fa06b58..2709cacf485524c7c617462e7673a2a2a756039f 100644 (file)
--- a/drivers/irqchip/irq-riscv-imsic-early.c
+++ b/drivers/irqchip/irq-riscv-imsic-early.c
@@ -8,6 +8,7 @@
 #include <linux/acpi.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
+#include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
@@ -21,6 +22,14 @@
 #include "irq-riscv-imsic-state.h"
 
 static int imsic_parent_irq;
+bool imsic_noipi __ro_after_init;
+
+static int __init imsic_noipi_cfg(char *buf)
+{
+       imsic_noipi = true;
+       return 0;
+}
+early_param("irqchip.riscv_imsic_noipi", imsic_noipi_cfg);
 
 #ifdef CONFIG_SMP
 static void imsic_ipi_send(unsigned int cpu)
@@ -32,12 +41,18 @@ static void imsic_ipi_send(unsigned int cpu)
 
 static void imsic_ipi_starting_cpu(void)
 {
+       if (imsic_noipi)
+               return;
+
        /* Enable IPIs for current CPU. */
        __imsic_id_set_enable(IMSIC_IPI_ID);
 }
 
 static void imsic_ipi_dying_cpu(void)
 {
+       if (imsic_noipi)
+               return;
+
        /* Disable IPIs for current CPU. */
        __imsic_id_clear_enable(IMSIC_IPI_ID);
 }
@@ -46,6 +61,9 @@ static int __init imsic_ipi_domain_init(void)
 {
        int virq;
 
+       if (imsic_noipi)
+               return 0;
+
        /* Create IMSIC IPI multiplexing */
        virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send);
        if (virq <= 0)
@@ -88,7 +106,7 @@ static void imsic_handle_irq(struct irq_desc *desc)
        while ((local_id = csr_swap(CSR_TOPEI, 0))) {
                local_id >>= TOPEI_ID_SHIFT;
 
-               if (local_id == IMSIC_IPI_ID) {
+               if (!imsic_noipi && local_id == IMSIC_IPI_ID) {
                        if (IS_ENABLED(CONFIG_SMP))
                                ipi_mux_process();
                        continue;

diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c
index 77670dd645ac38775cb2ac8280531a47168861f0..dc95ad856d80adc536c89479bdf2a11c80e8ea63 100644 (file)
--- a/drivers/irqchip/irq-riscv-imsic-state.c
+++ b/drivers/irqchip/irq-riscv-imsic-state.c
@@ -134,7 +134,7 @@ static bool __imsic_local_sync(struct imsic_local_priv *lpriv)
        lockdep_assert_held(&lpriv->lock);
 
        for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) {
-               if (!i || i == IMSIC_IPI_ID)
+               if (!i || (!imsic_noipi && i == IMSIC_IPI_ID))
                        goto skip;
                vec = &lpriv->vectors[i];
 
@@ -419,7 +419,7 @@ void imsic_vector_debug_show(struct seq_file *m, struct imsic_vector *vec, int i
        seq_printf(m, "%*starget_cpu      : %5u\n", ind, "", vec->cpu);
        seq_printf(m, "%*starget_local_id : %5u\n", ind, "", vec->local_id);
        seq_printf(m, "%*sis_reserved     : %5u\n", ind, "",
-                  (vec->local_id <= IMSIC_IPI_ID) ? 1 : 0);
+                  (!imsic_noipi && vec->local_id <= IMSIC_IPI_ID) ? 1 : 0);
        seq_printf(m, "%*sis_enabled      : %5u\n", ind, "", is_enabled ? 1 : 0);
        seq_printf(m, "%*sis_move_pending : %5u\n", ind, "", mvec ? 1 : 0);
        if (mvec) {
@@ -583,7 +583,8 @@ static int __init imsic_matrix_init(void)
        irq_matrix_assign_system(imsic->matrix, 0, false);
 
        /* Reserve IPI ID because it is special and used internally */
-       irq_matrix_assign_system(imsic->matrix, IMSIC_IPI_ID, false);
+       if (!imsic_noipi)
+               irq_matrix_assign_system(imsic->matrix, IMSIC_IPI_ID, false);
 
        return 0;
 }

diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h
index 3202ffa4e849d4cf22ddbb1bc0f32194c50707d2..57f951952b0c8b9bc31e37e378dc127f051ed756 100644 (file)
--- a/drivers/irqchip/irq-riscv-imsic-state.h
+++ b/drivers/irqchip/irq-riscv-imsic-state.h
@@ -61,6 +61,7 @@ struct imsic_priv {
        struct irq_domain                       *base_domain;
 };
 
+extern bool imsic_noipi;
 extern struct imsic_priv *imsic;
 
 void __imsic_eix_update(unsigned long base_id, unsigned long num_id, bool pend, bool val);