clk: ingenic: jz4725b: Add UDC PHY clock

Add clock for the USB Device Controller PHY.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 584ff4ff81c721b2c9a5d781c4062a3921998cb5..8901ea0295b7d2474edafaf2e6b1f769840e8af2 100644 (file)
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -205,6 +205,12 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
                .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
                .mux = { CGU_REG_OPCR, 2, 1},
        },
+
+       [JZ4725B_CLK_UDC_PHY] = {
+               "udc_phy", CGU_CLK_GATE,
+               .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+               .gate = { CGU_REG_OPCR, 6, true },
+       },
 };
 
 static void __init jz4725b_cgu_init(struct device_node *np)