drm/i915/dp: read Aux RD interval just before setting the FFE preset

Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of
DP2.1a spec.
After reading LANEx_CHANNEL_EQ_DONE, read the FFE presets.
AUX_RD_INTERVAL and then write the new FFE presets.

v4: Read AUX_RD_INTERVAL before get/set TX FFE preset (Jani)

Co-developed-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241011045825.2629469-1-arun.r.murthy@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index f41b69840ad9c9b56f5126c57753c7ae2b99b02e..a48a70ca4fb3f038f359dba6001333643fb6d74f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
        for (try = 0; try < max_tries; try++) {
                fsleep(delay_us);
 
-               /*
-                * The delay may get updated. The transmitter shall read the
-                * delay before link status during link training.
-                */
-               delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
-
                if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
                        lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
                        return false;
@@ -1451,8 +1445,15 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
                if (time_after(jiffies, deadline))
                        timeout = true; /* try one last time after deadline */
 
-               /* Update signal levels and training set as requested. */
+               /*
+                * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE
+                * presets.
+                */
+               delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
+
                intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
+
+               /* Update signal levels and training set as requested. */
                if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
                        lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
                        return false;