dt-bindings: arm: cpus: Add edac-enabled property

Some ARM Cortex CPUs including A72 have Error Detection And Correction (EDAC)
support on their L1 and L2 caches. That functionality is in implementation
defined registers, so using it is not safe in virtualized environments or when
EL3 already uses these registers. Add a edac-enabled flag which can be
explicitly set when EDAC can be used.

  [ bp: Massage commit message. ]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/1752714390-27389-3-git-send-email-vijayb@linux.microsoft.com

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 5bd517befb680548a248e30457f937f26a66ed18..4accf4cbc6c710c4940af5701e7434a62a72c84f 100644 (file)
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -353,6 +353,12 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle
     description: Link to Mediatek Cache Coherent Interconnect
 
+  edac-enabled:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      A72 CPUs support Error Detection And Correction (EDAC) on their L1 and
+      L2 caches. This flag marks this function as usable.
+
   qcom,saw:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
@@ -399,6 +405,17 @@ properties:
 allOf:
   - $ref: /schemas/cpu.yaml#
   - $ref: /schemas/opp/opp-v1.yaml#
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: arm,cortex-a72
+    then:
+      # Allow edac-enabled only for Cortex A72
+      properties:
+        edac-enabled: false
+
   - if:
       # If the enable-method property contains one of those values
       properties: