arm64: dts: qcom: x1e80100: Describe the PCIe 6a resources

On both the CRD and QCP, on PCIe 6a sits the NVMe. Add the 3.3V
gpio-controlled regulator and the clkreq, perst and wake gpios as
resources for the PCIe 6a.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-3-ee17a9939ba5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index a1f901dda92fba7848ee0539c5f8587b8a1ed51c..4c327762f001c20574b8e07b7c2802790ed65df7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -164,6 +164,20 @@
                regulator-always-on;
                regulator-boot-on;
        };
+
+       vreg_nvme: regulator-nvme {
+               compatible = "regulator-fixed";
+
+               regulator-name = "VREG_NVME_3P3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&nvme_reg_en>;
+       };
 };
 
 &apps_rsc {
@@ -646,6 +660,14 @@
 };
 
 &pcie6a {
+       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+       vddpe-3v3-supply = <&vreg_nvme>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie6a_default>;
+
        status = "okay";
 };
 
@@ -795,6 +817,36 @@
                bias-disable;
        };
 
+       nvme_reg_en: nvme-reg-en-state {
+               pins = "gpio18";
+               function = "gpio";
+               drive-strength = <2>;
+               bias-disable;
+       };
+
+       pcie6a_default: pcie2a-default-state {
+               clkreq-n-pins {
+                       pins = "gpio153";
+                       function = "pcie6a_clk";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio152";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                      pins = "gpio154";
+                      function = "gpio";
+                      drive-strength = <2>;
+                      bias-pull-up;
+              };
+       };
+
        tpad_default: tpad-default-state {
                pins = "gpio3";
                function = "gpio";

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
index 2aec8ae2bf5213ab1f4f57142d20b624a2a896e7..97c81667c6caf7e23db5b568263287b7d5c2aa69 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
@@ -50,6 +50,20 @@
                regulator-always-on;
                regulator-boot-on;
        };
+
+       vreg_nvme: regulator-nvme {
+               compatible = "regulator-fixed";
+
+               regulator-name = "VREG_NVME_3P3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&nvme_reg_en>;
+       };
 };
 
 &apps_rsc {
@@ -457,6 +471,14 @@
 };
 
 &pcie6a {
+       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+       vddpe-3v3-supply = <&vreg_nvme>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie6a_default>;
+
        status = "okay";
 };
 
@@ -519,6 +541,36 @@
                drive-strength = <16>;
                bias-disable;
        };
+
+       nvme_reg_en: nvme-reg-en-state {
+               pins = "gpio18";
+               function = "gpio";
+               drive-strength = <2>;
+               bias-disable;
+       };
+
+       pcie6a_default: pcie2a-default-state {
+               clkreq-n-pins {
+                       pins = "gpio153";
+                       function = "pcie6a_clk";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio152";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                      pins = "gpio154";
+                      function = "gpio";
+                      drive-strength = <2>;
+                      bias-pull-up;
+              };
+       };
 };
 
 &uart21 {