KVM: x86: hyper-v: Honor HV_MSR_SYNTIMER_AVAILABLE privilege bit

Synthetic timers MSRs (HV_X64_MSR_STIMER[0-3]_CONFIG,
HV_X64_MSR_STIMER[0-3]_COUNT) are only available to guest when
HV_MSR_SYNTIMER_AVAILABLE bit is exposed.

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210521095204.2161214-13-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
index 9d3aed3bebcd91200dacf3dbe8406e0fd10a34b5..787fd58593dda5abfb1328388c2ee5c97354614b 100644 (file)
--- a/arch/x86/kvm/hyperv.c
+++ b/arch/x86/kvm/hyperv.c
@@ -1236,6 +1236,16 @@ static bool hv_check_msr_access(struct kvm_vcpu_hv *hv_vcpu, u32 msr)
        case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
                return hv_vcpu->cpuid_cache.features_eax &
                        HV_MSR_SYNIC_AVAILABLE;
+       case HV_X64_MSR_STIMER0_CONFIG:
+       case HV_X64_MSR_STIMER1_CONFIG:
+       case HV_X64_MSR_STIMER2_CONFIG:
+       case HV_X64_MSR_STIMER3_CONFIG:
+       case HV_X64_MSR_STIMER0_COUNT:
+       case HV_X64_MSR_STIMER1_COUNT:
+       case HV_X64_MSR_STIMER2_COUNT:
+       case HV_X64_MSR_STIMER3_COUNT:
+               return hv_vcpu->cpuid_cache.features_eax &
+                       HV_MSR_SYNTIMER_AVAILABLE;
        default:
                break;
        }