Add check for isa 3.1 support

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index c4965a19ef7efe809d66dd1e9c2179f707227cd1..96217fb054c5c43220847373a99b08dcd01b42ba 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -28431,6 +28431,7 @@ DisResult disInstr_PPC_WRK (
    Bool      allow_DFP = False;
    Bool      allow_isa_2_07 = False;
    Bool      allow_isa_3_0  = False;
+   Bool      allow_isa_3_1  = False;
 
    /* What insn variants are we supporting today? */
    if (mode64) {
@@ -28442,6 +28443,7 @@ DisResult disInstr_PPC_WRK (
       allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC64_DFP));
       allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA2_07));
       allow_isa_3_0  = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA3_0));
+      allow_isa_3_1  = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA3_1));
    } else {
       allow_F  = (0 != (hwcaps & VEX_HWCAPS_PPC32_F));
       allow_V  = (0 != (hwcaps & VEX_HWCAPS_PPC32_V));
@@ -28451,6 +28453,7 @@ DisResult disInstr_PPC_WRK (
       allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC32_DFP));
       allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA2_07));
       allow_isa_3_0  = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA3_0));
+      allow_isa_3_1  = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA3_1));
    }
 
    /* Enable writting the OV32 and CA32 bits added with ISA3.0 */
@@ -30192,7 +30195,8 @@ DisResult disInstr_PPC ( IRSB*        irsb_IN,
 
    mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX
             | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX | VEX_HWCAPS_PPC64_DFP
-            | VEX_HWCAPS_PPC64_ISA2_07 | VEX_HWCAPS_PPC64_ISA3_0;
+            | VEX_HWCAPS_PPC64_ISA2_07 | VEX_HWCAPS_PPC64_ISA3_0
+            | VEX_HWCAPS_PPC64_ISA3_1;
 
    if (mode64) {
       vassert((hwcaps_guest & mask32) == 0);

diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index 10dbd65976fc3cfec1caa78175efdcb2b3f66d6b..93d0625800e370a989e98004c32ba395164d09d1 100644 (file)
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -7053,7 +7053,7 @@ HInstrArray* iselSB_PPC ( const IRSB* bb,
    mode64 = arch_host == VexArchPPC64;
 
    /* do some sanity checks,
-    * Note: no 32-bit support for ISA 3.0
+    * Note: no 32-bit support for ISA 3.0, ISA 3.1
     */
    mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V
             | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX | VEX_HWCAPS_PPC32_VX
@@ -7061,7 +7061,8 @@ HInstrArray* iselSB_PPC ( const IRSB* bb,
 
    mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX
             | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX | VEX_HWCAPS_PPC64_DFP
-            | VEX_HWCAPS_PPC64_ISA2_07 | VEX_HWCAPS_PPC64_ISA3_0;
+            | VEX_HWCAPS_PPC64_ISA2_07 | VEX_HWCAPS_PPC64_ISA3_0
+            | VEX_HWCAPS_PPC64_ISA3_1;
 
    if (mode64) {
       vassert((hwcaps_host & mask32) == 0);

diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index 3e788d524054ec890e4f71c52147b71ee3bb3d21..72f41998866a8d6473f66d8019f80dfe630bb0e3 100644 (file)
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1684,6 +1684,7 @@ static const HChar* show_hwcaps_ppc32 ( UInt hwcaps )
       { VEX_HWCAPS_PPC32_DFP,     "DFP"     },
       { VEX_HWCAPS_PPC32_ISA2_07, "ISA2_07" },
       { VEX_HWCAPS_PPC32_ISA3_0,  "ISA3_0"  },
+      { VEX_HWCAPS_PPC32_ISA3_1,  "ISA3_1"  },
    };
    /* Allocate a large enough buffer */
    static HChar buf[sizeof prefix + 
@@ -1715,6 +1716,7 @@ static const HChar* show_hwcaps_ppc64 ( UInt hwcaps )
       { VEX_HWCAPS_PPC64_DFP,     "DFP"     },
       { VEX_HWCAPS_PPC64_ISA2_07, "ISA2_07" },
       { VEX_HWCAPS_PPC64_ISA3_0,  "ISA3_0"  },
+      { VEX_HWCAPS_PPC64_ISA3_1,  "ISA3_1"  },
    };
    /* Allocate a large enough buffer */
    static HChar buf[sizeof prefix + 
@@ -2075,6 +2077,27 @@ static void check_hwcaps ( VexArch arch, UInt hwcaps )
                invalid_hwcaps(arch, hwcaps,
                               "ISA3_0 requires DFP capabilities\n");
          }
+
+         /* ISA3_1 requires everything else */
+         if ((hwcaps & VEX_HWCAPS_PPC64_ISA3_1) != 0) {
+            if ( !((hwcaps
+                    & VEX_HWCAPS_PPC64_ISA3_0) == VEX_HWCAPS_PPC64_ISA3_0))
+               invalid_hwcaps(arch, hwcaps,
+                          "ISA3_1 requires ISA3_0 capabilities\n");
+            if ( !((hwcaps
+                    & VEX_HWCAPS_PPC64_ISA2_07) == VEX_HWCAPS_PPC64_ISA2_07))
+               invalid_hwcaps(arch, hwcaps,
+                          "ISA3_1 requires ISA2_07 capabilities\n");
+            if ( !has_v_fx_gx)
+               invalid_hwcaps(arch, hwcaps,
+                        "ISA3_1 requires VMX and FX and GX capabilities\n");
+            if ( !(hwcaps & VEX_HWCAPS_PPC64_VX))
+               invalid_hwcaps(arch, hwcaps,
+                              "ISA3_1 requires VX capabilities\n");
+            if ( !(hwcaps & VEX_HWCAPS_PPC64_DFP))
+               invalid_hwcaps(arch, hwcaps,
+                              "ISA3_1 requires DFP capabilities\n");
+         }
          return;
       }
 

diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index 4eb97162faf85c5a250d4efbbe1d539591bf6b93..490ba06b5edc03aaba8a69d8c99a888ee32ae5e0 100644 (file)
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -112,6 +112,7 @@ typedef
 #define VEX_HWCAPS_PPC32_DFP   (1<<17) /* Decimal Floating Point (DFP) -- e.g., dadd */
 #define VEX_HWCAPS_PPC32_ISA2_07   (1<<19) /* ISA 2.07 -- e.g., mtvsrd */
 #define VEX_HWCAPS_PPC32_ISA3_0    (1<<21) /* ISA 3.0  -- e.g., cnttzw */
+#define VEX_HWCAPS_PPC32_ISA3_1    (1<<22) /* ISA 3.1  -- e.g., brh */
 
 /* ppc64: baseline capability is integer and basic FP insns */
 #define VEX_HWCAPS_PPC64_V     (1<<13) /* Altivec (VMX) */
@@ -122,6 +123,7 @@ typedef
 #define VEX_HWCAPS_PPC64_DFP   (1<<18) /* Decimal Floating Point (DFP) -- e.g., dadd */
 #define VEX_HWCAPS_PPC64_ISA2_07   (1<<20) /* ISA 2.07 -- e.g., mtvsrd */
 #define VEX_HWCAPS_PPC64_ISA3_0    (1<<22) /* ISA 3.0  -- e.g., cnttzw */
+#define VEX_HWCAPS_PPC64_ISA3_1    (1<<23) /* ISA 3.1  -- e.g., brh */
 
 /* s390x: Hardware capability encoding
 

diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
index e811ff667d600d637f233cac3b2659f1ae9c4252..365942c4f79fbaa18c48632bfbb0fbdb6d22949d 100644 (file)
--- a/coregrind/m_initimg/initimg-linux.c
+++ b/coregrind/m_initimg/initimg-linux.c
@@ -721,6 +721,7 @@ Addr setup_client_stack( void*  init_sp,
          case AT_HWCAP2:  {
             Bool auxv_2_07, hw_caps_2_07;
             Bool auxv_3_0, hw_caps_3_0;
+            Bool auxv_3_1, hw_caps_3_1;
 
            /* The HWCAP2 field may contain an arch_2_07 entry that indicates
              * if the processor is compliant with the 2.07 ISA. (i.e. Power 8
@@ -771,9 +772,27 @@ Addr setup_client_stack( void*  init_sp,
                == VEX_HWCAPS_PPC64_ISA3_0;
 
             /* Verify the PPC_FEATURE2_ARCH_3_00 setting in HWCAP2
-            * matches the setting in VEX HWCAPS.
-            */
+             * matches the setting in VEX HWCAPS.
+             */
             vg_assert(auxv_3_0 == hw_caps_3_0);
+
+            /*  Power ISA version 3.1
+                https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
+
+                64-bit ELF V? ABI specification for Power.  HWCAP2 bit pattern
+                for ISA 3.0, page ?.
+
+                ADD PUBLIC LINK WHEN AVAILABLE
+            */
+            /* ISA 3.1 */
+            auxv_3_1 = (auxv->u.a_val & 0x00040000ULL) == 0x00040000ULL;
+            hw_caps_3_1 = (vex_archinfo->hwcaps & VEX_HWCAPS_PPC64_ISA3_1)
+               == VEX_HWCAPS_PPC64_ISA3_1;
+
+            /* Verify the PPC_FEATURE2_ARCH_3_1 setting in HWCAP2
+             * matches the setting in VEX HWCAPS.
+             */
+            vg_assert(auxv_3_1 == hw_caps_3_1);
          }
 
             break;