fpga: zynqpl: Flush dcache only for non-bitstream data

In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index eabeb8aa8736ce90949d0abba2dc59510c70ee2f..e35d4921df88426e6695fba11e1bf62de59cff9d 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -541,7 +541,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
         * Flush destination address range only if image is not
         * bitstream.
         */
-       if (dstaddr != 0xFFFFFFFF)
+       if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
                flush_dcache_range((u32)dstaddr, (u32)dstaddr +
                                   roundup(dstlen << 2, ARCH_DMA_MINALIGN));