staging: rtl8723bs: include: Fix indent for switch case in rtw_security.h

This change ensures proper formatting for better readability and
maintainability.

Reported by `checkpatch.pl`:
WARNING: switch and case statements should be indented with tabs.

Signed-off-by: Sayyad Abid <sayyad.abid16@gmail.com>
Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/20240912040409.3315067-3-sayyad.abid16@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/rtl8723bs/include/rtw_security.h b/drivers/staging/rtl8723bs/include/rtw_security.h
index 953076667b4d1ebfb047e825cf666a0977f25561..74613ad9a371b12f1f586bd8da2582a30092cf19 100644 (file)
--- a/drivers/staging/rtl8723bs/include/rtw_security.h
+++ b/drivers/staging/rtl8723bs/include/rtw_security.h
@@ -191,27 +191,27 @@ do {\
 #define SET_ICE_IV_LEN(iv_len, icv_len, encrypt)\
 do {\
        switch (encrypt) {\
-               case _WEP40_:\
-               case _WEP104_:\
-                       iv_len = 4;\
-                       icv_len = 4;\
-                       break;\
-               case _TKIP_:\
-                       iv_len = 8;\
-                       icv_len = 4;\
-                       break;\
-               case _AES_:\
-                       iv_len = 8;\
-                       icv_len = 8;\
-                       break;\
-               case _SMS4_:\
-                       iv_len = 18;\
-                       icv_len = 16;\
-                       break;\
-               default:\
-                       iv_len = 0;\
-                       icv_len = 0;\
-                       break;\
+       case _WEP40_:\
+       case _WEP104_:\
+               iv_len = 4;\
+               icv_len = 4;\
+               break;\
+       case _TKIP_:\
+               iv_len = 8;\
+               icv_len = 4;\
+               break;\
+       case _AES_:\
+               iv_len = 8;\
+               icv_len = 8;\
+               break;\
+       case _SMS4_:\
+               iv_len = 18;\
+               icv_len = 16;\
+               break;\
+       default:\
+               iv_len = 0;\
+               icv_len = 0;\
+               break;\
        } \
 } while (0)