+2005-04-04 Andreas Krebbel <krebbel1@de.ibm.com>
+ Adrian Straetling <straetling@de.ibm.com>
+
+ * config/s390/2064.md ("z_mul", "z_inf"): New insn reservations.
+ * config/s390/2084.md ("x_mul_hi", "x_mul_sidi", "x_div"): Likewise.
+ * config/s390/s390.md ("imulhi", "imulsi", "imuldi"): Added to "type"
+ attribute.
+ ("imul"): Removed from "type" attribute.
+ ("*muldi3_sign", "muldi3"): Changed type to imuldi.
+ ("mulsi3/1", "mulsi3/3", "mulsi/4", "mulsidi3", "umulsidi3"):
+ Changed type to imulsi.
+ ("*mulsi3_sign", "mulsi3/2"): Changed type to imulhi.
+
2005-04-04 Richard Sandiford <rsandifo@redhat.com>
* config/mcore/mcore.h (target_flags, HARDLIT_BIT, ALIGN8_BIT, DIV_BIT)
(eq_attr "type" "jsr"))
"z_e1*5,z_wr")
+(define_insn_reservation "z_mul" 5
+ (and (eq_attr "cpu" "g5,g6,z900")
+ (eq_attr "type" "imulsi,imulhi"))
+ "z_e1*5,z_wr")
+
+(define_insn_reservation "z_inf" 10
+ (and (eq_attr "cpu" "g5,g6,z900")
+ (eq_attr "type" "idiv,imuldi"))
+ "z_e1*10,z_wr")
+
;; For everything else we check the atype flag.
(define_insn_reservation "z_int" 1
(define_insn_reservation "x_call" 5
(and (eq_attr "cpu" "z990")
(eq_attr "type" "jsr"))
- "x-e1-np*5,x-wr-np")
+ "x-e1-np*5,x-wr-np")
+
+(define_insn_reservation "x_mul_hi" 2
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "imulhi"))
+ "x-e1-np*2,x-wr-np")
+
+(define_insn_reservation "x_mul_sidi" 4
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "imulsi,imuldi"))
+ "x-e1-np*4,x-wr-np")
+
+(define_insn_reservation "x_div" 10
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "idiv"))
+ "x-e1-np*10,x-wr-np")
;;
;; Multicycle insns
;; Instruction type attribute used for scheduling.
(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
- cs,vs,store,imul,idiv,
+ cs,vs,store,idiv,
+ imulhi,imulsi,imuldi,
branch,jsr,fsimpd,fsimps,
floadd,floads,fstored, fstores,
fmuld,fmuls,fdivd,fdivs,
msgfr\t%0,%2
msgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
- (set_attr "type" "imul")])
+ (set_attr "type" "imuldi")])
(define_insn "muldi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
mghi\t%0,%h2
msg\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXY")
- (set_attr "type" "imul")])
+ (set_attr "type" "imuldi")])
;
; mulsi3 instruction pattern(s).
""
"mh\t%0,%2"
[(set_attr "op_type" "RX")
- (set_attr "type" "imul")])
+ (set_attr "type" "imulhi")])
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
ms\t%0,%2
msy\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX,RXY")
- (set_attr "type" "imul")])
+ (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
;
; mulsidi3 instruction pattern(s).
mr\t%0,%2
m\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "imul")])
+ (set_attr "type" "imulsi")])
;
; umulsidi3 instruction pattern(s).
mlr\t%0,%2
ml\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
- (set_attr "type" "imul")])
+ (set_attr "type" "imulsi")])
;
; muldf3 instruction pattern(s).