RISC-V: Add implicit dependency to the XTheadVector extension

While this dependency is not directly stated in the documentation,
the XTheadVector extension cannot work without the Zicsr extension
(the documentation does not specify CSR access instruction subset
either as in the Zkr extension or the seed CSR section in the manual).

Also, making an implication to the Zicsr extension is in parity with
the ratified vector extensions (in GNU Binutils, the Zve32x extension --
a dependency of V -- depends on the Zvl32b and Zicsr extensions).

This commit adds this implicit dependency.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implicit
	dependency "XTheadVector" -> "Zicsr".

gas/ChangeLog:

	* testsuite/gas/riscv/imply.s: Add implicit "XTheadVector"
	dependency to the "Zicsr" extension.
	* testsuite/gas/riscv/imply.d: Ditto.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cdcbcd7a29b7130d727c538d7ba0c762167da43b..2487beeecc5659aa882e52c7f50f3704121bf5b2 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1206,6 +1206,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"xsfvqmaccdod", "+zve32x,+zvl128b", check_implicit_always},
   {"xsfvfnrclipxfqf", "+zve32f", check_implicit_always},
 
+  {"xtheadvector", "+zicsr", check_implicit_always},
+
   {"v", "+zve64d,+zvl128b", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
   {"zvfhmin", "+zve32f", check_implicit_always},

diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index bce97ddf471a1bbc72e48a71a01593ec0269c407..58f13e488cfe5bb17fb810ac98bd3c8692cf310f 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -22,6 +22,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfvfnrclipxfqf1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_xtheadvector1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0

diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index c047ed6b758ea183557e0669f9aa93aa90b9f06e..fc5cd5007754d4937c6ba88516e11ce28644fc67 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -25,6 +25,8 @@ imply xsfvqmaccqoq
 imply xsfvqmaccdod
 imply xsfvfnrclipxfqf
 
+imply xtheadvector
+
 imply v
 imply zvfh
 imply zvfhmin