can: rcar_canfd: Use devm_clk_get_optional() for RAM clk

Replace devm_clk_get_optional_enabled()->devm_clk_get_optional() as the
RAM clk needs to be enabled in resume for proper operation in STR mode
for RZ/G3E SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251124102837.106973-4-biju.das.jz@bp.renesas.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index 15358eefa8fa37657ed6013afb7125eafda21863..3f71adce6f560ff65c2b393da788c6184dcfc63b 100644 (file)
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -468,6 +468,7 @@ struct rcar_canfd_global {
        struct platform_device *pdev;   /* Respective platform device */
        struct clk *clkp;               /* Peripheral clock */
        struct clk *can_clk;            /* fCAN clock */
+       struct clk *clk_ram;            /* Clock RAM */
        unsigned long channels_mask;    /* Enabled channels mask */
        bool extclk;                    /* CANFD or Ext clock */
        bool fdmode;                    /* CAN FD or Classical CAN only mode */
@@ -1975,7 +1976,6 @@ static int rcar_canfd_probe(struct platform_device *pdev)
        u32 rule_entry = 0;
        bool fdmode = true;                     /* CAN FD only mode - default */
        char name[9] = "channelX";
-       struct clk *clk_ram;
        int i;
 
        info = of_device_get_match_data(dev);
@@ -2065,10 +2065,10 @@ static int rcar_canfd_probe(struct platform_device *pdev)
                gpriv->extclk = gpriv->info->external_clk;
        }
 
-       clk_ram = devm_clk_get_optional_enabled(dev, "ram_clk");
-       if (IS_ERR(clk_ram))
-               return dev_err_probe(dev, PTR_ERR(clk_ram),
-                                    "cannot get enabled ram clock\n");
+       gpriv->clk_ram = devm_clk_get_optional(dev, "ram_clk");
+       if (IS_ERR(gpriv->clk_ram))
+               return dev_err_probe(dev, PTR_ERR(gpriv->clk_ram),
+                                    "cannot get ram clock\n");
 
        addr = devm_platform_ioremap_resource(pdev, 0);
        if (IS_ERR(addr)) {
@@ -2134,10 +2134,18 @@ static int rcar_canfd_probe(struct platform_device *pdev)
                goto fail_reset;
        }
 
+       /* Enable RAM clock  */
+       err = clk_prepare_enable(gpriv->clk_ram);
+       if (err) {
+               dev_err(dev, "failed to enable RAM clock: %pe\n",
+                       ERR_PTR(err));
+               goto fail_clk;
+       }
+
        err = rcar_canfd_reset_controller(gpriv);
        if (err) {
                dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err));
-               goto fail_clk;
+               goto fail_ram_clk;
        }
 
        /* Controller in Global reset & Channel reset mode */
@@ -2189,6 +2197,8 @@ fail_channel:
                rcar_canfd_channel_remove(gpriv, ch);
 fail_mode:
        rcar_canfd_disable_global_interrupts(gpriv);
+fail_ram_clk:
+       clk_disable_unprepare(gpriv->clk_ram);
 fail_clk:
        clk_disable_unprepare(gpriv->clkp);
 fail_reset:
@@ -2213,6 +2223,7 @@ static void rcar_canfd_remove(struct platform_device *pdev)
 
        /* Enter global sleep mode */
        rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
+       clk_disable_unprepare(gpriv->clk_ram);
        clk_disable_unprepare(gpriv->clkp);
        reset_control_assert(gpriv->rstc2);
        reset_control_assert(gpriv->rstc1);