drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS

The MTL+ pipe DMC clock gating bits can be parametrized.
Make it so.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-3-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1d748b9dca443bd98d1888ca4e3039adf864b668..ef61870b882912b1284dcab3d4d8aa3788215331 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -483,7 +483,8 @@ static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
         * for pipe A and B.
         */
        intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,
-                    MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
+                    MTL_PIPEDMC_GATING_DIS(PIPE_A) |
+                    MTL_PIPEDMC_GATING_DIS(PIPE_B));
 }
 
 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a902532e6f7d9cabff5f105a93202ec994ccea..04fb40867cc05005f5730319ecf69bbe4b401183 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -763,8 +763,7 @@
  */
 #define GEN9_CLKGATE_DIS_0             _MMIO(0x46530)
 #define   DARBF_GATING_DIS             REG_BIT(27)
-#define   MTL_PIPEDMC_GATING_DIS_A     REG_BIT(15)
-#define   MTL_PIPEDMC_GATING_DIS_B     REG_BIT(14)
+#define   MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
 #define   PWM2_GATING_DIS              REG_BIT(14)
 #define   PWM1_GATING_DIS              REG_BIT(13)