]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
x86/mce/inject: Only write MCA_MISC when a value has been supplied
authorYazen Ghannam <yazen.ghannam@amd.com>
Thu, 23 May 2024 15:56:33 +0000 (10:56 -0500)
committerBorislav Petkov (AMD) <bp@alien8.de>
Mon, 27 May 2024 08:42:35 +0000 (10:42 +0200)
The MCA_MISC register is used to control the MCA thresholding feature on
AMD systems. Therefore, it is not generally part of the error state that
a user would adjust when testing non-thresholding cases.

However, MCA_MISC is unconditionally written even if a user does not
supply a value. The default value of '0' will be used and clobber the
register.

Write the MCA_MISC register only if the user has given a value for it.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20240523155641.2805411-2-yazen.ghannam@amd.com
arch/x86/kernel/cpu/mce/inject.c

index 94953d749475d025dd64efe5414a4cdbf83a63e4..8d18074534fffe82d7755b426bea8fb114276b18 100644 (file)
@@ -487,12 +487,16 @@ static void prepare_msrs(void *info)
                        wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr);
                }
 
-               wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);
                wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd);
+
+               if (m.misc)
+                       wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);
        } else {
                wrmsrl(MSR_IA32_MCx_STATUS(b), m.status);
                wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr);
-               wrmsrl(MSR_IA32_MCx_MISC(b), m.misc);
+
+               if (m.misc)
+                       wrmsrl(MSR_IA32_MCx_MISC(b), m.misc);
        }
 }