drm/i915/dsb: Introduce intel_dsb_exec_time_us()

Pull the magic 20 usec DSB execution deadline into
intel_dsb_arm_exec_time_us(), and also add its counterpart
for the non-arming register write section. For the non-arming
part we'll just throw in a random 80 usec for now so the total
is 100usec. The total exec time will be needed by the upcoming
flip queue code.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-4-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 50d8c4900644a9642a4f6850ec01a5cfc5a1c8ab..06a615d36a86d17b55bdba263c3a7adedccb9946 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -685,14 +685,36 @@ static u32 dsb_error_int_en(struct intel_display *display)
        return errors;
 }
 
+/*
+ * FIXME calibrate these sensibly, ideally compute based on
+ * the number of regisetrs to be written. But that requires
+ * measuring the actual DSB execution speed on each platform
+ * (and the speed also depends on CDCLK and memory clock)...
+ */
+static int intel_dsb_noarm_exec_time_us(void)
+{
+       return 80;
+}
+
+static int intel_dsb_arm_exec_time_us(void)
+{
+       return 20;
+}
+
+int intel_dsb_exec_time_us(void)
+{
+       return intel_dsb_noarm_exec_time_us() +
+               intel_dsb_arm_exec_time_us();
+}
+
 void intel_dsb_vblank_evade(struct intel_atomic_state *state,
                            struct intel_dsb *dsb)
 {
        struct intel_crtc *crtc = dsb->crtc;
        const struct intel_crtc_state *crtc_state =
                intel_pre_commit_crtc_state(state, crtc);
-       /* FIXME calibrate sensibly */
-       int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20);
+       int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
+                                              intel_dsb_arm_exec_time_us());
        int start, end;
 
        /*

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index ab64897498666e92d8b9490847ab38c05f91b5c7..6bcfb03f3415c53246fc6d31737bee9e0a2f6ef2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -35,6 +35,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
 void intel_dsb_finish(struct intel_dsb *dsb);
 void intel_dsb_gosub_finish(struct intel_dsb *dsb);
 void intel_dsb_cleanup(struct intel_dsb *dsb);
+int intel_dsb_exec_time_us(void);
 void intel_dsb_reg_write(struct intel_dsb *dsb,
                         i915_reg_t reg, u32 val);
 void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,