Enable fsqrt

Document store fp single-precision problem

git-svn-id: svn://svn.valgrind.org/vex/trunk@1492

diff --git a/VEX/priv/guest-ppc32/toIR.c b/VEX/priv/guest-ppc32/toIR.c
index b5f7acfe1eaf78fa9e486ba09a8815e3ba1f4b95..696ea85a78cb06f55c50c296797be9961860e48a 100644 (file)
--- a/VEX/priv/guest-ppc32/toIR.c
+++ b/VEX/priv/guest-ppc32/toIR.c
@@ -5584,6 +5584,10 @@ static Bool dis_fp_store ( UInt theInstr )
    case 0x34: // stfs (Store Float Single, PPC32 p518)
       DIP("stfs fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
       assign( EA, ea_rAor0_simm(rA_addr, simm16) );
+      /* TODO
+         This implementation ends up rounding twice, losing accuracy.
+         - first via F64toF32, and then by the backend fp store (stfs)
+      */
       storeBE( mkexpr(EA),
                binop(Iop_F64toF32, get_roundingmode(), mkexpr(frS)) );
       break;
@@ -5595,6 +5599,7 @@ static Bool dis_fp_store ( UInt theInstr )
       }
       DIP("stfsu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
       assign( EA, ea_rA_simm(rA_addr, simm16) );
+      /* This implementation loses accuracy - see note for stfs */
       storeBE( mkexpr(EA),
                binop(Iop_F64toF32, get_roundingmode(), mkexpr(frS)) );
       putIReg( rA_addr, mkexpr(EA) );
@@ -5627,6 +5632,7 @@ static Bool dis_fp_store ( UInt theInstr )
       case 0x297: // stfsx (Store Float Single Indexed, PPC32 p521)
          DIP("stfsx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
          assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+         /* This implementation loses accuracy - see note for stfs */
          storeBE( mkexpr(EA),
                   binop(Iop_F64toF32, get_roundingmode(), mkexpr(frS)) );
          break;
@@ -5638,6 +5644,7 @@ static Bool dis_fp_store ( UInt theInstr )
          }
          DIP("stfsux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
          assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+         /* This implementation loses accuracy - see note for stfs */
          storeBE( mkexpr(EA),
                   binop(Iop_F64toF32, get_roundingmode(), mkexpr(frS)) );
          putIReg( rA_addr, mkexpr(EA) );
@@ -5810,15 +5817,15 @@ static Bool dis_fp_arith ( UInt theInstr )
          assign( frD, binop( Iop_AddF64, mkexpr(frA), mkexpr(frB) ) );
          break;
 
-//zz       case 0x16: // fsqrt (Floating SqRt (Double-Precision), PPC32 p427)
-//zz          if (frA_addr != 0 || frC_addr != 0) {
-//zz             vex_printf("dis_fp_arith(PPC32)(instr,fsqrt)\n");
-//zz             return False;
-//zz          }
-//zz          DIP("fsqrt%s fr%u,fr%u\n", flag_rC ? "." : "",
-//zz              frD_addr, frB_addr);
-//zz          assign( frD, unop( Iop_SqrtF64, mkexpr(frB) ) );
-//zz          break;
+      case 0x16: // fsqrt (Floating SqRt (Double-Precision), PPC32 p427)
+         if (frA_addr != 0 || frC_addr != 0) {
+            vex_printf("dis_fp_arith(PPC32)(instr,fsqrt)\n");
+            return False;
+         }
+         DIP("fsqrt%s fr%u,fr%u\n", flag_rC ? "." : "",
+             frD_addr, frB_addr);
+         assign( frD, unop( Iop_SqrtF64, mkexpr(frB) ) );
+         break;
 
       case 0x17: { // fsel (Floating Select, PPC32 p426)
          IRTemp cc    = newTemp(Ity_I32);