drm/amd/display: Share dce100_validate_bandwidth with DCE6-8

DCE6-8 have very similar capabilities to DCE10, they support the
same DP and HDMI versions and work similarly.

Share dce100_validate_bandwidth between DCE6-10 to reduce code
duplication in the DC driver.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index f36ec4edf0aec4a1f319de9983d3205e3e0a3ca8..6421a56ffd23c7eacf67d7abb67031979581d505 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -837,7 +837,7 @@ static enum dc_status build_mapped_resource(
        return DC_OK;
 }
 
-static enum dc_status dce100_validate_bandwidth(
+enum dc_status dce100_validate_bandwidth(
        struct dc  *dc,
        struct dc_state *context,
        enum dc_validate_mode validate_mode)
@@ -862,7 +862,16 @@ static enum dc_status dce100_validate_bandwidth(
                context->bw_ctx.bw.dce.dispclk_khz = 681000;
                context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
        } else {
-               context->bw_ctx.bw.dce.dispclk_khz = 0;
+               /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and
+                * the DP clock, and shouldn't be turned off. Just select the display
+                * clock value from its low power mode.
+                */
+               if (dc->ctx->dce_version == DCE_VERSION_6_0 ||
+                       dc->ctx->dce_version == DCE_VERSION_6_4)
+                       context->bw_ctx.bw.dce.dispclk_khz = 352000;
+               else
+                       context->bw_ctx.bw.dce.dispclk_khz = 0;
+
                context->bw_ctx.bw.dce.yclk_khz = 0;
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h
index fecab7c560f5ba161a3df58bf2ce4b0c64db7fa7..08e045601a770ed0c975c5ea842031aff97427fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h
@@ -41,6 +41,11 @@ struct resource_pool *dce100_create_resource_pool(
 
 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);
 
+enum dc_status dce100_validate_bandwidth(
+               struct dc  *dc,
+               struct dc_state *context,
+               enum dc_validate_mode validate_mode);
+
 enum dc_status dce100_add_stream_to_ctx(
                struct dc *dc,
                struct dc_state *new_ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
index b5433349fc7a6a43e1599f3af3d64286a29eb10d..61ad3703461e94e11310c82cd719e00c56c08316 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
@@ -864,47 +864,6 @@ static void dce60_resource_destruct(struct dce110_resource_pool *pool)
        }
 }
 
-static enum dc_status dce60_validate_bandwidth(
-       struct dc *dc,
-       struct dc_state *context,
-       enum dc_validate_mode validate_mode)
-{
-       int i;
-       bool at_least_one_pipe = false;
-       struct dc_stream_state *stream = NULL;
-       const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
-
-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
-               stream = context->res_ctx.pipe_ctx[i].stream;
-               if (stream) {
-                       at_least_one_pipe = true;
-
-                       if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
-                               return DC_FAIL_BANDWIDTH_VALIDATE;
-               }
-       }
-
-       if (at_least_one_pipe) {
-               /* TODO implement when needed but for now hardcode max value*/
-               context->bw_ctx.bw.dce.dispclk_khz = 681000;
-               context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
-       } else {
-               /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and
-                * the DP clock, and shouldn't be turned off. Just select the display
-                * clock value from its low power mode.
-                */
-               if (dc->ctx->dce_version == DCE_VERSION_6_0 ||
-                       dc->ctx->dce_version == DCE_VERSION_6_4)
-                       context->bw_ctx.bw.dce.dispclk_khz = 352000;
-               else
-                       context->bw_ctx.bw.dce.dispclk_khz = 0;
-
-               context->bw_ctx.bw.dce.yclk_khz = 0;
-       }
-
-       return DC_OK;
-}
-
 static bool dce60_validate_surface_sets(
                struct dc_state *context)
 {
@@ -948,7 +907,7 @@ static const struct resource_funcs dce60_res_pool_funcs = {
        .destroy = dce60_destroy_resource_pool,
        .link_enc_create = dce60_link_encoder_create,
        .panel_cntl_create = dce60_panel_cntl_create,
-       .validate_bandwidth = dce60_validate_bandwidth,
+       .validate_bandwidth = dce100_validate_bandwidth,
        .validate_plane = dce100_validate_plane,
        .add_stream_to_ctx = dce100_add_stream_to_ctx,
        .validate_global = dce60_validate_global,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
index 538eafea82d5f1baafe24602564ee67dc7280a50..0c9a39bf7ff4f1254728359afe551be756ee270c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
@@ -870,38 +870,6 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool)
        }
 }
 
-static enum dc_status dce80_validate_bandwidth(
-       struct dc *dc,
-       struct dc_state *context,
-       enum dc_validate_mode validate_mode)
-{
-       int i;
-       bool at_least_one_pipe = false;
-       struct dc_stream_state *stream = NULL;
-       const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
-
-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
-               stream = context->res_ctx.pipe_ctx[i].stream;
-               if (stream) {
-                       at_least_one_pipe = true;
-
-                       if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
-                               return DC_FAIL_BANDWIDTH_VALIDATE;
-               }
-       }
-
-       if (at_least_one_pipe) {
-               /* TODO implement when needed but for now hardcode max value*/
-               context->bw_ctx.bw.dce.dispclk_khz = 681000;
-               context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
-       } else {
-               context->bw_ctx.bw.dce.dispclk_khz = 0;
-               context->bw_ctx.bw.dce.yclk_khz = 0;
-       }
-
-       return DC_OK;
-}
-
 static bool dce80_validate_surface_sets(
                struct dc_state *context)
 {
@@ -945,7 +913,7 @@ static const struct resource_funcs dce80_res_pool_funcs = {
        .destroy = dce80_destroy_resource_pool,
        .link_enc_create = dce80_link_encoder_create,
        .panel_cntl_create = dce80_panel_cntl_create,
-       .validate_bandwidth = dce80_validate_bandwidth,
+       .validate_bandwidth = dce100_validate_bandwidth,
        .validate_plane = dce100_validate_plane,
        .add_stream_to_ctx = dce100_add_stream_to_ctx,
        .validate_global = dce80_validate_global,