]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
wifi: iwlwifi: rename bits in config/boot control register
authorJohannes Berg <johannes.berg@intel.com>
Sat, 28 Dec 2024 20:34:07 +0000 (22:34 +0200)
committerJohannes Berg <johannes.berg@intel.com>
Mon, 13 Jan 2025 14:26:39 +0000 (15:26 +0100)
The register 0x000 is now really boot control, and some
of the old bit names were (even for old hardware) not
reflecting the names on the hardware side; rename them
in the driver to align the naming.

Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
Link: https://patch.msgid.link/20241228223206.6f25be160619.I3ffc9601e99dc414a9ae54a0d90c9d20c0253da5@changeid
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c
drivers/net/wireless/intel/iwlwifi/iwl-csr.h
drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c
drivers/net/wireless/intel/iwlwifi/pcie/trans.c

index 931aa3f5798d52e2e1f23614ce9a684b11a0cae5..cdc05f7e75a6187ba8234bf8b190c143f8f8a57e 100644 (file)
@@ -676,12 +676,12 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
        for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) {
                /* Request semaphore */
                iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                           CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
+                           CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
 
                /* See if we got it */
                ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
-                               CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
-                               CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
+                               CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
+                               CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
                                IWL_EEPROM_SEM_TIMEOUT);
                if (ret >= 0) {
                        IWL_DEBUG_EEPROM(trans->dev,
@@ -697,7 +697,7 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
 {
        iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
-                     CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
+                     CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
 }
 
 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
index 98563757ce2c9d680e5baddc25bf2384769f44b8..c2cd5c24646bffd01133ba396e1a63d01da81ec3 100644 (file)
 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH      (12)
 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP      (14)
 
-#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A  (0x00080000)
-#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM        (0x00200000)
-#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY     (0x00400000) /* PCI_OWN_SEM */
-#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
-#define CSR_HW_IF_CONFIG_REG_PREPARE             (0x08000000) /* WAKE_ME */
-#define CSR_HW_IF_CONFIG_REG_ENABLE_PME                  (0x10000000)
-#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE        (0x40000000) /* PERSISTENCE */
+#define CSR_HW_IF_CONFIG_REG_HAP_WAKE                  0x00080000
+/* NOTE: EEPROM_OWN_SEM is no longer defined for new HW */
+#define CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM            0x00200000
+#define CSR_HW_IF_CONFIG_REG_PCI_OWN_SET               0x00400000
+#define CSR_HW_IF_CONFIG_REG_ME_OWN                    0x02000000
+#define CSR_HW_IF_CONFIG_REG_WAKE_ME                   0x08000000
+#define CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN     0x10000000
+#define CSR_HW_IF_CONFIG_REG_PERSISTENCE               0x40000000
 
 #define CSR_MBOX_SET_REG_OS_ALIVE              BIT(5)
 
index 5f6cd60b50b95d75a99f1db66bfc58a0fa526704..3677e015488888a341ade84470b101b6546ea2f5 100644 (file)
@@ -43,7 +43,7 @@ int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
         * wake device's PCI Express link L1a -> L0s
         */
        iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                   CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
+                   CSR_HW_IF_CONFIG_REG_HAP_WAKE);
 
        iwl_pcie_apm_config(trans);
 
@@ -68,8 +68,8 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
                iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
                            CSR_RESET_LINK_PWR_MGMT_DISABLED);
                iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                           CSR_HW_IF_CONFIG_REG_PREPARE |
-                           CSR_HW_IF_CONFIG_REG_ENABLE_PME);
+                           CSR_HW_IF_CONFIG_REG_WAKE_ME |
+                           CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
                mdelay(1);
                iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
                              CSR_RESET_LINK_PWR_MGMT_DISABLED);
index 86f1d87a909c5c0d66c8df7b6dd59ae5a52e56c7..053f0ac756be2ea378c800f6a79b188b151cf544 100644 (file)
@@ -311,7 +311,7 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
         * wake device's PCI Express link L1a -> L0s
         */
        iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                   CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
+                   CSR_HW_IF_CONFIG_REG_HAP_WAKE);
 
        iwl_pcie_apm_config(trans);
 
@@ -439,7 +439,7 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
         * SHRD_HW_RST is applied in S3.
         */
        iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                   CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
+                   CSR_HW_IF_CONFIG_REG_PERSISTENCE);
 
        /*
         * Clear "initialization complete" bit to move adapter from
@@ -508,8 +508,8 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
                        iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
                                    CSR_RESET_LINK_PWR_MGMT_DISABLED);
                        iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                                   CSR_HW_IF_CONFIG_REG_PREPARE |
-                                   CSR_HW_IF_CONFIG_REG_ENABLE_PME);
+                                   CSR_HW_IF_CONFIG_REG_WAKE_ME |
+                                   CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
                        mdelay(1);
                        iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
                                      CSR_RESET_LINK_PWR_MGMT_DISABLED);
@@ -581,12 +581,12 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
        int ret;
 
        iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
+                   CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);
 
        /* See if we got it */
        ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
-                          CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
-                          CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
+                          CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
+                          CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
                           HW_READY_TIMEOUT);
 
        if (ret >= 0)
@@ -620,7 +620,7 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 
                /* If HW is not ready, prepare the conditions to check again */
                iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                           CSR_HW_IF_CONFIG_REG_PREPARE);
+                           CSR_HW_IF_CONFIG_REG_WAKE_ME);
 
                do {
                        ret = iwl_pcie_set_hw_ready(trans);
@@ -1566,7 +1566,7 @@ int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset)
        if (!reset)
                /* Enable persistence mode to avoid reset */
                iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-                           CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
+                           CSR_HW_IF_CONFIG_REG_PERSISTENCE);
 
        ret = iwl_pcie_d3_handshake(trans, true);
        if (ret)