break;
case 0x6f:
chip->name = "acp_asoc_rembrandt";
+ chip->rsrc = &rmb_rsrc;
chip->acp_hw_ops_init = acp6x_hw_ops_init;
chip->machines = snd_soc_acpi_amd_rmb_acp_machines;
break;
#define MP1_C2PMSG_85 0x3B10A54
#define MP1_C2PMSG_93 0x3B10A74
-static struct acp_resource rsrc = {
- .offset = 0,
- .no_of_ctrls = 2,
- .irqp_used = 1,
- .soc_mclk = true,
- .irq_reg_offset = 0x1a00,
- .scratch_reg_offset = 0x12800,
- .sram_pte_offset = 0x03802800,
-};
-
static struct snd_soc_dai_driver acp_rmb_dai[] = {
{
.name = "acp-i2s-sp",
}
chip->dev = dev;
- chip->rsrc = &rsrc;
chip->dai_driver = acp_rmb_dai;
chip->num_dai = ARRAY_SIZE(acp_rmb_dai);
- if (chip->is_i2s_config && rsrc.soc_mclk) {
+ if (chip->is_i2s_config && chip->rsrc->soc_mclk) {
ret = acp6x_master_clock_generate(dev);
if (ret)
return ret;
ACP_CONFIG_20,
};
+struct acp_resource rmb_rsrc = {
+ .offset = 0,
+ .no_of_ctrls = 2,
+ .irqp_used = 1,
+ .soc_mclk = true,
+ .irq_reg_offset = 0x1a00,
+ .scratch_reg_offset = 0x12800,
+ .sram_pte_offset = 0x03802800,
+};
+
struct acp_resource acp63_rsrc = {
.offset = 0,
.no_of_ctrls = 2,