testsuite: RISC-V: Fix vector flags handling [PR117603]

The DejaGnu routine "riscv_get_arch" fails to infer the correct
architecture string when GCC is built for RV32EC.  This causes invalid
architecture string to be produced by "add_options_for_riscv_v":
  xgcc: error: '-march=rv32cv': first ISA subset must be 'e', 'i' or 'g'

Fix by adding the E base ISA variant to the list of possible architecture
modifiers.

Also, the V extension is added to the machine string without checking
whether dependent extensions are available.  This results in errors when
GCC is built for RV32EC:
  Executing on host: .../xgcc ... -march=rv32ecv ...
  cc1: error: ILP32E ABI does not support the 'D' extension
  cc1: sorry, unimplemented: Currently the 'V' implementation requires the 'M' extension

Fix by disabling vector tests for RISC-V if V extension cannot be added
to current architecture.

Tested riscv32-none-elf for -march=rv32ec using GNU simulator.  Most of
the remaining failures are due to explicit addition of vector options,
yet missing "dg-require-effective-target riscv_v_ok":

                === gcc Summary ===

 # of expected passes            211958
 # of unexpected failures        1826
 # of expected failures          1059
 # of unresolved testcases       5209
 # of unsupported tests          15513

Ensured riscv64-unknown-linux-gnu tested with qemu has no new passing or
failing tests, before and after applying this patch:

 Running target riscv-sim/-march=rv64imafdc/-mabi=lp64d/-mcmodel=medlow
 ...
                === gcc Summary ===

 # of expected passes            237209
 # of unexpected failures        335
 # of expected failures          1670
 # of unresolved testcases       43
 # of unsupported tests          16767

	PR target/117603

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp (riscv_get_arch): Add comment about
	function purpose.  Add E ISA to list of possible
	modifiers.
	(check_vect_support_and_set_flags): Do not advertise vector
	support if V extension cannot be enabled.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f38287939865fe242fbde2757d9f66c46c16e45d..d550f288a0fa370a1fd857e5cc2caf413d851ff5 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2201,10 +2201,13 @@ proc check_effective_target_riscv_v_misalign_ok { } {
     return 0
 }
 
+# Deduce the string for the RISC-V architecture targeted by the compiler
+# under test.  Also take into account the global compiler flags passed
+# by testsuite.
 proc riscv_get_arch { } {
     set gcc_march ""
     # ??? do we neeed to add more extensions to the list below?
-    foreach ext { i m a f d q c b v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc zabha zacas } {
+    foreach ext { i e m a f d q c b v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc zabha zacas } {
        if { [check_no_compiler_messages  riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
                #ifndef DEF
                #error "Not DEF"
@@ -12056,12 +12059,16 @@ proc check_vect_support_and_set_flags { } {
            if [check_effective_target_riscv_v_misalign_ok] {
                lappend DEFAULT_VECTCFLAGS "-mno-vector-strict-align"
            }
-       } else {
+       } elseif [check_effective_target_riscv_v_ok] {
            foreach item [add_options_for_riscv_v ""] {
                lappend DEFAULT_VECTCFLAGS $item
            }
            set dg-do-what-default compile
-       }
+       } else {
+           # Current architecture cannot support vectors (e.g. the
+           # dependent D extension is missing).
+           return 0
+        }
     } elseif [istarget loongarch*-*-*] {
       # Set the default vectorization option to "-mlsx" due to the problem
       # of non-aligned memory access when using 256-bit vectorization.