arm64: dts: rockchip: Add display subsystem for RK3368

Add vop and display-subsystem nodes to RK3368's device tree.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 73618df7a889882f5a70f2454d723408118f94f3..9761dfc888561f597ef6336510b0d2c58e7f3519 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -140,6 +140,12 @@
                };
        };
 
+       display_subsystem: display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vop_out>;
+               status = "disabled";
+       };
+
        arm-pmu {
                compatible = "arm,cortex-a53-pmu";
                interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
@@ -847,6 +853,25 @@
                status = "disabled";
        };
 
+       vop: vop@ff930000 {
+               compatible = "rockchip,rk3368-vop";
+               reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+               assigned-clock-rates = <400000000>, <200000000>;
+               clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               iommus = <&vop_mmu>;
+               resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+               reset-names = "axi", "ahb", "dclk";
+               status = "disabled";
+
+               vop_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+
        vop_mmu: iommu@ff930300 {
                compatible = "rockchip,iommu";
                reg = <0x0 0xff930300 0x0 0x100>;