"aclk_vio_noc",
/* ddrc */
- "sclk_ddrc"
+ "sclk_ddrc",
+
+ "armclkl",
+ "armclkb",
};
static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
rockchip_clk_register_branches(ctx, rk3399_clk_branches,
ARRAY_SIZE(rk3399_clk_branches));
- rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
- ARRAY_SIZE(rk3399_cru_critical_clocks));
-
rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
&rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
&rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
ARRAY_SIZE(rk3399_cpuclkb_rates));
+ rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
+ ARRAY_SIZE(rk3399_cru_critical_clocks));
+
rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);